2 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org>
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <sys/cdefs.h>
18 __FBSDID("$FreeBSD$");
19 #include <sys/param.h>
20 #include <sys/sockio.h>
21 #include <sys/sysctl.h>
23 #include <sys/mutex.h>
25 #include <sys/kernel.h>
26 #include <sys/socket.h>
27 #include <sys/systm.h>
28 #include <sys/malloc.h>
29 #include <sys/module.h>
31 #include <sys/endian.h>
34 #include <machine/bus.h>
35 #include <machine/resource.h>
39 #include <net/if_arp.h>
40 #include <net/ethernet.h>
41 #include <net/if_dl.h>
42 #include <net/if_media.h>
43 #include <net/if_types.h>
46 #include <netinet/in.h>
47 #include <netinet/in_systm.h>
48 #include <netinet/in_var.h>
49 #include <netinet/if_ether.h>
50 #include <netinet/ip.h>
53 #include <net80211/ieee80211_var.h>
54 #include <net80211/ieee80211_regdomain.h>
55 #include <net80211/ieee80211_radiotap.h>
57 #include <dev/usb/usb.h>
58 #include <dev/usb/usbdi.h>
61 #include <dev/usb/wlan/if_urtwreg.h>
62 #include <dev/usb/wlan/if_urtwvar.h>
64 static SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW, 0, "USB Realtek 8187L");
67 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, &urtw_debug, 0,
68 "control debugging printfs");
69 TUNABLE_INT("hw.usb.urtw.debug", &urtw_debug);
71 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
72 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */
73 URTW_DEBUG_RESET = 0x00000004, /* reset processing */
74 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */
75 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */
76 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */
77 URTW_DEBUG_STAT = 0x00000040, /* statistic */
78 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */
79 URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */
80 URTW_DEBUG_ANY = 0xffffffff
82 #define DPRINTF(sc, m, fmt, ...) do { \
83 if (sc->sc_debug & (m)) \
84 printf(fmt, __VA_ARGS__); \
87 #define DPRINTF(sc, m, fmt, ...) do { \
91 static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG;
92 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RW | CTLFLAG_TUN,
93 &urtw_preamble_mode, 0, "set the preable mode (long or short)");
94 TUNABLE_INT("hw.usb.urtw.preamble_mode", &urtw_preamble_mode);
96 /* recognized device vendors/products */
97 #define urtw_lookup(v, p) \
98 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p))
99 #define URTW_DEV_B(v,p) \
100 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) }
101 #define URTW_DEV_L(v,p) \
102 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) }
103 #define URTW_REV_RTL8187B 0
104 #define URTW_REV_RTL8187L 1
105 static const STRUCT_USB_HOST_ID urtw_devs[] = {
106 URTW_DEV_B(NETGEAR, WG111V3),
107 URTW_DEV_B(REALTEK, RTL8187B_0),
108 URTW_DEV_B(REALTEK, RTL8187B_1),
109 URTW_DEV_B(REALTEK, RTL8187B_2),
110 URTW_DEV_B(SITECOMEU, WL168V4),
111 URTW_DEV_L(ASUS, P5B_WIFI),
112 URTW_DEV_L(BELKIN, F5D7050E),
113 URTW_DEV_L(LINKSYS4, WUSB54GCV2),
114 URTW_DEV_L(NETGEAR, WG111V2),
115 URTW_DEV_L(REALTEK, RTL8187),
116 URTW_DEV_L(SITECOMEU, WL168V1),
117 URTW_DEV_L(SURECOM, EP9001G2A),
118 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) },
119 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) },
120 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) },
121 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) },
122 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) },
123 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) },
124 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) },
129 #define urtw_read8_m(sc, val, data) do { \
130 error = urtw_read8_c(sc, val, data); \
134 #define urtw_write8_m(sc, val, data) do { \
135 error = urtw_write8_c(sc, val, data); \
139 #define urtw_read16_m(sc, val, data) do { \
140 error = urtw_read16_c(sc, val, data); \
144 #define urtw_write16_m(sc, val, data) do { \
145 error = urtw_write16_c(sc, val, data); \
149 #define urtw_read32_m(sc, val, data) do { \
150 error = urtw_read32_c(sc, val, data); \
154 #define urtw_write32_m(sc, val, data) do { \
155 error = urtw_write32_c(sc, val, data); \
159 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \
160 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \
164 #define urtw_8187_write_phy_cck(sc, val, data) do { \
165 error = urtw_8187_write_phy_cck_c(sc, val, data); \
169 #define urtw_8225_write(sc, val, data) do { \
170 error = urtw_8225_write_c(sc, val, data); \
180 static uint8_t urtw_8225_agc[] = {
181 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b,
182 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90,
183 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85,
184 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a,
185 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f,
186 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24,
187 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19,
188 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
189 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03,
190 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
191 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
192 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
195 static uint8_t urtw_8225z2_agc[] = {
196 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51,
197 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b,
198 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25,
199 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f,
200 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
201 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19,
202 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23,
203 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a,
204 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d,
205 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31,
206 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31,
207 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31
210 static uint32_t urtw_8225_channel[] = {
211 0x0000, /* dummy channel 0 */
228 static uint8_t urtw_8225_gain[] = {
229 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */
230 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */
231 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */
232 0x33, 0x80, 0x79, 0xc5, /* -78dbm */
233 0x43, 0x78, 0x76, 0xc5, /* -74dbm */
234 0x53, 0x60, 0x73, 0xc5, /* -70dbm */
235 0x63, 0x58, 0x70, 0xc5, /* -66dbm */
238 static struct urtw_pair urtw_8225_rf_part1[] = {
239 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
240 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a },
241 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 },
242 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 },
245 static struct urtw_pair urtw_8225_rf_part2[] = {
246 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
247 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
248 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 },
249 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 },
250 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 },
251 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef },
252 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 },
253 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 },
254 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 },
258 static struct urtw_pair urtw_8225_rf_part3[] = {
259 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
260 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b },
261 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 },
262 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d },
263 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e },
264 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a },
265 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 }
268 static uint16_t urtw_8225_rxgain[] = {
269 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
270 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
271 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
272 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
273 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
274 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
275 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
276 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
277 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
278 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
279 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
280 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
283 static uint8_t urtw_8225_threshold[] = {
284 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
287 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = {
288 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
291 static uint8_t urtw_8225_txpwr_cck[] = {
292 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
293 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
294 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
295 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
296 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
297 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
300 static uint8_t urtw_8225_txpwr_cck_ch14[] = {
301 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
302 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
303 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
304 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
305 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
306 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
309 static uint8_t urtw_8225_txpwr_ofdm[]={
310 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
313 static uint8_t urtw_8225v2_gain_bg[]={
314 0x23, 0x15, 0xa5, /* -82-1dbm */
315 0x23, 0x15, 0xb5, /* -82-2dbm */
316 0x23, 0x15, 0xc5, /* -82-3dbm */
317 0x33, 0x15, 0xc5, /* -78dbm */
318 0x43, 0x15, 0xc5, /* -74dbm */
319 0x53, 0x15, 0xc5, /* -70dbm */
320 0x63, 0x15, 0xc5, /* -66dbm */
323 static struct urtw_pair urtw_8225v2_rf_part1[] = {
324 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
325 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
326 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
327 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
330 static struct urtw_pair urtw_8225v2b_rf_part0[] = {
331 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
332 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
333 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
334 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
337 static struct urtw_pair urtw_8225v2b_rf_part1[] = {
338 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00},
339 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43},
340 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46},
341 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00},
342 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00},
343 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00},
344 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b},
345 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09},
346 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff},
347 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e},
348 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03},
349 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06},
350 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00},
351 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68},
352 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d},
353 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08},
354 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04},
355 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23},
356 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08},
357 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08},
358 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08},
359 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56},
360 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f},
361 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24},
362 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07},
363 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12},
364 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a},
365 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80},
366 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03},
367 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01},
368 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00}
371 static struct urtw_pair urtw_8225v2_rf_part2[] = {
372 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
373 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
374 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 },
375 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 },
376 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 },
377 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 },
378 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 },
379 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 },
380 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 },
381 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 }
384 static struct urtw_pair urtw_8225v2b_rf_part2[] = {
385 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 },
386 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 },
387 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 },
388 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 },
389 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 },
390 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 },
391 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 },
392 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 },
393 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a },
394 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f },
395 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 },
396 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 },
397 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 },
398 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e },
399 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 }
402 static struct urtw_pair urtw_8225v2_rf_part3[] = {
403 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
404 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 },
405 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 },
406 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 },
407 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d },
408 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 },
409 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 },
410 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 }
413 static uint16_t urtw_8225v2_rxgain[] = {
414 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009,
415 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141,
416 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183,
417 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244,
418 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288,
419 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345,
420 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389,
421 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393,
422 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d,
423 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9,
424 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
425 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
428 static uint16_t urtw_8225v2b_rxgain[] = {
429 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
430 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
431 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
432 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
433 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
434 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
435 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
436 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
437 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
438 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
439 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
440 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
443 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = {
444 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
445 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
446 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
447 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
448 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
449 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
452 static uint8_t urtw_8225v2_txpwr_cck[] = {
453 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
456 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = {
457 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
460 static uint8_t urtw_8225v2b_txpwr_cck[] = {
461 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04,
462 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03,
463 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03,
464 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03
467 static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = {
468 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00,
469 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
470 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
471 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00
474 static struct urtw_pair urtw_ratetable[] = {
475 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 },
476 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 },
477 { 96, 10 }, { 108, 11 }
480 static const uint8_t urtw_8187b_reg_table[][3] = {
481 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 },
482 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 },
483 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 },
484 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 },
485 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 },
486 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 },
487 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 },
488 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 },
489 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 },
490 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 },
491 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 },
492 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 },
493 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 },
494 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 },
495 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 },
496 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 },
497 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 },
498 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 },
499 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 },
500 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 },
501 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 },
502 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 },
503 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 },
504 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 },
505 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 },
506 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 },
507 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 },
508 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 },
509 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 },
510 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 },
511 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 }
514 static usb_callback_t urtw_bulk_rx_callback;
515 static usb_callback_t urtw_bulk_tx_callback;
516 static usb_callback_t urtw_bulk_tx_status_callback;
518 static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = {
519 [URTW_8187B_BULK_RX] = {
522 .direction = UE_DIR_IN,
529 .callback = urtw_bulk_rx_callback
531 [URTW_8187B_BULK_TX_STATUS] = {
534 .direction = UE_DIR_IN,
535 .bufsize = sizeof(uint64_t),
540 .callback = urtw_bulk_tx_status_callback
542 [URTW_8187B_BULK_TX_BE] = {
544 .endpoint = URTW_8187B_TXPIPE_BE,
545 .direction = UE_DIR_OUT,
546 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT,
548 .force_short_xfer = 1,
551 .callback = urtw_bulk_tx_callback,
552 .timeout = URTW_DATA_TIMEOUT
554 [URTW_8187B_BULK_TX_BK] = {
556 .endpoint = URTW_8187B_TXPIPE_BK,
557 .direction = UE_DIR_OUT,
558 .bufsize = URTW_TX_MAXSIZE,
561 .force_short_xfer = 1,
564 .callback = urtw_bulk_tx_callback,
565 .timeout = URTW_DATA_TIMEOUT
567 [URTW_8187B_BULK_TX_VI] = {
569 .endpoint = URTW_8187B_TXPIPE_VI,
570 .direction = UE_DIR_OUT,
571 .bufsize = URTW_TX_MAXSIZE,
574 .force_short_xfer = 1,
577 .callback = urtw_bulk_tx_callback,
578 .timeout = URTW_DATA_TIMEOUT
580 [URTW_8187B_BULK_TX_VO] = {
582 .endpoint = URTW_8187B_TXPIPE_VO,
583 .direction = UE_DIR_OUT,
584 .bufsize = URTW_TX_MAXSIZE,
587 .force_short_xfer = 1,
590 .callback = urtw_bulk_tx_callback,
591 .timeout = URTW_DATA_TIMEOUT
593 [URTW_8187B_BULK_TX_EP12] = {
596 .direction = UE_DIR_OUT,
597 .bufsize = URTW_TX_MAXSIZE,
600 .force_short_xfer = 1,
603 .callback = urtw_bulk_tx_callback,
604 .timeout = URTW_DATA_TIMEOUT
608 static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = {
609 [URTW_8187L_BULK_RX] = {
612 .direction = UE_DIR_IN,
619 .callback = urtw_bulk_rx_callback
621 [URTW_8187L_BULK_TX_LOW] = {
624 .direction = UE_DIR_OUT,
625 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT,
627 .force_short_xfer = 1,
630 .callback = urtw_bulk_tx_callback,
631 .timeout = URTW_DATA_TIMEOUT
633 [URTW_8187L_BULK_TX_NORMAL] = {
636 .direction = UE_DIR_OUT,
637 .bufsize = URTW_TX_MAXSIZE,
640 .force_short_xfer = 1,
643 .callback = urtw_bulk_tx_callback,
644 .timeout = URTW_DATA_TIMEOUT
648 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *,
649 const char [IFNAMSIZ], int, enum ieee80211_opmode,
650 int, const uint8_t [IEEE80211_ADDR_LEN],
651 const uint8_t [IEEE80211_ADDR_LEN]);
652 static void urtw_vap_delete(struct ieee80211vap *);
653 static void urtw_init(void *);
654 static void urtw_stop(struct ifnet *);
655 static void urtw_stop_locked(struct ifnet *);
656 static int urtw_ioctl(struct ifnet *, u_long, caddr_t);
657 static void urtw_start(struct ifnet *);
658 static int urtw_alloc_rx_data_list(struct urtw_softc *);
659 static int urtw_alloc_tx_data_list(struct urtw_softc *);
660 static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *,
661 const struct ieee80211_bpf_params *);
662 static void urtw_scan_start(struct ieee80211com *);
663 static void urtw_scan_end(struct ieee80211com *);
664 static void urtw_set_channel(struct ieee80211com *);
665 static void urtw_update_mcast(struct ifnet *);
666 static int urtw_tx_start(struct urtw_softc *,
667 struct ieee80211_node *, struct mbuf *,
668 struct urtw_data *, int);
669 static int urtw_newstate(struct ieee80211vap *,
670 enum ieee80211_state, int);
671 static void urtw_led_ch(void *);
672 static void urtw_ledtask(void *, int);
673 static void urtw_watchdog(void *);
674 static void urtw_set_multi(void *);
675 static int urtw_isbmode(uint16_t);
676 static uint16_t urtw_rate2rtl(uint32_t);
677 static uint16_t urtw_rtl2rate(uint32_t);
678 static usb_error_t urtw_set_rate(struct urtw_softc *);
679 static usb_error_t urtw_update_msr(struct urtw_softc *);
680 static usb_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *);
681 static usb_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *);
682 static usb_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *);
683 static usb_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t);
684 static usb_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t);
685 static usb_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t);
686 static usb_error_t urtw_eprom_cs(struct urtw_softc *, int);
687 static usb_error_t urtw_eprom_ck(struct urtw_softc *);
688 static usb_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *,
690 static usb_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t,
692 static usb_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *);
693 static usb_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t);
694 static usb_error_t urtw_get_macaddr(struct urtw_softc *);
695 static usb_error_t urtw_get_txpwr(struct urtw_softc *);
696 static usb_error_t urtw_get_rfchip(struct urtw_softc *);
697 static usb_error_t urtw_led_init(struct urtw_softc *);
698 static usb_error_t urtw_8185_rf_pins_enable(struct urtw_softc *);
699 static usb_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t);
700 static usb_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t,
702 static usb_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *,
704 static usb_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t,
706 static usb_error_t urtw_8225_setgain(struct urtw_softc *, int16_t);
707 static usb_error_t urtw_8225_usb_init(struct urtw_softc *);
708 static usb_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t,
710 static usb_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int,
712 static usb_error_t urtw_8225_read(struct urtw_softc *, uint8_t,
714 static usb_error_t urtw_8225_rf_init(struct urtw_softc *);
715 static usb_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int);
716 static usb_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int);
717 static usb_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int);
718 static usb_error_t urtw_8225_rf_stop(struct urtw_softc *);
719 static usb_error_t urtw_8225v2_rf_init(struct urtw_softc *);
720 static usb_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int);
721 static usb_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int);
722 static usb_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t);
723 static usb_error_t urtw_8225_isv2(struct urtw_softc *, int *);
724 static usb_error_t urtw_8225v2b_rf_init(struct urtw_softc *);
725 static usb_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int);
726 static usb_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *);
727 static usb_error_t urtw_write8e(struct urtw_softc *, int, uint8_t);
728 static usb_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t);
729 static usb_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t);
730 static usb_error_t urtw_intr_enable(struct urtw_softc *);
731 static usb_error_t urtw_intr_disable(struct urtw_softc *);
732 static usb_error_t urtw_reset(struct urtw_softc *);
733 static usb_error_t urtw_led_on(struct urtw_softc *, int);
734 static usb_error_t urtw_led_ctl(struct urtw_softc *, int);
735 static usb_error_t urtw_led_blink(struct urtw_softc *);
736 static usb_error_t urtw_led_mode0(struct urtw_softc *, int);
737 static usb_error_t urtw_led_mode1(struct urtw_softc *, int);
738 static usb_error_t urtw_led_mode2(struct urtw_softc *, int);
739 static usb_error_t urtw_led_mode3(struct urtw_softc *, int);
740 static usb_error_t urtw_rx_setconf(struct urtw_softc *);
741 static usb_error_t urtw_rx_enable(struct urtw_softc *);
742 static usb_error_t urtw_tx_enable(struct urtw_softc *sc);
743 static void urtw_free_tx_data_list(struct urtw_softc *);
744 static void urtw_free_rx_data_list(struct urtw_softc *);
745 static void urtw_free_data_list(struct urtw_softc *,
746 struct urtw_data data[], int, int);
747 static usb_error_t urtw_adapter_start(struct urtw_softc *);
748 static usb_error_t urtw_adapter_start_b(struct urtw_softc *);
749 static usb_error_t urtw_set_mode(struct urtw_softc *, uint32_t);
750 static usb_error_t urtw_8187b_cmd_reset(struct urtw_softc *);
751 static usb_error_t urtw_do_request(struct urtw_softc *,
752 struct usb_device_request *, void *);
753 static usb_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int);
754 static usb_error_t urtw_led_off(struct urtw_softc *, int);
755 static void urtw_abort_xfers(struct urtw_softc *);
756 static struct urtw_data *
757 urtw_getbuf(struct urtw_softc *sc);
758 static int urtw_compute_txtime(uint16_t, uint16_t, uint8_t,
760 static void urtw_updateslot(struct ifnet *);
761 static void urtw_updateslottask(void *, int);
762 static void urtw_sysctl_node(struct urtw_softc *);
765 urtw_match(device_t dev)
767 struct usb_attach_arg *uaa = device_get_ivars(dev);
769 if (uaa->usb_mode != USB_MODE_HOST)
771 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX)
773 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX)
776 return (usbd_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa));
780 urtw_attach(device_t dev)
782 const struct usb_config *setup_start;
784 struct urtw_softc *sc = device_get_softc(dev);
785 struct usb_attach_arg *uaa = device_get_ivars(dev);
786 struct ieee80211com *ic;
788 uint8_t bands, iface_index = URTW_IFACE_INDEX; /* XXX */
793 device_set_usb_desc(dev);
796 sc->sc_udev = uaa->device;
797 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B)
798 sc->sc_flags |= URTW_RTL8187B;
800 sc->sc_debug = urtw_debug;
803 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK,
805 usb_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0);
806 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc);
807 TASK_INIT(&sc->sc_updateslot_task, 0, urtw_updateslottask, sc);
808 callout_init(&sc->sc_watchdog_ch, 0);
810 if (sc->sc_flags & URTW_RTL8187B) {
811 setup_start = urtw_8187b_usbconfig;
812 n_setup = URTW_8187B_N_XFERS;
814 setup_start = urtw_8187l_usbconfig;
815 n_setup = URTW_8187L_N_XFERS;
818 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
819 setup_start, n_setup, sc, &sc->sc_mtx);
821 device_printf(dev, "could not allocate USB transfers, "
822 "err=%s\n", usbd_errstr(error));
827 if (sc->sc_flags & URTW_RTL8187B) {
829 usbd_xfer_get_frame_buffer(sc->sc_xfer[
830 URTW_8187B_BULK_TX_BE], 0);
833 usbd_xfer_get_frame_buffer(sc->sc_xfer[
834 URTW_8187L_BULK_TX_LOW], 0);
839 urtw_read32_m(sc, URTW_RX, &data);
840 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 :
843 error = urtw_get_rfchip(sc);
846 error = urtw_get_macaddr(sc);
849 error = urtw_get_txpwr(sc);
852 error = urtw_led_init(sc);
858 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY;
859 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY;
861 sc->sc_preamble_mode = urtw_preamble_mode;
863 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
865 device_printf(sc->sc_dev, "can not allocate ifnet\n");
871 if_initname(ifp, "urtw", device_get_unit(sc->sc_dev));
872 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
873 ifp->if_init = urtw_init;
874 ifp->if_ioctl = urtw_ioctl;
875 ifp->if_start = urtw_start;
876 /* XXX URTW_TX_DATA_LIST_COUNT */
877 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
878 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
879 IFQ_SET_READY(&ifp->if_snd);
883 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
884 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
886 /* set device capabilities */
888 IEEE80211_C_STA | /* station mode */
889 IEEE80211_C_MONITOR | /* monitor mode supported */
890 IEEE80211_C_TXPMGT | /* tx power management */
891 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
892 IEEE80211_C_SHSLOT | /* short slot time supported */
893 IEEE80211_C_BGSCAN | /* capable of bg scanning */
894 IEEE80211_C_WPA; /* 802.11i */
897 setbit(&bands, IEEE80211_MODE_11B);
898 setbit(&bands, IEEE80211_MODE_11G);
899 ieee80211_init_channels(ic, NULL, &bands);
901 ieee80211_ifattach(ic, sc->sc_bssid);
902 ic->ic_raw_xmit = urtw_raw_xmit;
903 ic->ic_scan_start = urtw_scan_start;
904 ic->ic_scan_end = urtw_scan_end;
905 ic->ic_set_channel = urtw_set_channel;
906 ic->ic_updateslot = urtw_updateslot;
907 ic->ic_vap_create = urtw_vap_create;
908 ic->ic_vap_delete = urtw_vap_delete;
909 ic->ic_update_mcast = urtw_update_mcast;
911 ieee80211_radiotap_attach(ic,
912 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
913 URTW_TX_RADIOTAP_PRESENT,
914 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
915 URTW_RX_RADIOTAP_PRESENT);
917 urtw_sysctl_node(sc);
920 ieee80211_announce(ic);
923 fail: URTW_UNLOCK(sc);
924 fail1: usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ?
925 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS);
931 urtw_detach(device_t dev)
933 struct urtw_softc *sc = device_get_softc(dev);
934 struct ifnet *ifp = sc->sc_ifp;
935 struct ieee80211com *ic = ifp->if_l2com;
937 unsigned int n_xfers;
939 /* Prevent further ioctls */
941 sc->sc_flags |= URTW_DETACHED;
946 ieee80211_draintask(ic, &sc->sc_updateslot_task);
947 ieee80211_draintask(ic, &sc->sc_led_task);
949 usb_callout_drain(&sc->sc_led_ch);
950 callout_drain(&sc->sc_watchdog_ch);
952 n_xfers = (sc->sc_flags & URTW_RTL8187B) ?
953 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS;
955 /* prevent further allocations from RX/TX data lists */
957 STAILQ_INIT(&sc->sc_tx_active);
958 STAILQ_INIT(&sc->sc_tx_inactive);
959 STAILQ_INIT(&sc->sc_tx_pending);
961 STAILQ_INIT(&sc->sc_rx_active);
962 STAILQ_INIT(&sc->sc_rx_inactive);
965 /* drain USB transfers */
966 for (x = 0; x != n_xfers; x++)
967 usbd_transfer_drain(sc->sc_xfer[x]);
969 /* free data buffers */
971 urtw_free_tx_data_list(sc);
972 urtw_free_rx_data_list(sc);
975 /* free USB transfers and some data buffers */
976 usbd_transfer_unsetup(sc->sc_xfer, n_xfers);
978 ieee80211_ifdetach(ic);
980 mtx_destroy(&sc->sc_mtx);
985 urtw_free_tx_data_list(struct urtw_softc *sc)
987 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0);
991 urtw_free_rx_data_list(struct urtw_softc *sc)
993 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1);
997 urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata,
1002 for (i = 0; i < ndata; i++) {
1003 struct urtw_data *dp = &data[i];
1005 if (fillmbuf == 1) {
1006 if (dp->m != NULL) {
1014 if (dp->ni != NULL) {
1015 ieee80211_free_node(dp->ni);
1021 static struct ieee80211vap *
1022 urtw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1023 enum ieee80211_opmode opmode, int flags,
1024 const uint8_t bssid[IEEE80211_ADDR_LEN],
1025 const uint8_t mac[IEEE80211_ADDR_LEN])
1027 struct urtw_vap *uvp;
1028 struct ieee80211vap *vap;
1030 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
1032 uvp = (struct urtw_vap *) malloc(sizeof(struct urtw_vap),
1033 M_80211_VAP, M_NOWAIT | M_ZERO);
1037 /* enable s/w bmiss handling for sta mode */
1038 ieee80211_vap_setup(ic, vap, name, unit, opmode,
1039 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac);
1041 /* override state transition machine */
1042 uvp->newstate = vap->iv_newstate;
1043 vap->iv_newstate = urtw_newstate;
1045 /* complete setup */
1046 ieee80211_vap_attach(vap, ieee80211_media_change,
1047 ieee80211_media_status);
1048 ic->ic_opmode = opmode;
1053 urtw_vap_delete(struct ieee80211vap *vap)
1055 struct urtw_vap *uvp = URTW_VAP(vap);
1057 ieee80211_vap_detach(vap);
1058 free(uvp, M_80211_VAP);
1062 urtw_init_locked(void *arg)
1065 struct urtw_softc *sc = arg;
1066 struct ifnet *ifp = sc->sc_ifp;
1069 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1070 urtw_stop_locked(ifp);
1072 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) :
1073 urtw_adapter_start(sc);
1077 /* reset softc variables */
1080 if (!(sc->sc_flags & URTW_INIT_ONCE)) {
1081 ret = urtw_alloc_rx_data_list(sc);
1084 ret = urtw_alloc_tx_data_list(sc);
1087 sc->sc_flags |= URTW_INIT_ONCE;
1090 error = urtw_rx_enable(sc);
1093 error = urtw_tx_enable(sc);
1097 if (sc->sc_flags & URTW_RTL8187B)
1098 usbd_transfer_start(sc->sc_xfer[URTW_8187B_BULK_TX_STATUS]);
1100 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1101 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1103 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1109 urtw_init(void *arg)
1111 struct urtw_softc *sc = arg;
1114 urtw_init_locked(arg);
1119 urtw_adapter_start_b(struct urtw_softc *sc)
1121 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
1125 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1129 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1130 urtw_write8_m(sc, URTW_CONFIG3,
1131 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT);
1132 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON);
1133 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON);
1134 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON);
1136 urtw_write8_m(sc, 0x61, 0x10);
1137 urtw_read8_m(sc, 0x62, &data8);
1138 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5));
1139 urtw_write8_m(sc, 0x62, data8 | (1 << 5));
1141 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1142 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE;
1143 urtw_write8_m(sc, URTW_CONFIG3, data8);
1145 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1149 error = urtw_8187b_cmd_reset(sc);
1153 error = sc->sc_rf_init(sc);
1156 urtw_write8_m(sc, URTW_CMD, URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE);
1158 /* fix RTL8187B RX stall */
1159 error = urtw_intr_enable(sc);
1163 error = urtw_write8e(sc, 0x41, 0xf4);
1166 error = urtw_write8e(sc, 0x40, 0x00);
1169 error = urtw_write8e(sc, 0x42, 0x00);
1172 error = urtw_write8e(sc, 0x42, 0x01);
1175 error = urtw_write8e(sc, 0x40, 0x0f);
1178 error = urtw_write8e(sc, 0x42, 0x00);
1181 error = urtw_write8e(sc, 0x42, 0x01);
1185 urtw_read8_m(sc, 0xdb, &data8);
1186 urtw_write8_m(sc, 0xdb, data8 | (1 << 2));
1187 urtw_write16_m(sc, 0x372, 0x59fa);
1188 urtw_write16_m(sc, 0x374, 0x59d2);
1189 urtw_write16_m(sc, 0x376, 0x59d2);
1190 urtw_write16_m(sc, 0x378, 0x19fa);
1191 urtw_write16_m(sc, 0x37a, 0x19fa);
1192 urtw_write16_m(sc, 0x37c, 0x00d0);
1193 urtw_write8_m(sc, 0x61, 0);
1195 urtw_write8_m(sc, 0x180, 0x0f);
1196 urtw_write8_m(sc, 0x183, 0x03);
1197 urtw_write8_m(sc, 0xda, 0x10);
1198 urtw_write8_m(sc, 0x24d, 0x08);
1199 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b);
1201 urtw_write16_m(sc, 0x1ec, 0x800); /* RX MAX SIZE */
1208 urtw_adapter_start(struct urtw_softc *sc)
1212 error = urtw_reset(sc);
1216 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0);
1217 urtw_write8_m(sc, URTW_GPIO, 0);
1220 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1221 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON);
1225 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1228 /* applying MAC address again. */
1229 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)sc->sc_bssid)[0]);
1230 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)sc->sc_bssid)[1] & 0xffff);
1231 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1235 error = urtw_update_msr(sc);
1239 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0);
1240 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
1241 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1);
1242 error = urtw_set_rate(sc);
1246 error = sc->sc_rf_init(sc);
1249 if (sc->sc_rf_set_sens != NULL)
1250 sc->sc_rf_set_sens(sc, sc->sc_sens);
1252 /* XXX correct? to call write16 */
1253 urtw_write16_m(sc, URTW_PSR, 1);
1254 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10);
1255 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80);
1256 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60);
1257 /* XXX correct? to call write16 */
1258 urtw_write16_m(sc, URTW_PSR, 0);
1259 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1261 error = urtw_intr_enable(sc);
1270 urtw_set_mode(struct urtw_softc *sc, uint32_t mode)
1275 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1276 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT);
1277 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK);
1278 urtw_write8_m(sc, URTW_EPROM_CMD, data);
1284 urtw_8187b_cmd_reset(struct urtw_softc *sc)
1290 /* XXX the code can be duplicate with urtw_reset(). */
1291 urtw_read8_m(sc, URTW_CMD, &data8);
1292 data8 = (data8 & 0x2) | URTW_CMD_RST;
1293 urtw_write8_m(sc, URTW_CMD, data8);
1295 for (i = 0; i < 20; i++) {
1296 usb_pause_mtx(&sc->sc_mtx, 2);
1297 urtw_read8_m(sc, URTW_CMD, &data8);
1298 if (!(data8 & URTW_CMD_RST))
1302 device_printf(sc->sc_dev, "reset timeout\n");
1310 urtw_do_request(struct urtw_softc *sc,
1311 struct usb_device_request *req, void *data)
1316 URTW_ASSERT_LOCKED(sc);
1319 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx,
1320 req, data, 0, NULL, 250 /* ms */);
1324 DPRINTF(sc, URTW_DEBUG_INIT,
1325 "Control request failed, %s (retrying)\n",
1327 usb_pause_mtx(&sc->sc_mtx, hz / 100);
1333 urtw_stop_locked(struct ifnet *ifp)
1335 struct urtw_softc *sc = ifp->if_softc;
1339 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1341 error = urtw_intr_disable(sc);
1344 urtw_read8_m(sc, URTW_CMD, &data8);
1345 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE);
1346 urtw_write8_m(sc, URTW_CMD, data8);
1348 error = sc->sc_rf_stop(sc);
1352 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1355 urtw_read8_m(sc, URTW_CONFIG4, &data8);
1356 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF);
1357 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1362 device_printf(sc->sc_dev, "failed to stop (%s)\n",
1363 usbd_errstr(error));
1365 usb_callout_stop(&sc->sc_led_ch);
1366 callout_stop(&sc->sc_watchdog_ch);
1368 urtw_abort_xfers(sc);
1372 urtw_stop(struct ifnet *ifp)
1374 struct urtw_softc *sc = ifp->if_softc;
1377 urtw_stop_locked(ifp);
1382 urtw_abort_xfers(struct urtw_softc *sc)
1386 URTW_ASSERT_LOCKED(sc);
1388 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS :
1391 /* abort any pending transfers */
1392 for (i = 0; i < max; i++)
1393 usbd_transfer_stop(sc->sc_xfer[i]);
1397 urtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1399 struct urtw_softc *sc = ifp->if_softc;
1400 struct ieee80211com *ic = ifp->if_l2com;
1401 struct ifreq *ifr = (struct ifreq *) data;
1406 error = (sc->sc_flags & URTW_DETACHED) ? ENXIO : 0;
1413 if (ifp->if_flags & IFF_UP) {
1414 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1415 if ((ifp->if_flags ^ sc->sc_if_flags) &
1416 (IFF_ALLMULTI | IFF_PROMISC))
1419 urtw_init(ifp->if_softc);
1423 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1426 sc->sc_if_flags = ifp->if_flags;
1428 ieee80211_start_all(ic);
1431 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
1434 error = ether_ioctl(ifp, cmd, data);
1444 urtw_start(struct ifnet *ifp)
1446 struct urtw_data *bf;
1447 struct urtw_softc *sc = ifp->if_softc;
1448 struct ieee80211_node *ni;
1451 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1456 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1459 bf = urtw_getbuf(sc);
1461 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1465 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1466 m->m_pkthdr.rcvif = NULL;
1468 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) {
1470 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1471 ieee80211_free_node(ni);
1476 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1482 urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[],
1483 int ndata, int maxsz, void *dma_buf)
1487 for (i = 0; i < ndata; i++) {
1488 struct urtw_data *dp = &data[i];
1491 if (dma_buf == NULL) {
1492 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1493 if (dp->m == NULL) {
1494 device_printf(sc->sc_dev,
1495 "could not allocate rx mbuf\n");
1499 dp->buf = mtod(dp->m, uint8_t *);
1502 dp->buf = ((uint8_t *)dma_buf) +
1509 fail: urtw_free_data_list(sc, data, ndata, 1);
1514 urtw_alloc_rx_data_list(struct urtw_softc *sc)
1518 error = urtw_alloc_data_list(sc,
1519 sc->sc_rx, URTW_RX_DATA_LIST_COUNT,
1520 MCLBYTES, NULL /* mbufs */);
1524 STAILQ_INIT(&sc->sc_rx_active);
1525 STAILQ_INIT(&sc->sc_rx_inactive);
1527 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++)
1528 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next);
1534 urtw_alloc_tx_data_list(struct urtw_softc *sc)
1538 error = urtw_alloc_data_list(sc,
1539 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE,
1540 sc->sc_tx_dma_buf /* no mbufs */);
1544 STAILQ_INIT(&sc->sc_tx_active);
1545 STAILQ_INIT(&sc->sc_tx_inactive);
1546 STAILQ_INIT(&sc->sc_tx_pending);
1548 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++)
1549 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i],
1556 urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1557 const struct ieee80211_bpf_params *params)
1559 struct ieee80211com *ic = ni->ni_ic;
1560 struct ifnet *ifp = ic->ic_ifp;
1561 struct urtw_data *bf;
1562 struct urtw_softc *sc = ifp->if_softc;
1564 /* prevent management frames from being sent if we're not ready */
1565 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1567 ieee80211_free_node(ni);
1571 bf = urtw_getbuf(sc);
1573 ieee80211_free_node(ni);
1576 return (ENOBUFS); /* XXX */
1580 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) {
1581 ieee80211_free_node(ni);
1583 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1594 urtw_scan_start(struct ieee80211com *ic)
1597 /* XXX do nothing? */
1601 urtw_scan_end(struct ieee80211com *ic)
1604 /* XXX do nothing? */
1608 urtw_set_channel(struct ieee80211com *ic)
1610 struct urtw_softc *sc = ic->ic_ifp->if_softc;
1611 struct ifnet *ifp = sc->sc_ifp;
1612 uint32_t data, orig;
1616 * if the user set a channel explicitly using ifconfig(8) this function
1617 * can be called earlier than we're expected that in some cases the
1618 * initialization would be failed if setting a channel is called before
1619 * the init have done.
1621 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1624 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan)
1630 * during changing th channel we need to temporarily be disable
1633 urtw_read32_m(sc, URTW_TX_CONF, &orig);
1634 data = orig & ~URTW_TX_LOOPBACK_MASK;
1635 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC);
1637 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan));
1640 usb_pause_mtx(&sc->sc_mtx, 10);
1641 urtw_write32_m(sc, URTW_TX_CONF, orig);
1643 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1644 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1645 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
1646 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1651 sc->sc_curchan = ic->ic_curchan;
1654 device_printf(sc->sc_dev, "could not change the channel\n");
1658 urtw_update_mcast(struct ifnet *ifp)
1661 /* XXX do nothing? */
1665 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0,
1666 struct urtw_data *data, int prior)
1668 struct ifnet *ifp = sc->sc_ifp;
1669 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *);
1670 struct ieee80211_key *k;
1671 const struct ieee80211_txparam *tp;
1672 struct ieee80211com *ic = ifp->if_l2com;
1673 struct ieee80211vap *vap = ni->ni_vap;
1674 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = {
1675 sc->sc_xfer[URTW_8187B_BULK_TX_BE],
1676 sc->sc_xfer[URTW_8187B_BULK_TX_BK],
1677 sc->sc_xfer[URTW_8187B_BULK_TX_VI],
1678 sc->sc_xfer[URTW_8187B_BULK_TX_VO]
1680 struct usb_xfer *xfer;
1681 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate,
1682 pkttime = 0, txdur = 0, isshort = 0, xferlen;
1683 uint16_t acktime, rtstime, ctstime;
1687 URTW_ASSERT_LOCKED(sc);
1692 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1693 k = ieee80211_crypto_encap(ni, m0);
1695 device_printf(sc->sc_dev,
1696 "ieee80211_crypto_encap returns NULL.\n");
1697 /* XXX we don't expect the fragmented frames */
1702 /* in case packet header moved, reset pointer */
1703 wh = mtod(m0, struct ieee80211_frame *);
1706 if (ieee80211_radiotap_active_vap(vap)) {
1707 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap;
1709 /* XXX Are variables correct? */
1711 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1712 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1714 ieee80211_radiotap_tx(vap, m0);
1717 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_MGT ||
1718 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_CTL) {
1719 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)];
1720 rate = tp->mgmtrate;
1722 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
1723 /* for data frames */
1724 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1725 rate = tp->mcastrate;
1726 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
1727 rate = tp->ucastrate;
1729 rate = urtw_rtl2rate(sc->sc_currate);
1732 sc->sc_stats.txrates[sc->sc_currate]++;
1734 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1735 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1736 IEEE80211_CRC_LEN, rate, 0, 0);
1738 acktime = urtw_compute_txtime(14, 2,0, 0);
1739 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) {
1742 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0);
1743 ctstime = urtw_compute_txtime(14, 2, 0, 0);
1744 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1745 IEEE80211_CRC_LEN, rate, 0, isshort);
1746 rtsdur = ctstime + pkttime + acktime +
1747 3 * URTW_ASIFS_TIME;
1748 txdur = rtstime + rtsdur;
1750 rtsenable = ctsenable = rtsdur = 0;
1751 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1752 IEEE80211_CRC_LEN, rate, 0, isshort);
1753 txdur = pkttime + URTW_ASIFS_TIME + acktime;
1756 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1757 dur = urtw_compute_txtime(m0->m_pkthdr.len +
1758 IEEE80211_CRC_LEN, rate, 0, isshort) +
1759 3 * URTW_ASIFS_TIME +
1762 dur = URTW_ASIFS_TIME + acktime;
1764 *(uint16_t *)wh->i_dur = htole16(dur);
1766 xferlen = m0->m_pkthdr.len;
1767 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3);
1768 if ((0 == xferlen % 64) || (0 == xferlen % 512))
1771 memset(data->buf, 0, URTW_TX_MAXSIZE);
1772 flags = m0->m_pkthdr.len & 0xfff;
1773 flags |= URTW_TX_FLAG_NO_ENC;
1774 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
1775 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) &&
1776 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) &&
1777 (sc->sc_currate != 0))
1778 flags |= URTW_TX_FLAG_SPLCP;
1779 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1780 flags |= URTW_TX_FLAG_MOREFRAG;
1782 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT;
1784 if (sc->sc_flags & URTW_RTL8187B) {
1785 struct urtw_8187b_txhdr *tx;
1787 tx = (struct urtw_8187b_txhdr *)data->buf;
1789 flags |= URTW_TX_FLAG_CTS;
1791 flags |= URTW_TX_FLAG_RTS;
1792 flags |= (urtw_rate2rtl(11) & 0xf) <<
1793 URTW_TX_FLAG_RTSRATE_SHIFT;
1794 tx->rtsdur = rtsdur;
1796 tx->flag = htole32(flags);
1798 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
1799 IEEE80211_FC0_TYPE_MGT &&
1800 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1801 IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1804 tx->retry = URTW_TX_MAXRETRY;
1805 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1807 struct urtw_8187l_txhdr *tx;
1809 tx = (struct urtw_8187l_txhdr *)data->buf;
1811 flags |= URTW_TX_FLAG_RTS;
1812 tx->rtsdur = rtsdur;
1814 flags |= (urtw_rate2rtl(11) & 0xf) << URTW_TX_FLAG_RTSRATE_SHIFT;
1815 tx->flag = htole32(flags);
1816 tx->retry = 3; /* CW minimum */
1817 tx->retry = 7 << 4; /* CW maximum */
1818 tx->retry = URTW_TX_MAXRETRY << 8; /* retry limitation */
1819 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1822 data->buflen = xferlen;
1826 if (sc->sc_flags & URTW_RTL8187B) {
1827 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1828 case IEEE80211_FC0_TYPE_CTL:
1829 case IEEE80211_FC0_TYPE_MGT:
1830 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12];
1833 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX,
1834 ("unsupported WME pipe %d", M_WME_GETAC(m0)));
1835 xfer = rtl8187b_pipes[M_WME_GETAC(m0)];
1839 xfer = (prior == URTW_PRIORITY_LOW) ?
1840 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] :
1841 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL];
1843 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
1844 usbd_transfer_start(xfer);
1846 error = urtw_led_ctl(sc, URTW_LED_CTL_TX);
1848 device_printf(sc->sc_dev, "could not control LED (%d)\n",
1854 urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1856 struct ieee80211com *ic = vap->iv_ic;
1857 struct urtw_softc *sc = ic->ic_ifp->if_softc;
1858 struct urtw_vap *uvp = URTW_VAP(vap);
1859 struct ieee80211_node *ni;
1860 usb_error_t error = 0;
1862 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__,
1863 ieee80211_state_name[vap->iv_state],
1864 ieee80211_state_name[nstate]);
1866 sc->sc_state = nstate;
1868 IEEE80211_UNLOCK(ic);
1870 usb_callout_stop(&sc->sc_led_ch);
1871 callout_stop(&sc->sc_watchdog_ch);
1874 case IEEE80211_S_INIT:
1875 case IEEE80211_S_SCAN:
1876 case IEEE80211_S_AUTH:
1877 case IEEE80211_S_ASSOC:
1879 case IEEE80211_S_RUN:
1880 ni = ieee80211_ref_node(vap->iv_bss);
1881 /* setting bssid. */
1882 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]);
1883 urtw_write16_m(sc, URTW_BSSID + 4,
1884 ((uint16_t *)ni->ni_bssid)[2]);
1885 urtw_update_msr(sc);
1886 /* XXX maybe the below would be incorrect. */
1887 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1888 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1889 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64);
1890 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1891 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK);
1893 device_printf(sc->sc_dev,
1894 "could not control LED (%d)\n", error);
1895 ieee80211_free_node(ni);
1903 return (uvp->newstate(vap, nstate, arg));
1907 urtw_watchdog(void *arg)
1909 struct urtw_softc *sc = arg;
1910 struct ifnet *ifp = sc->sc_ifp;
1912 if (sc->sc_txtimer > 0) {
1913 if (--sc->sc_txtimer == 0) {
1914 device_printf(sc->sc_dev, "device timeout\n");
1918 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1923 urtw_set_multi(void *arg)
1925 struct urtw_softc *sc = arg;
1926 struct ifnet *ifp = sc->sc_ifp;
1928 if (!(ifp->if_flags & IFF_UP))
1932 * XXX don't know how to set a device. Lack of docs. Just try to set
1933 * IFF_ALLMULTI flag here.
1935 ifp->if_flags |= IFF_ALLMULTI;
1939 urtw_set_rate(struct urtw_softc *sc)
1941 int i, basic_rate, min_rr_rate, max_rr_rate;
1945 basic_rate = urtw_rate2rtl(48);
1946 min_rr_rate = urtw_rate2rtl(12);
1947 max_rr_rate = urtw_rate2rtl(48);
1949 urtw_write8_m(sc, URTW_RESP_RATE,
1950 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT |
1951 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT);
1953 urtw_read16_m(sc, URTW_BRSR, &data);
1954 data &= ~URTW_BRSR_MBR_8185;
1956 for (i = 0; i <= basic_rate; i++)
1959 urtw_write16_m(sc, URTW_BRSR, data);
1965 urtw_rate2rtl(uint32_t rate)
1967 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
1970 for (i = 0; i < N(urtw_ratetable); i++) {
1971 if (rate == urtw_ratetable[i].reg)
1972 return urtw_ratetable[i].val;
1980 urtw_rtl2rate(uint32_t rate)
1982 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
1985 for (i = 0; i < N(urtw_ratetable); i++) {
1986 if (rate == urtw_ratetable[i].val)
1987 return urtw_ratetable[i].reg;
1995 urtw_update_msr(struct urtw_softc *sc)
1997 struct ifnet *ifp = sc->sc_ifp;
1998 struct ieee80211com *ic = ifp->if_l2com;
2002 urtw_read8_m(sc, URTW_MSR, &data);
2003 data &= ~URTW_MSR_LINK_MASK;
2005 if (sc->sc_state == IEEE80211_S_RUN) {
2006 switch (ic->ic_opmode) {
2007 case IEEE80211_M_STA:
2008 case IEEE80211_M_MONITOR:
2009 data |= URTW_MSR_LINK_STA;
2010 if (sc->sc_flags & URTW_RTL8187B)
2011 data |= URTW_MSR_LINK_ENEDCA;
2013 case IEEE80211_M_IBSS:
2014 data |= URTW_MSR_LINK_ADHOC;
2016 case IEEE80211_M_HOSTAP:
2017 data |= URTW_MSR_LINK_HOSTAP;
2020 DPRINTF(sc, URTW_DEBUG_STATE,
2021 "unsupported operation mode 0x%x\n",
2023 error = USB_ERR_INVAL;
2027 data |= URTW_MSR_LINK_NONE;
2029 urtw_write8_m(sc, URTW_MSR, data);
2035 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data)
2037 struct usb_device_request req;
2040 URTW_ASSERT_LOCKED(sc);
2042 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2043 req.bRequest = URTW_8187_GETREGS_REQ;
2044 USETW(req.wValue, (val & 0xff) | 0xff00);
2045 USETW(req.wIndex, (val >> 8) & 0x3);
2046 USETW(req.wLength, sizeof(uint8_t));
2048 error = urtw_do_request(sc, &req, data);
2053 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data)
2055 struct usb_device_request req;
2058 URTW_ASSERT_LOCKED(sc);
2060 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2061 req.bRequest = URTW_8187_GETREGS_REQ;
2062 USETW(req.wValue, (val & 0xff) | 0xff00);
2063 USETW(req.wIndex, (val >> 8) & 0x3);
2064 USETW(req.wLength, sizeof(uint16_t));
2066 error = urtw_do_request(sc, &req, data);
2071 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data)
2073 struct usb_device_request req;
2076 URTW_ASSERT_LOCKED(sc);
2078 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2079 req.bRequest = URTW_8187_GETREGS_REQ;
2080 USETW(req.wValue, (val & 0xff) | 0xff00);
2081 USETW(req.wIndex, (val >> 8) & 0x3);
2082 USETW(req.wLength, sizeof(uint32_t));
2084 error = urtw_do_request(sc, &req, data);
2089 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data)
2091 struct usb_device_request req;
2093 URTW_ASSERT_LOCKED(sc);
2095 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2096 req.bRequest = URTW_8187_SETREGS_REQ;
2097 USETW(req.wValue, (val & 0xff) | 0xff00);
2098 USETW(req.wIndex, (val >> 8) & 0x3);
2099 USETW(req.wLength, sizeof(uint8_t));
2101 return (urtw_do_request(sc, &req, &data));
2105 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data)
2107 struct usb_device_request req;
2109 URTW_ASSERT_LOCKED(sc);
2111 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2112 req.bRequest = URTW_8187_SETREGS_REQ;
2113 USETW(req.wValue, (val & 0xff) | 0xff00);
2114 USETW(req.wIndex, (val >> 8) & 0x3);
2115 USETW(req.wLength, sizeof(uint16_t));
2117 return (urtw_do_request(sc, &req, &data));
2121 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data)
2123 struct usb_device_request req;
2125 URTW_ASSERT_LOCKED(sc);
2127 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2128 req.bRequest = URTW_8187_SETREGS_REQ;
2129 USETW(req.wValue, (val & 0xff) | 0xff00);
2130 USETW(req.wIndex, (val >> 8) & 0x3);
2131 USETW(req.wLength, sizeof(uint32_t));
2133 return (urtw_do_request(sc, &req, &data));
2137 urtw_get_macaddr(struct urtw_softc *sc)
2142 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data);
2145 sc->sc_bssid[0] = data & 0xff;
2146 sc->sc_bssid[1] = (data & 0xff00) >> 8;
2147 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data);
2150 sc->sc_bssid[2] = data & 0xff;
2151 sc->sc_bssid[3] = (data & 0xff00) >> 8;
2152 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data);
2155 sc->sc_bssid[4] = data & 0xff;
2156 sc->sc_bssid[5] = (data & 0xff00) >> 8;
2162 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data)
2164 #define URTW_READCMD_LEN 3
2166 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 };
2169 /* NB: make sure the buffer is initialized */
2172 /* enable EPROM programming */
2173 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE);
2174 DELAY(URTW_EPROM_DELAY);
2176 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE);
2179 error = urtw_eprom_ck(sc);
2182 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN);
2185 if (sc->sc_epromtype == URTW_EEPROM_93C56) {
2187 addrstr[0] = addr & (1 << 7);
2188 addrstr[1] = addr & (1 << 6);
2189 addrstr[2] = addr & (1 << 5);
2190 addrstr[3] = addr & (1 << 4);
2191 addrstr[4] = addr & (1 << 3);
2192 addrstr[5] = addr & (1 << 2);
2193 addrstr[6] = addr & (1 << 1);
2194 addrstr[7] = addr & (1 << 0);
2197 addrstr[0] = addr & (1 << 5);
2198 addrstr[1] = addr & (1 << 4);
2199 addrstr[2] = addr & (1 << 3);
2200 addrstr[3] = addr & (1 << 2);
2201 addrstr[4] = addr & (1 << 1);
2202 addrstr[5] = addr & (1 << 0);
2204 error = urtw_eprom_sendbits(sc, addrstr, addrlen);
2208 error = urtw_eprom_writebit(sc, 0);
2212 for (i = 0; i < 16; i++) {
2213 error = urtw_eprom_ck(sc);
2216 error = urtw_eprom_readbit(sc, &data16);
2220 (*data) |= (data16 << (15 - i));
2223 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE);
2226 error = urtw_eprom_ck(sc);
2230 /* now disable EPROM programming */
2231 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE);
2234 #undef URTW_READCMD_LEN
2238 urtw_eprom_cs(struct urtw_softc *sc, int able)
2243 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2244 if (able == URTW_EPROM_ENABLE)
2245 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS);
2247 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS);
2248 DELAY(URTW_EPROM_DELAY);
2254 urtw_eprom_ck(struct urtw_softc *sc)
2260 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2261 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK);
2262 DELAY(URTW_EPROM_DELAY);
2264 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2265 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK);
2266 DELAY(URTW_EPROM_DELAY);
2272 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data)
2277 urtw_read8_m(sc, URTW_EPROM_CMD, &data8);
2278 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0;
2279 DELAY(URTW_EPROM_DELAY);
2286 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit)
2291 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2293 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT);
2295 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT);
2296 DELAY(URTW_EPROM_DELAY);
2302 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen)
2305 usb_error_t error = 0;
2307 for (i = 0; i < buflen; i++) {
2308 error = urtw_eprom_writebit(sc, buf[i]);
2311 error = urtw_eprom_ck(sc);
2321 urtw_get_txpwr(struct urtw_softc *sc)
2327 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data);
2330 sc->sc_txpwr_cck_base = data & 0xf;
2331 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf;
2333 for (i = 1, j = 0; i < 6; i += 2, j++) {
2334 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data);
2337 sc->sc_txpwr_cck[i] = data & 0xf;
2338 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8;
2339 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4;
2340 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12;
2342 for (i = 1, j = 0; i < 4; i += 2, j++) {
2343 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data);
2346 sc->sc_txpwr_cck[i + 6] = data & 0xf;
2347 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8;
2348 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4;
2349 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12;
2351 if (sc->sc_flags & URTW_RTL8187B) {
2352 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data);
2355 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf;
2356 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4;
2357 error = urtw_eprom_read32(sc, 0x0a, &data);
2360 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf;
2361 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4;
2362 error = urtw_eprom_read32(sc, 0x1c, &data);
2365 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf;
2366 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8;
2367 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4;
2368 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12;
2370 for (i = 1, j = 0; i < 4; i += 2, j++) {
2371 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j,
2375 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf;
2376 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8;
2377 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4;
2378 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12;
2387 urtw_get_rfchip(struct urtw_softc *sc)
2394 if (sc->sc_flags & URTW_RTL8187B) {
2395 urtw_read8_m(sc, 0xe1, &data8);
2398 sc->sc_flags |= URTW_RTL8187B_REV_B;
2401 sc->sc_flags |= URTW_RTL8187B_REV_D;
2404 sc->sc_flags |= URTW_RTL8187B_REV_E;
2407 device_printf(sc->sc_dev, "unknown type: %#x\n", data8);
2408 sc->sc_flags |= URTW_RTL8187B_REV_B;
2412 urtw_read32_m(sc, URTW_TX_CONF, &data);
2413 switch (data & URTW_TX_HWMASK) {
2414 case URTW_TX_R8187vD_B:
2415 sc->sc_flags |= URTW_RTL8187B;
2417 case URTW_TX_R8187vD:
2420 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n",
2421 data & URTW_TX_HWMASK);
2426 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data);
2429 switch (data & 0xff) {
2430 case URTW_EPROM_RFCHIPID_RTL8225U:
2431 error = urtw_8225_isv2(sc, &ret);
2435 sc->sc_rf_init = urtw_8225_rf_init;
2436 sc->sc_rf_set_sens = urtw_8225_rf_set_sens;
2437 sc->sc_rf_set_chan = urtw_8225_rf_set_chan;
2438 sc->sc_rf_stop = urtw_8225_rf_stop;
2440 sc->sc_rf_init = urtw_8225v2_rf_init;
2441 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan;
2442 sc->sc_rf_stop = urtw_8225_rf_stop;
2444 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2445 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2447 case URTW_EPROM_RFCHIPID_RTL8225Z2:
2448 sc->sc_rf_init = urtw_8225v2b_rf_init;
2449 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan;
2450 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2451 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2452 sc->sc_rf_stop = urtw_8225_rf_stop;
2455 DPRINTF(sc, URTW_DEBUG_STATE,
2456 "unsupported RF chip %d\n", data & 0xff);
2457 error = USB_ERR_INVAL;
2461 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n",
2462 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l",
2463 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" :
2465 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" :
2466 (data8 == 1) ? "d" : "e") : "none");
2474 urtw_led_init(struct urtw_softc *sc)
2479 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr);
2480 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev);
2484 switch (rev & URTW_EPROM_CID_MASK) {
2485 case URTW_EPROM_CID_ALPHA0:
2486 sc->sc_strategy = URTW_SW_LED_MODE1;
2488 case URTW_EPROM_CID_SERCOMM_PS:
2489 sc->sc_strategy = URTW_SW_LED_MODE3;
2491 case URTW_EPROM_CID_HW_LED:
2492 sc->sc_strategy = URTW_HW_LED;
2494 case URTW_EPROM_CID_RSVD0:
2495 case URTW_EPROM_CID_RSVD1:
2497 sc->sc_strategy = URTW_SW_LED_MODE0;
2501 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0;
2509 urtw_8225_rf_init(struct urtw_softc *sc)
2511 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
2516 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2520 error = urtw_8225_usb_init(sc);
2524 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2525 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2526 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2527 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2529 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2532 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2533 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2537 error = urtw_8185_rf_pins_enable(sc);
2540 usb_pause_mtx(&sc->sc_mtx, 1000);
2542 for (i = 0; i < N(urtw_8225_rf_part1); i++) {
2543 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg,
2544 urtw_8225_rf_part1[i].val);
2545 usb_pause_mtx(&sc->sc_mtx, 1);
2547 usb_pause_mtx(&sc->sc_mtx, 100);
2549 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2550 usb_pause_mtx(&sc->sc_mtx, 200);
2552 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2553 usb_pause_mtx(&sc->sc_mtx, 200);
2555 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3);
2557 for (i = 0; i < 95; i++) {
2558 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2559 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]);
2563 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4);
2565 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5);
2567 for (i = 0; i < 128; i++) {
2568 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2569 usb_pause_mtx(&sc->sc_mtx, 1);
2570 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2571 usb_pause_mtx(&sc->sc_mtx, 1);
2574 for (i = 0; i < N(urtw_8225_rf_part2); i++) {
2575 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg,
2576 urtw_8225_rf_part2[i].val);
2577 usb_pause_mtx(&sc->sc_mtx, 1);
2580 error = urtw_8225_setgain(sc, 4);
2584 for (i = 0; i < N(urtw_8225_rf_part3); i++) {
2585 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg,
2586 urtw_8225_rf_part3[i].val);
2587 usb_pause_mtx(&sc->sc_mtx, 1);
2590 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2592 error = urtw_8225_set_txpwrlvl(sc, 1);
2596 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2597 usb_pause_mtx(&sc->sc_mtx, 1);
2598 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2599 usb_pause_mtx(&sc->sc_mtx, 1);
2601 /* TX ant A, 0x0 for B */
2602 error = urtw_8185_tx_antenna(sc, 0x3);
2605 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
2607 error = urtw_8225_rf_set_chan(sc, 1);
2614 urtw_8185_rf_pins_enable(struct urtw_softc *sc)
2616 usb_error_t error = 0;
2618 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7);
2624 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant)
2628 urtw_write8_m(sc, URTW_TX_ANTENNA, ant);
2629 usb_pause_mtx(&sc->sc_mtx, 1);
2635 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2639 return urtw_8187_write_phy(sc, addr, data);
2643 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2647 return urtw_8187_write_phy(sc, addr, data | 0x10000);
2651 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2656 phyw = ((data << 8) | (addr | 0x80));
2657 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24));
2658 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16));
2659 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8));
2660 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff)));
2661 usb_pause_mtx(&sc->sc_mtx, 1);
2667 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain)
2671 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]);
2672 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]);
2673 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]);
2674 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]);
2680 urtw_8225_usb_init(struct urtw_softc *sc)
2685 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0);
2686 urtw_write8_m(sc, URTW_GPIO, 0);
2687 error = urtw_read8e(sc, 0x53, &data);
2690 error = urtw_write8e(sc, 0x53, data | (1 << 7));
2693 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4);
2694 urtw_write8_m(sc, URTW_GPIO, 0x20);
2695 urtw_write8_m(sc, URTW_GP_ENABLE, 0);
2697 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80);
2698 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80);
2699 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80);
2701 usb_pause_mtx(&sc->sc_mtx, 500);
2707 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data)
2709 uint16_t d80, d82, d84;
2712 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80);
2713 d80 &= URTW_RF_PINS_MAGIC1;
2714 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82);
2715 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84);
2716 d84 &= URTW_RF_PINS_MAGIC2;
2717 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3);
2718 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3);
2721 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2723 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80);
2726 error = urtw_8225_write_s16(sc, addr, 0x8225, &data);
2730 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2732 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2733 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84);
2734 usb_pause_mtx(&sc->sc_mtx, 2);
2740 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index,
2745 struct usb_device_request req;
2746 usb_error_t error = 0;
2750 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2751 req.bRequest = URTW_8187_SETREGS_REQ;
2752 USETW(req.wValue, addr);
2753 USETW(req.wIndex, index);
2754 USETW(req.wLength, sizeof(uint16_t));
2755 buf[0] = (data16 & 0x00ff);
2756 buf[1] = (data16 & 0xff00) >> 8;
2758 error = urtw_do_request(sc, &req, buf);
2764 urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan)
2768 error = urtw_8225_set_txpwrlvl(sc, chan);
2771 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
2772 usb_pause_mtx(&sc->sc_mtx, 10);
2778 urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens)
2782 if (sens < 0 || sens > 6)
2787 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1);
2790 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2);
2793 error = urtw_8225_setgain(sc, sens);
2797 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]);
2804 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan)
2807 uint8_t *cck_pwltable;
2808 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max;
2809 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
2810 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
2813 cck_pwrlvl_max = 11;
2814 ofdm_pwrlvl_max = 25; /* 12 -> 25 */
2815 ofdm_pwrlvl_min = 10;
2817 /* CCK power setting */
2818 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
2819 idx = cck_pwrlvl % 6;
2820 set = cck_pwrlvl / 6;
2821 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 :
2822 urtw_8225_txpwr_cck;
2824 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
2825 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2826 for (i = 0; i < 8; i++) {
2827 urtw_8187_write_phy_cck(sc, 0x44 + i,
2828 cck_pwltable[idx * 8 + i]);
2830 usb_pause_mtx(&sc->sc_mtx, 1);
2832 /* OFDM power setting */
2833 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
2834 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
2835 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
2837 idx = ofdm_pwrlvl % 6;
2838 set = ofdm_pwrlvl / 6;
2840 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
2843 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
2844 urtw_8187_write_phy_ofdm(sc, 6, 0);
2845 urtw_8187_write_phy_ofdm(sc, 8, 0);
2847 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
2848 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2849 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]);
2850 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]);
2851 usb_pause_mtx(&sc->sc_mtx, 1);
2858 urtw_8225_rf_stop(struct urtw_softc *sc)
2863 urtw_8225_write(sc, 0x4, 0x1f);
2865 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2869 urtw_read8_m(sc, URTW_CONFIG3, &data);
2870 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
2871 if (sc->sc_flags & URTW_RTL8187B) {
2872 urtw_write32_m(sc, URTW_ANAPARAM2,
2873 URTW_8187B_8225_ANAPARAM2_OFF);
2874 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF);
2875 urtw_write32_m(sc, URTW_ANAPARAM3,
2876 URTW_8187B_8225_ANAPARAM3_OFF);
2878 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF);
2879 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF);
2882 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
2883 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2892 urtw_8225v2_rf_init(struct urtw_softc *sc)
2894 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
2900 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2904 error = urtw_8225_usb_init(sc);
2908 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2909 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2910 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2911 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2913 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2916 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2917 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2921 error = urtw_8185_rf_pins_enable(sc);
2925 usb_pause_mtx(&sc->sc_mtx, 500);
2927 for (i = 0; i < N(urtw_8225v2_rf_part1); i++) {
2928 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg,
2929 urtw_8225v2_rf_part1[i].val);
2931 usb_pause_mtx(&sc->sc_mtx, 50);
2934 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1);
2936 for (i = 0; i < 95; i++) {
2937 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2938 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
2939 urtw_8225v2_rxgain[i]);
2943 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1);
2945 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1);
2947 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2);
2949 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2950 usb_pause_mtx(&sc->sc_mtx, 100);
2952 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2953 usb_pause_mtx(&sc->sc_mtx, 100);
2955 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2958 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1)
2959 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32);
2960 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) {
2962 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2963 usb_pause_mtx(&sc->sc_mtx, 100);
2965 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2966 usb_pause_mtx(&sc->sc_mtx, 50);
2967 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2970 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2))
2971 device_printf(sc->sc_dev, "RF calibration failed\n");
2973 usb_pause_mtx(&sc->sc_mtx, 100);
2976 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6);
2977 for (i = 0; i < 128; i++) {
2978 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2979 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2982 for (i = 0; i < N(urtw_8225v2_rf_part2); i++) {
2983 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg,
2984 urtw_8225v2_rf_part2[i].val);
2987 error = urtw_8225v2_setgain(sc, 4);
2991 for (i = 0; i < N(urtw_8225v2_rf_part3); i++) {
2992 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg,
2993 urtw_8225v2_rf_part3[i].val);
2996 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2998 error = urtw_8225v2_set_txpwrlvl(sc, 1);
3002 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
3003 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
3005 /* TX ant A, 0x0 for B */
3006 error = urtw_8185_tx_antenna(sc, 0x3);
3009 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
3011 error = urtw_8225_rf_set_chan(sc, 1);
3018 urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan)
3022 error = urtw_8225v2_set_txpwrlvl(sc, chan);
3026 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3027 usb_pause_mtx(&sc->sc_mtx, 10);
3033 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data)
3037 uint8_t rlen = 12, wlen = 6;
3038 uint16_t o1, o2, o3, tmp;
3039 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27;
3040 uint32_t mask = 0x80000000, value = 0;
3043 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1);
3044 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2);
3045 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3);
3046 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4);
3047 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4);
3048 o1 &= ~URTW_RF_PINS_MAGIC4;
3049 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN);
3051 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1);
3054 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) {
3055 bit = ((d2w & mask) != 0) ? 1 : 0;
3057 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3059 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3060 URTW_BB_HOST_BANG_CLK);
3062 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3063 URTW_BB_HOST_BANG_CLK);
3068 bit = ((d2w & mask) != 0) ? 1 : 0;
3069 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3070 URTW_BB_HOST_BANG_CLK);
3072 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3073 URTW_BB_HOST_BANG_CLK);
3075 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3078 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW |
3079 URTW_BB_HOST_BANG_CLK);
3081 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW);
3083 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW);
3087 for (i = 0; i < rlen; i++, mask = mask >> 1) {
3088 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3089 o1 | URTW_BB_HOST_BANG_RW);
3091 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3092 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3094 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3095 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3097 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3098 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3101 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp);
3102 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0);
3103 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3104 o1 | URTW_BB_HOST_BANG_RW);
3108 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN |
3109 URTW_BB_HOST_BANG_RW);
3112 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2);
3113 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3);
3114 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1);
3124 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan)
3127 uint8_t *cck_pwrtable;
3128 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10;
3129 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3130 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3133 /* CCK power setting */
3134 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
3135 cck_pwrlvl += sc->sc_txpwr_cck_base;
3136 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3137 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 :
3138 urtw_8225v2_txpwr_cck;
3140 for (i = 0; i < 8; i++)
3141 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3143 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3144 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]);
3145 usb_pause_mtx(&sc->sc_mtx, 1);
3147 /* OFDM power setting */
3148 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
3149 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
3150 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3151 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3153 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3157 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
3158 urtw_8187_write_phy_ofdm(sc, 5, 0x0);
3159 urtw_8187_write_phy_ofdm(sc, 6, 0x40);
3160 urtw_8187_write_phy_ofdm(sc, 7, 0x0);
3161 urtw_8187_write_phy_ofdm(sc, 8, 0x40);
3163 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3164 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]);
3165 usb_pause_mtx(&sc->sc_mtx, 1);
3171 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain)
3177 gainp = urtw_8225v2_gain_bg;
3178 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]);
3179 usb_pause_mtx(&sc->sc_mtx, 1);
3180 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]);
3181 usb_pause_mtx(&sc->sc_mtx, 1);
3182 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]);
3183 usb_pause_mtx(&sc->sc_mtx, 1);
3184 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17);
3185 usb_pause_mtx(&sc->sc_mtx, 1);
3191 urtw_8225_isv2(struct urtw_softc *sc, int *ret)
3198 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5);
3199 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5);
3200 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5);
3201 usb_pause_mtx(&sc->sc_mtx, 500);
3203 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3204 URTW_8225_ADDR_0_DATA_MAGIC1);
3206 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data);
3209 if (data != URTW_8225_ADDR_8_DATA_MAGIC1)
3212 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data);
3215 if (data != URTW_8225_ADDR_9_DATA_MAGIC1)
3219 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3220 URTW_8225_ADDR_0_DATA_MAGIC2);
3226 urtw_8225v2b_rf_init(struct urtw_softc *sc)
3228 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
3233 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3238 * initialize extra registers on 8187
3240 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff);
3243 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3244 data8 |= URTW_CW_CONF_PERPACKET_RETRY;
3245 urtw_write8_m(sc, URTW_CW_CONF, data8);
3248 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3249 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN;
3250 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3252 /* Auto Rate Fallback Control */
3253 #define URTW_ARFR 0x1e0
3254 urtw_write16_m(sc, URTW_ARFR, 0xfff);
3255 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8);
3256 urtw_write8_m(sc, URTW_RATE_FALLBACK,
3257 data8 | URTW_RATE_FALLBACK_ENABLE);
3259 urtw_read8_m(sc, URTW_MSR, &data8);
3260 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3);
3261 urtw_read8_m(sc, URTW_MSR, &data8);
3262 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA);
3263 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl);
3265 urtw_write16_m(sc, URTW_ATIM_WND, 2);
3266 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
3267 #define URTW_FEMR_FOR_8187B 0x1d4
3268 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff);
3271 urtw_read8_m(sc, URTW_CONFIG1, &data8);
3272 data8 = (data8 & 0x3f) | 0x80;
3273 urtw_write8_m(sc, URTW_CONFIG1, data8);
3275 /* applying MAC address again. */
3276 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)sc->sc_bssid)[0]);
3277 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)sc->sc_bssid)[1] & 0xffff);
3279 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3283 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
3288 for (i = 0; i < N(urtw_8225v2b_rf_part1); i++)
3289 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg,
3290 urtw_8225v2b_rf_part1[i].val);
3291 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50);
3292 urtw_write16_m(sc, URTW_INT_MIG, 0x0000);
3293 urtw_write32_m(sc, 0x1f0, 0);
3294 urtw_write32_m(sc, 0x1f4, 0);
3295 urtw_write8_m(sc, 0x1f8, 0);
3296 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001);
3298 #define URTW_RFSW_CTRL 0x272
3299 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a);
3304 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3307 urtw_read8_m(sc, URTW_CONFIG3, &data8);
3308 urtw_write8_m(sc, URTW_CONFIG3,
3309 data8 | URTW_CONFIG3_ANAPARAM_WRITE);
3311 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3315 /* setup RFE initial timing */
3316 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480);
3317 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488);
3318 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff);
3319 usb_pause_mtx(&sc->sc_mtx, 1100);
3321 for (i = 0; i < N(urtw_8225v2b_rf_part0); i++) {
3322 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg,
3323 urtw_8225v2b_rf_part0[i].val);
3324 usb_pause_mtx(&sc->sc_mtx, 1);
3326 urtw_8225_write(sc, 0x00, 0x01b7);
3328 for (i = 0; i < 95; i++) {
3329 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
3330 usb_pause_mtx(&sc->sc_mtx, 1);
3331 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
3332 urtw_8225v2b_rxgain[i]);
3333 usb_pause_mtx(&sc->sc_mtx, 1);
3336 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080);
3337 usb_pause_mtx(&sc->sc_mtx, 1);
3338 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004);
3339 usb_pause_mtx(&sc->sc_mtx, 1);
3340 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7);
3341 usb_pause_mtx(&sc->sc_mtx, 1);
3342 usb_pause_mtx(&sc->sc_mtx, 3000);
3343 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d);
3344 usb_pause_mtx(&sc->sc_mtx, 2000);
3345 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d);
3346 usb_pause_mtx(&sc->sc_mtx, 1);
3347 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf);
3348 usb_pause_mtx(&sc->sc_mtx, 1);
3350 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03);
3351 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07);
3352 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03);
3354 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12);
3355 for (i = 0; i < 128; i++) {
3356 uint32_t addr, data;
3358 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f;
3359 addr = ((i + 0x80) << 8) | 0x0000008e;
3361 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff);
3362 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff);
3363 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00);
3365 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10);
3367 for (i = 0; i < N(urtw_8225v2b_rf_part2); i++)
3368 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val);
3370 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c);
3371 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c);
3372 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c);
3373 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c);
3375 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46);
3376 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6);
3377 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc);
3378 urtw_8187_write_phy_cck(sc, 0xc1, 0x88);
3386 urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan)
3390 error = urtw_8225v2b_set_txpwrlvl(sc, chan);
3394 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3395 usb_pause_mtx(&sc->sc_mtx, 10);
3401 urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan)
3404 uint8_t *cck_pwrtable;
3405 uint8_t cck_pwrlvl_max = 15;
3406 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3407 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3410 /* CCK power setting */
3411 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ?
3412 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) :
3413 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7));
3414 cck_pwrlvl += sc->sc_txpwr_cck_base;
3415 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3416 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 :
3417 urtw_8225v2b_txpwr_cck;
3419 if (sc->sc_flags & URTW_RTL8187B_REV_B)
3420 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 :
3421 ((cck_pwrlvl <= 11) ? 8 : 16);
3423 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 :
3424 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24));
3426 for (i = 0; i < 8; i++)
3427 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3429 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3430 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1);
3431 usb_pause_mtx(&sc->sc_mtx, 1);
3433 /* OFDM power setting */
3434 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ?
3435 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) :
3436 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10));
3437 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3438 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3440 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3441 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1);
3443 if (sc->sc_flags & URTW_RTL8187B_REV_B) {
3444 if (ofdm_pwrlvl <= 11) {
3445 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60);
3446 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60);
3448 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3449 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3452 if (ofdm_pwrlvl <= 11) {
3453 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3454 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3455 } else if (ofdm_pwrlvl <= 17) {
3456 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54);
3457 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54);
3459 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50);
3460 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50);
3463 usb_pause_mtx(&sc->sc_mtx, 1);
3469 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data)
3471 struct usb_device_request req;
3474 req.bmRequestType = UT_READ_VENDOR_DEVICE;
3475 req.bRequest = URTW_8187_GETREGS_REQ;
3476 USETW(req.wValue, val | 0xfe00);
3477 USETW(req.wIndex, 0);
3478 USETW(req.wLength, sizeof(uint8_t));
3480 error = urtw_do_request(sc, &req, data);
3485 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data)
3487 struct usb_device_request req;
3489 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
3490 req.bRequest = URTW_8187_SETREGS_REQ;
3491 USETW(req.wValue, val | 0xfe00);
3492 USETW(req.wIndex, 0);
3493 USETW(req.wLength, sizeof(uint8_t));
3495 return (urtw_do_request(sc, &req, &data));
3499 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val)
3504 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3508 urtw_read8_m(sc, URTW_CONFIG3, &data);
3509 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3510 urtw_write32_m(sc, URTW_ANAPARAM, val);
3511 urtw_read8_m(sc, URTW_CONFIG3, &data);
3512 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3514 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3522 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val)
3527 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3531 urtw_read8_m(sc, URTW_CONFIG3, &data);
3532 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3533 urtw_write32_m(sc, URTW_ANAPARAM2, val);
3534 urtw_read8_m(sc, URTW_CONFIG3, &data);
3535 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3537 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3545 urtw_intr_enable(struct urtw_softc *sc)
3549 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff);
3555 urtw_intr_disable(struct urtw_softc *sc)
3559 urtw_write16_m(sc, URTW_INTR_MASK, 0);
3565 urtw_reset(struct urtw_softc *sc)
3570 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3573 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3577 error = urtw_intr_disable(sc);
3580 usb_pause_mtx(&sc->sc_mtx, 100);
3582 error = urtw_write8e(sc, 0x18, 0x10);
3585 error = urtw_write8e(sc, 0x18, 0x11);
3588 error = urtw_write8e(sc, 0x18, 0x00);
3591 usb_pause_mtx(&sc->sc_mtx, 100);
3593 urtw_read8_m(sc, URTW_CMD, &data);
3594 data = (data & 0x2) | URTW_CMD_RST;
3595 urtw_write8_m(sc, URTW_CMD, data);
3596 usb_pause_mtx(&sc->sc_mtx, 100);
3598 urtw_read8_m(sc, URTW_CMD, &data);
3599 if (data & URTW_CMD_RST) {
3600 device_printf(sc->sc_dev, "reset timeout\n");
3604 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD);
3607 usb_pause_mtx(&sc->sc_mtx, 100);
3609 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3612 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3620 urtw_led_ctl(struct urtw_softc *sc, int mode)
3622 usb_error_t error = 0;
3624 switch (sc->sc_strategy) {
3625 case URTW_SW_LED_MODE0:
3626 error = urtw_led_mode0(sc, mode);
3628 case URTW_SW_LED_MODE1:
3629 error = urtw_led_mode1(sc, mode);
3631 case URTW_SW_LED_MODE2:
3632 error = urtw_led_mode2(sc, mode);
3634 case URTW_SW_LED_MODE3:
3635 error = urtw_led_mode3(sc, mode);
3638 DPRINTF(sc, URTW_DEBUG_STATE,
3639 "unsupported LED mode %d\n", sc->sc_strategy);
3640 error = USB_ERR_INVAL;
3648 urtw_led_mode0(struct urtw_softc *sc, int mode)
3652 case URTW_LED_CTL_POWER_ON:
3653 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK;
3655 case URTW_LED_CTL_TX:
3656 if (sc->sc_gpio_ledinprogress == 1)
3659 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL;
3660 sc->sc_gpio_blinktime = 2;
3662 case URTW_LED_CTL_LINK:
3663 sc->sc_gpio_ledstate = URTW_LED_ON;
3666 DPRINTF(sc, URTW_DEBUG_STATE,
3667 "unsupported LED mode 0x%x", mode);
3668 return (USB_ERR_INVAL);
3671 switch (sc->sc_gpio_ledstate) {
3673 if (sc->sc_gpio_ledinprogress != 0)
3675 urtw_led_on(sc, URTW_LED_GPIO);
3677 case URTW_LED_BLINK_NORMAL:
3678 if (sc->sc_gpio_ledinprogress != 0)
3680 sc->sc_gpio_ledinprogress = 1;
3681 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ?
3682 URTW_LED_OFF : URTW_LED_ON;
3683 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3685 case URTW_LED_POWER_ON_BLINK:
3686 urtw_led_on(sc, URTW_LED_GPIO);
3687 usb_pause_mtx(&sc->sc_mtx, 100);
3688 urtw_led_off(sc, URTW_LED_GPIO);
3691 DPRINTF(sc, URTW_DEBUG_STATE,
3692 "unknown LED status 0x%x", sc->sc_gpio_ledstate);
3693 return (USB_ERR_INVAL);
3699 urtw_led_mode1(struct urtw_softc *sc, int mode)
3701 return (USB_ERR_INVAL);
3705 urtw_led_mode2(struct urtw_softc *sc, int mode)
3707 return (USB_ERR_INVAL);
3711 urtw_led_mode3(struct urtw_softc *sc, int mode)
3713 return (USB_ERR_INVAL);
3717 urtw_led_on(struct urtw_softc *sc, int type)
3721 if (type == URTW_LED_GPIO) {
3722 switch (sc->sc_gpio_ledpin) {
3723 case URTW_LED_PIN_GPIO0:
3724 urtw_write8_m(sc, URTW_GPIO, 0x01);
3725 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00);
3728 DPRINTF(sc, URTW_DEBUG_STATE,
3729 "unsupported LED PIN type 0x%x",
3730 sc->sc_gpio_ledpin);
3731 error = USB_ERR_INVAL;
3735 DPRINTF(sc, URTW_DEBUG_STATE,
3736 "unsupported LED type 0x%x", type);
3737 error = USB_ERR_INVAL;
3741 sc->sc_gpio_ledon = 1;
3747 urtw_led_off(struct urtw_softc *sc, int type)
3751 if (type == URTW_LED_GPIO) {
3752 switch (sc->sc_gpio_ledpin) {
3753 case URTW_LED_PIN_GPIO0:
3754 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1);
3756 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1);
3759 DPRINTF(sc, URTW_DEBUG_STATE,
3760 "unsupported LED PIN type 0x%x",
3761 sc->sc_gpio_ledpin);
3762 error = USB_ERR_INVAL;
3766 DPRINTF(sc, URTW_DEBUG_STATE,
3767 "unsupported LED type 0x%x", type);
3768 error = USB_ERR_INVAL;
3772 sc->sc_gpio_ledon = 0;
3779 urtw_led_ch(void *arg)
3781 struct urtw_softc *sc = arg;
3782 struct ifnet *ifp = sc->sc_ifp;
3783 struct ieee80211com *ic = ifp->if_l2com;
3785 ieee80211_runtask(ic, &sc->sc_led_task);
3789 urtw_ledtask(void *arg, int pending)
3791 struct urtw_softc *sc = arg;
3793 if (sc->sc_strategy != URTW_SW_LED_MODE0) {
3794 DPRINTF(sc, URTW_DEBUG_STATE,
3795 "could not process a LED strategy 0x%x",
3806 urtw_led_blink(struct urtw_softc *sc)
3811 if (sc->sc_gpio_blinkstate == URTW_LED_ON)
3812 error = urtw_led_on(sc, URTW_LED_GPIO);
3814 error = urtw_led_off(sc, URTW_LED_GPIO);
3815 sc->sc_gpio_blinktime--;
3816 if (sc->sc_gpio_blinktime == 0)
3819 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL &&
3820 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY &&
3821 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3)
3825 if (sc->sc_gpio_ledstate == URTW_LED_ON &&
3826 sc->sc_gpio_ledon == 0)
3827 error = urtw_led_on(sc, URTW_LED_GPIO);
3828 else if (sc->sc_gpio_ledstate == URTW_LED_OFF &&
3829 sc->sc_gpio_ledon == 1)
3830 error = urtw_led_off(sc, URTW_LED_GPIO);
3832 sc->sc_gpio_blinktime = 0;
3833 sc->sc_gpio_ledinprogress = 0;
3837 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ?
3838 URTW_LED_ON : URTW_LED_OFF;
3840 switch (sc->sc_gpio_ledstate) {
3841 case URTW_LED_BLINK_NORMAL:
3842 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3845 DPRINTF(sc, URTW_DEBUG_STATE,
3846 "unknown LED status 0x%x",
3847 sc->sc_gpio_ledstate);
3848 return (USB_ERR_INVAL);
3854 urtw_rx_enable(struct urtw_softc *sc)
3859 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ?
3860 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]);
3862 error = urtw_rx_setconf(sc);
3866 if ((sc->sc_flags & URTW_RTL8187B) == 0) {
3867 urtw_read8_m(sc, URTW_CMD, &data);
3868 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE);
3875 urtw_tx_enable(struct urtw_softc *sc)
3881 if (sc->sc_flags & URTW_RTL8187B) {
3882 urtw_read32_m(sc, URTW_TX_CONF, &data);
3883 data &= ~URTW_TX_LOOPBACK_MASK;
3884 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3885 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3886 data &= ~URTW_TX_SWPLCPLEN;
3887 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE |
3888 (7 << 8) | /* short retry limit */
3889 (7 << 0) | /* long retry limit */
3890 (7 << 21); /* MAX TX DMA */
3891 urtw_write32_m(sc, URTW_TX_CONF, data);
3893 urtw_read8_m(sc, URTW_MSR, &data8);
3894 data8 |= URTW_MSR_LINK_ENEDCA;
3895 urtw_write8_m(sc, URTW_MSR, data8);
3899 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3900 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY);
3901 urtw_write8_m(sc, URTW_CW_CONF, data8);
3903 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3904 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN;
3905 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL;
3906 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT;
3907 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3909 urtw_read32_m(sc, URTW_TX_CONF, &data);
3910 data &= ~URTW_TX_LOOPBACK_MASK;
3911 data |= URTW_TX_LOOPBACK_NONE;
3912 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3913 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT;
3914 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT;
3915 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3916 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW;
3917 data &= ~URTW_TX_SWPLCPLEN;
3918 data |= URTW_TX_NOICV;
3919 urtw_write32_m(sc, URTW_TX_CONF, data);
3921 urtw_read8_m(sc, URTW_CMD, &data8);
3922 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE);
3928 urtw_rx_setconf(struct urtw_softc *sc)
3930 struct ifnet *ifp = sc->sc_ifp;
3931 struct ieee80211com *ic = ifp->if_l2com;
3935 urtw_read32_m(sc, URTW_RX, &data);
3936 data = data &~ URTW_RX_FILTER_MASK;
3937 if (sc->sc_flags & URTW_RTL8187B) {
3938 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA |
3939 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST |
3940 URTW_RX_FILTER_NICMAC | URTW_RX_CHECK_BSSID |
3941 URTW_RX_FIFO_THRESHOLD_NONE |
3942 URTW_MAX_RX_DMA_2048 |
3943 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT;
3945 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA;
3946 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST;
3948 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
3949 data = data | URTW_RX_FILTER_ICVERR;
3950 data = data | URTW_RX_FILTER_PWR;
3952 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR)
3953 data = data | URTW_RX_FILTER_CRCERR;
3955 if (ic->ic_opmode == IEEE80211_M_MONITOR ||
3956 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) {
3957 data = data | URTW_RX_FILTER_ALLMAC;
3959 data = data | URTW_RX_FILTER_NICMAC;
3960 data = data | URTW_RX_CHECK_BSSID;
3963 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK;
3964 data = data | URTW_RX_FIFO_THRESHOLD_NONE |
3965 URTW_RX_AUTORESETPHY;
3966 data = data &~ URTW_MAX_RX_DMA_MASK;
3967 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT;
3970 urtw_write32_m(sc, URTW_RX, data);
3975 static struct mbuf *
3976 urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p,
3979 int actlen, flen, rssi;
3980 struct ieee80211_frame *wh;
3981 struct mbuf *m, *mnew;
3982 struct urtw_softc *sc = data->sc;
3983 struct ifnet *ifp = sc->sc_ifp;
3984 struct ieee80211com *ic = ifp->if_l2com;
3985 uint8_t noise = 0, rate;
3987 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
3989 if (actlen < (int)URTW_MIN_RXBUFSZ) {
3994 if (sc->sc_flags & URTW_RTL8187B) {
3995 struct urtw_8187b_rxhdr *rx;
3997 rx = (struct urtw_8187b_rxhdr *)(data->buf +
3998 (actlen - (sizeof(struct urtw_8187b_rxhdr))));
3999 flen = le32toh(rx->flag) & 0xfff;
4000 if (flen > actlen) {
4004 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
4006 rssi = rx->rssi & URTW_RX_RSSI_MASK;
4009 struct urtw_8187l_rxhdr *rx;
4011 rx = (struct urtw_8187l_rxhdr *)(data->buf +
4012 (actlen - (sizeof(struct urtw_8187l_rxhdr))));
4013 flen = le32toh(rx->flag) & 0xfff;
4014 if (flen > actlen) {
4019 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
4021 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK;
4025 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
4033 data->buf = mtod(mnew, uint8_t *);
4036 m->m_pkthdr.rcvif = ifp;
4037 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN;
4039 if (ieee80211_radiotap_active(ic)) {
4040 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap;
4042 /* XXX Are variables correct? */
4043 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
4044 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
4045 tap->wr_dbm_antsignal = (int8_t)rssi;
4048 wh = mtod(m, struct ieee80211_frame *);
4049 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA)
4050 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate;
4053 *nf_p = noise; /* XXX correct? */
4059 urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
4061 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4062 struct ifnet *ifp = sc->sc_ifp;
4063 struct ieee80211com *ic = ifp->if_l2com;
4064 struct ieee80211_frame *wh;
4065 struct ieee80211_node *ni;
4066 struct mbuf *m = NULL;
4067 struct urtw_data *data;
4071 URTW_ASSERT_LOCKED(sc);
4073 switch (USB_GET_STATE(xfer)) {
4074 case USB_ST_TRANSFERRED:
4075 data = STAILQ_FIRST(&sc->sc_rx_active);
4078 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4079 m = urtw_rxeof(xfer, data, &rssi, &nf);
4080 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4084 data = STAILQ_FIRST(&sc->sc_rx_inactive);
4086 KASSERT(m == NULL, ("mbuf isn't NULL"));
4089 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
4090 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
4091 usbd_xfer_set_frame_data(xfer, 0, data->buf,
4092 usbd_xfer_max_len(xfer));
4093 usbd_transfer_submit(xfer);
4096 * To avoid LOR we should unlock our private mutex here to call
4097 * ieee80211_input() because here is at the end of a USB
4098 * callback and safe to unlock.
4102 wh = mtod(m, struct ieee80211_frame *);
4103 ni = ieee80211_find_rxnode(ic,
4104 (struct ieee80211_frame_min *)wh);
4106 (void) ieee80211_input(ni, m, rssi, nf);
4107 /* node is no longer needed */
4108 ieee80211_free_node(ni);
4110 (void) ieee80211_input_all(ic, m, rssi, nf);
4116 /* needs it to the inactive queue due to a error. */
4117 data = STAILQ_FIRST(&sc->sc_rx_active);
4119 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4120 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4122 if (error != USB_ERR_CANCELLED) {
4123 usbd_xfer_set_stall(xfer);
4131 #define URTW_STATUS_TYPE_TXCLOSE 1
4132 #define URTW_STATUS_TYPE_BEACON_INTR 0
4135 urtw_txstatus_eof(struct usb_xfer *xfer)
4137 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4138 struct ifnet *ifp = sc->sc_ifp;
4139 int actlen, type, pktretry, seq;
4142 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
4144 if (actlen != sizeof(uint64_t))
4147 val = le64toh(sc->sc_txstatus);
4148 type = (val >> 30) & 0x3;
4149 if (type == URTW_STATUS_TYPE_TXCLOSE) {
4150 pktretry = val & 0xff;
4151 seq = (val >> 16) & 0xff;
4152 if (pktretry == URTW_TX_MAXRETRY)
4154 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n",
4160 urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error)
4162 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4163 struct ifnet *ifp = sc->sc_ifp;
4164 void *dma_buf = usbd_xfer_get_frame_buffer(xfer, 0);
4166 URTW_ASSERT_LOCKED(sc);
4168 switch (USB_GET_STATE(xfer)) {
4169 case USB_ST_TRANSFERRED:
4170 urtw_txstatus_eof(xfer);
4174 memcpy(dma_buf, &sc->sc_txstatus, sizeof(uint64_t));
4175 usbd_xfer_set_frame_len(xfer, 0, sizeof(uint64_t));
4176 usbd_transfer_submit(xfer);
4179 if (error != USB_ERR_CANCELLED) {
4180 usbd_xfer_set_stall(xfer);
4189 urtw_txeof(struct usb_xfer *xfer, struct urtw_data *data)
4191 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4192 struct ifnet *ifp = sc->sc_ifp;
4195 URTW_ASSERT_LOCKED(sc);
4198 * Do any tx complete callback. Note this must be done before releasing
4199 * the node reference.
4203 if (m->m_flags & M_TXCB) {
4205 ieee80211_process_callback(data->ni, m, 0);
4211 ieee80211_free_node(data->ni);
4216 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4220 urtw_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error)
4222 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4223 struct ifnet *ifp = sc->sc_ifp;
4224 struct urtw_data *data;
4226 URTW_ASSERT_LOCKED(sc);
4228 switch (USB_GET_STATE(xfer)) {
4229 case USB_ST_TRANSFERRED:
4230 data = STAILQ_FIRST(&sc->sc_tx_active);
4233 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
4234 urtw_txeof(xfer, data);
4235 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next);
4239 data = STAILQ_FIRST(&sc->sc_tx_pending);
4241 DPRINTF(sc, URTW_DEBUG_XMIT,
4242 "%s: empty pending queue\n", __func__);
4245 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next);
4246 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next);
4248 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen);
4249 usbd_transfer_submit(xfer);
4256 data = STAILQ_FIRST(&sc->sc_tx_active);
4259 if (data->ni != NULL) {
4260 ieee80211_free_node(data->ni);
4264 if (error != USB_ERR_CANCELLED) {
4265 usbd_xfer_set_stall(xfer);
4272 static struct urtw_data *
4273 _urtw_getbuf(struct urtw_softc *sc)
4275 struct urtw_data *bf;
4277 bf = STAILQ_FIRST(&sc->sc_tx_inactive);
4279 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next);
4283 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__,
4284 "out of xmit buffers");
4288 static struct urtw_data *
4289 urtw_getbuf(struct urtw_softc *sc)
4291 struct urtw_data *bf;
4293 URTW_ASSERT_LOCKED(sc);
4295 bf = _urtw_getbuf(sc);
4297 struct ifnet *ifp = sc->sc_ifp;
4299 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__);
4300 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4306 urtw_isbmode(uint16_t rate)
4309 return ((rate <= 22 && rate != 12 && rate != 18) ||
4310 rate == 44) ? (1) : (0);
4314 urtw_rate2dbps(uint16_t rate)
4334 urtw_compute_txtime(uint16_t framelen, uint16_t rate,
4335 uint8_t ismgt, uint8_t isshort)
4337 uint16_t ceiling, frametime, n_dbps;
4339 if (urtw_isbmode(rate)) {
4340 if (ismgt || !isshort || rate == 2)
4341 frametime = (uint16_t)(144 + 48 +
4342 (framelen * 8 / (rate / 2)));
4344 frametime = (uint16_t)(72 + 24 +
4345 (framelen * 8 / (rate / 2)));
4346 if ((framelen * 8 % (rate / 2)) != 0)
4349 n_dbps = urtw_rate2dbps(rate);
4350 ceiling = (16 + 8 * framelen + 6) / n_dbps
4351 + (((16 + 8 * framelen + 6) % n_dbps) ? 1 : 0);
4352 frametime = (uint16_t)(16 + 4 + 4 * ceiling + 6);
4358 * Callback from the 802.11 layer to update the
4359 * slot time based on the current setting.
4362 urtw_updateslot(struct ifnet *ifp)
4364 struct urtw_softc *sc = ifp->if_softc;
4365 struct ieee80211com *ic = ifp->if_l2com;
4367 ieee80211_runtask(ic, &sc->sc_updateslot_task);
4371 urtw_updateslottask(void *arg, int pending)
4373 struct urtw_softc *sc = arg;
4374 struct ifnet *ifp = sc->sc_ifp;
4375 struct ieee80211com *ic = ifp->if_l2com;
4378 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
4382 if (sc->sc_flags & URTW_RTL8187B) {
4383 urtw_write8_m(sc, URTW_SIFS, 0x22);
4384 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
4385 urtw_write8_m(sc, URTW_SLOT, 0x9);
4387 urtw_write8_m(sc, URTW_SLOT, 0x14);
4388 urtw_write8_m(sc, URTW_8187B_EIFS, 0x5b);
4389 urtw_write8_m(sc, URTW_CARRIER_SCOUNT, 0x5b);
4391 urtw_write8_m(sc, URTW_SIFS, 0x22);
4392 if (sc->sc_state == IEEE80211_S_ASSOC &&
4393 ic->ic_flags & IEEE80211_F_SHSLOT)
4394 urtw_write8_m(sc, URTW_SLOT, 0x9);
4396 urtw_write8_m(sc, URTW_SLOT, 0x14);
4397 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
4398 urtw_write8_m(sc, URTW_DIFS, 0x14);
4399 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14);
4400 urtw_write8_m(sc, URTW_CW_VAL, 0x73);
4402 urtw_write8_m(sc, URTW_DIFS, 0x24);
4403 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24);
4404 urtw_write8_m(sc, URTW_CW_VAL, 0xa5);
4412 urtw_sysctl_node(struct urtw_softc *sc)
4414 #define URTW_SYSCTL_STAT_ADD32(c, h, n, p, d) \
4415 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
4416 struct sysctl_ctx_list *ctx;
4417 struct sysctl_oid_list *child, *parent;
4418 struct sysctl_oid *tree;
4419 struct urtw_stats *stats = &sc->sc_stats;
4421 ctx = device_get_sysctl_ctx(sc->sc_dev);
4422 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev));
4424 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
4425 NULL, "URTW statistics");
4426 parent = SYSCTL_CHILDREN(tree);
4428 /* Tx statistics. */
4429 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
4430 NULL, "Tx MAC statistics");
4431 child = SYSCTL_CHILDREN(tree);
4432 URTW_SYSCTL_STAT_ADD32(ctx, child, "1m", &stats->txrates[0],
4434 URTW_SYSCTL_STAT_ADD32(ctx, child, "2m", &stats->txrates[1],
4436 URTW_SYSCTL_STAT_ADD32(ctx, child, "5.5m", &stats->txrates[2],
4438 URTW_SYSCTL_STAT_ADD32(ctx, child, "6m", &stats->txrates[4],
4440 URTW_SYSCTL_STAT_ADD32(ctx, child, "9m", &stats->txrates[5],
4442 URTW_SYSCTL_STAT_ADD32(ctx, child, "11m", &stats->txrates[3],
4444 URTW_SYSCTL_STAT_ADD32(ctx, child, "12m", &stats->txrates[6],
4446 URTW_SYSCTL_STAT_ADD32(ctx, child, "18m", &stats->txrates[7],
4448 URTW_SYSCTL_STAT_ADD32(ctx, child, "24m", &stats->txrates[8],
4450 URTW_SYSCTL_STAT_ADD32(ctx, child, "36m", &stats->txrates[9],
4452 URTW_SYSCTL_STAT_ADD32(ctx, child, "48m", &stats->txrates[10],
4454 URTW_SYSCTL_STAT_ADD32(ctx, child, "54m", &stats->txrates[11],
4456 #undef URTW_SYSCTL_STAT_ADD32
4459 static device_method_t urtw_methods[] = {
4460 DEVMETHOD(device_probe, urtw_match),
4461 DEVMETHOD(device_attach, urtw_attach),
4462 DEVMETHOD(device_detach, urtw_detach),
4465 static driver_t urtw_driver = {
4467 .methods = urtw_methods,
4468 .size = sizeof(struct urtw_softc)
4470 static devclass_t urtw_devclass;
4472 DRIVER_MODULE(urtw, uhub, urtw_driver, urtw_devclass, NULL, 0);
4473 MODULE_DEPEND(urtw, wlan, 1, 1, 1);
4474 MODULE_DEPEND(urtw, usb, 1, 1, 1);
4475 MODULE_VERSION(urtw, 1);