2 * Copyright(c) 2002-2011 Exar Corp.
5 * Redistribution and use in source and binary forms, with or without
6 * modification are permitted provided the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Exar Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
36 #define VXGE_PCI_VENDOR_ID 0x17D5
37 #define VXGE_PCI_DEVICE_ID_TITAN_1 0x5833
38 #define VXGE_PCI_REVISION_TITAN_1 1
39 #define VXGE_PCI_DEVICE_ID_TITAN_1A 0x5833
40 #define VXGE_PCI_REVISION_TITAN_1A 2
41 #define VXGE_PCI_DEVICE_ID_TITAN_2 0x5834
42 #define VXGE_PCI_REVISION_TITAN_2 1
44 #define VXGE_MIN_FW_MAJOR_VERSION 1
45 #define VXGE_MIN_FW_MINOR_VERSION 8
46 #define VXGE_MIN_FW_BUILD_NUMBER 1
48 #define VXGE_DRIVER_VENDOR "Exar Corp."
49 #define VXGE_CHIP_FAMILY "X3100"
50 #define VXGE_SUPPORTED_MEDIA_0 "Fiber"
52 #define VXGE_DRIVER_NAME \
53 "Neterion X3100 10GbE PCIe Server Adapter Driver"
55 * mBIT(loc) - set bit at offset
57 #define mBIT(loc) (0x8000000000000000ULL >> (loc))
60 * vBIT(val, loc, sz) - set bits at offset
62 #define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz)))
63 #define vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz)))
66 * bVALx(bits, loc) - Get the value of x bits at location
68 #define bVAL1(bits, loc) ((((u64)bits) >> (64-(loc+1))) & 0x1)
69 #define bVAL2(bits, loc) ((((u64)bits) >> (64-(loc+2))) & 0x3)
70 #define bVAL3(bits, loc) ((((u64)bits) >> (64-(loc+3))) & 0x7)
71 #define bVAL4(bits, loc) ((((u64)bits) >> (64-(loc+4))) & 0xF)
72 #define bVAL5(bits, loc) ((((u64)bits) >> (64-(loc+5))) & 0x1F)
73 #define bVAL6(bits, loc) ((((u64)bits) >> (64-(loc+6))) & 0x3F)
74 #define bVAL7(bits, loc) ((((u64)bits) >> (64-(loc+7))) & 0x7F)
75 #define bVAL8(bits, loc) ((((u64)bits) >> (64-(loc+8))) & 0xFF)
76 #define bVAL9(bits, loc) ((((u64)bits) >> (64-(loc+9))) & 0x1FF)
77 #define bVAL11(bits, loc) ((((u64)bits) >> (64-(loc+11))) & 0x7FF)
78 #define bVAL12(bits, loc) ((((u64)bits) >> (64-(loc+12))) & 0xFFF)
79 #define bVAL14(bits, loc) ((((u64)bits) >> (64-(loc+14))) & 0x3FFF)
80 #define bVAL15(bits, loc) ((((u64)bits) >> (64-(loc+15))) & 0x7FFF)
81 #define bVAL16(bits, loc) ((((u64)bits) >> (64-(loc+16))) & 0xFFFF)
82 #define bVAL17(bits, loc) ((((u64)bits) >> (64-(loc+17))) & 0x1FFFF)
83 #define bVAL18(bits, loc) ((((u64)bits) >> (64-(loc+18))) & 0x3FFFF)
84 #define bVAL20(bits, loc) ((((u64)bits) >> (64-(loc+20))) & 0xFFFFF)
85 #define bVAL22(bits, loc) ((((u64)bits) >> (64-(loc+22))) & 0x3FFFFF)
86 #define bVAL24(bits, loc) ((((u64)bits) >> (64-(loc+24))) & 0xFFFFFF)
87 #define bVAL28(bits, loc) ((((u64)bits) >> (64-(loc+28))) & 0xFFFFFFF)
88 #define bVAL32(bits, loc) ((((u64)bits) >> (64-(loc+32))) & 0xFFFFFFFF)
89 #define bVAL36(bits, loc) ((((u64)bits) >> (64-(loc+36))) & 0xFFFFFFFFFULL)
90 #define bVAL40(bits, loc) ((((u64)bits) >> (64-(loc+40))) & 0xFFFFFFFFFFULL)
91 #define bVAL44(bits, loc) ((((u64)bits) >> (64-(loc+44))) & 0xFFFFFFFFFFFULL)
92 #define bVAL48(bits, loc) ((((u64)bits) >> (64-(loc+48))) & 0xFFFFFFFFFFFFULL)
93 #define bVAL52(bits, loc) ((((u64)bits) >> (64-(loc+52))) & 0xFFFFFFFFFFFFFULL)
94 #define bVAL56(bits, loc) ((((u64)bits) >> (64-(loc+56))) & 0xFFFFFFFFFFFFFFULL)
95 #define bVAL60(bits, loc) \
96 ((((u64)bits) >> (64-(loc+60))) & 0xFFFFFFFFFFFFFFFULL)
97 #define bVAL61(bits, loc) \
98 ((((u64)bits) >> (64-(loc+61))) & 0x1FFFFFFFFFFFFFFFULL)
100 #define VXGE_HAL_VPATH_BMAP_START 47
101 #define VXGE_HAL_VPATH_BMAP_END 63
103 #define VXGE_HAL_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL
105 #define VXGE_HAL_INTR_MASK_ALL 0xFFFFFFFFFFFFFFFFULL
107 #define VXGE_HAL_MAX_VIRTUAL_PATHS 17
109 #define VXGE_HAL_MAX_FUNCTIONS 8
111 #define VXGE_HAL_MAX_ITABLE_ENTRIES 256
113 #define VXGE_HAL_MAX_RSS_KEY_SIZE 40
115 #define VXGE_HAL_MAC_MAX_WIRE_PORTS 2
117 #define VXGE_HAL_MAC_SWITCH_PORT 2
119 #define VXGE_HAL_MAC_MAX_AGGR_PORTS 2
121 #define VXGE_HAL_MAC_MAX_PORTS 3
123 #define VXGE_HAL_INTR_ALARM (1<<4)
125 #define VXGE_HAL_INTR_TX (1<<(3-VXGE_HAL_VPATH_INTR_TX))
127 #define VXGE_HAL_INTR_RX (1<<(3-VXGE_HAL_VPATH_INTR_RX))
129 #define VXGE_HAL_INTR_EINTA (1<<(3-VXGE_HAL_VPATH_INTR_EINTA))
131 #define VXGE_HAL_INTR_BMAP (1<<(3-VXGE_HAL_VPATH_INTR_BMAP))
133 #define VXGE_HAL_PCI_CONFIG_SPACE_SIZE VXGE_OS_PCI_CONFIG_SIZE
135 #define VXGE_HAL_DEFAULT_32 0xffffffff
137 #define VXGE_HAL_DEFAULT_64 0xffffffffffffffff
139 #define VXGE_HAL_DUMP_BUF_SIZE 0x10000
141 #define VXGE_HAL_VPD_BUFFER_SIZE 128
143 #define VXGE_HAL_VPD_LENGTH 80
145 /* Check whether an address is multicast. */
146 #define VXGE_HAL_IS_NULL(Address) (Address == 0x0000000000000000ULL)
148 /* Check whether an address is multicast. */
149 #define VXGE_HAL_IS_MULTICAST(Address) (Address & 0x0000010000000000ULL)
151 /* Check whether an address is broadcast. */
152 #define VXGE_HAL_IS_BROADCAST(Address) \
153 ((Address & 0x0000FFFF00000000ULL) == 0x0000FFFF00000000ULL)
155 #define VXGE_HAL_IS_UNICAST(Address) \
156 (!(VXGE_HAL_IS_NULL(Address) || \
157 VXGE_HAL_IS_MULTICAST(Address) || \
158 VXGE_HAL_IS_BROADCAST(Address)))
161 #define VXGE_HAL_HEADER_ETHERNET_II_802_3_SIZE 14
162 #define VXGE_HAL_HEADER_802_2_SIZE 3
163 #define VXGE_HAL_HEADER_SNAP_SIZE 5
164 #define VXGE_HAL_HEADER_VLAN_SIZE 4
165 #define VXGE_HAL_MAC_HEADER_MAX_SIZE \
166 (VXGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + \
167 VXGE_HAL_HEADER_802_2_SIZE + \
168 VXGE_HAL_HEADER_SNAP_SIZE)
170 #define VXGE_HAL_TCPIP_HEADER_MAX_SIZE (64 + 64)
172 /* 32bit alignments */
174 /* A receive data corruption can occur resulting in either a single-bit or
175 double-bit ECC error being flagged in the ASIC if starting offset of a
176 buffer in single buffer mode is 0x2 to 0xa. Single bit ECC error will not
177 lock up the card but can hide the data corruption while the double-bit ECC
178 error will lock up the card. Limiting the starting offset of the buffers to
179 0x0, 0x1 or to a value greater than 0xF will workaround this issue.
180 VXGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN of 2 causes the starting offset of
181 buffer to be 0x2, 0x12 and so on, to have the start of the ip header dword
182 aligned. The start of buffer of 0x2 will cause this problem to occur.
183 To avoid this problem in all cases, add 0x10 to 0x2, to ensure that the start
184 of buffer is outside of the problem causing offsets.
187 #define VXGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN 0x12
188 #define VXGE_HAL_HEADER_802_2_SNAP_ALIGN 2
189 #define VXGE_HAL_HEADER_802_2_ALIGN 3
190 #define VXGE_HAL_HEADER_SNAP_ALIGN 1
192 #define VXGE_HAL_MIN_MTU 46
193 #define VXGE_HAL_MAX_MTU 9600
194 #define VXGE_HAL_DEFAULT_MTU 1500
196 #define VXGE_HAL_SEGEMENT_OFFLOAD_MAX_SIZE 81920
198 #if defined(__EXTERN_BEGIN_DECLS)
199 #undef __EXTERN_BEGIN_DECLS
202 #if defined(__EXTERN_END_DECLS)
203 #undef __EXTERN_END_DECLS
206 #if defined(__cplusplus)
207 #define __EXTERN_BEGIN_DECLS extern "C" {
208 #define __EXTERN_END_DECLS }
210 #define __EXTERN_BEGIN_DECLS
211 #define __EXTERN_END_DECLS
216 /* --------------------------- common stuffs ------------------------------ */
218 * VXGE_OS_DMA_REQUIRES_SYNC - should be defined or
219 * NOT defined in the Makefile
221 #define VXGE_OS_DMA_CACHELINE_ALIGNED 0x1
224 * Either STREAMING or CONSISTENT should be used.
225 * The combination of both or none is invalid
227 #define VXGE_OS_DMA_STREAMING 0x2
228 #define VXGE_OS_DMA_CONSISTENT 0x4
229 #define VXGE_OS_SPRINTF_STRLEN 64
231 /* --------------------------- common stuffs ------------------------------ */
232 #ifndef VXGE_OS_LLXFMT
233 #define VXGE_OS_LLXFMT "%llx"
236 #ifndef VXGE_OS_LLDFMT
237 #define VXGE_OS_LLDFMT "%lld"
240 #ifndef VXGE_OS_STXFMT
241 #define VXGE_OS_STXFMT "%zx"
244 #ifndef VXGE_OS_STDFMT
245 #define VXGE_OS_STDFMT "%zd"
251 #endif /* VXGE_DEFS_H */