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33 #ifndef VXGE_HAL_MGMT_H
34 #define VXGE_HAL_MGMT_H
39 * struct vxge_hal_mgmt_about_info_t - About info.
40 * @vendor: PCI Vendor ID.
41 * @device: PCI Device ID.
42 * @subsys_vendor: PCI Subsystem Vendor ID.
43 * @subsys_device: PCI Subsystem Device ID.
44 * @board_rev: PCI Board revision, e.g. 3 - for Xena 3.
45 * @vendor_name: Exar Corp.
47 * @media: Fiber, copper.
48 * @hal_major: HAL major version number.
49 * @hal_minor: HAL minor version number.
50 * @hal_fix: HAL fix number.
51 * @hal_build: HAL build number.
52 * @ll_major: Link-layer ULD major version number.
53 * @ll_minor: Link-layer ULD minor version number.
54 * @ll_fix: Link-layer ULD fix version number.
55 * @ll_build: Link-layer ULD build number.
57 typedef struct vxge_hal_mgmt_about_info_t {
74 } vxge_hal_mgmt_about_info_t;
78 * vxge_hal_mgmt_about - Retrieve about info.
79 * @devh: HAL device handle.
80 * @about_info: Filled in by HAL. See vxge_hal_mgmt_about_info_t {}.
81 * @size: Pointer to buffer containing the Size of the @buffer_info.
82 * HAL will return an error if the size is smaller than
83 * sizeof(vxge_hal_mgmt_about_info_t) and returns required size in this field
85 * Retrieve information such as PCI device and vendor IDs, board
86 * revision number, HAL version number, etc.
88 * Returns: VXGE_HAL_OK - success;
89 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
90 * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
91 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
92 * VXGE_HAL_FAIL - Failed to retrieve the information.
94 * See also: vxge_hal_mgmt_about_info_t {}.
97 vxge_hal_mgmt_about(vxge_hal_device_h devh,
98 vxge_hal_mgmt_about_info_t *about_info,
102 * vxge_hal_mgmt_pci_config - Retrieve PCI configuration.
103 * @devh: HAL device handle.
104 * @buffer: Buffer for PCI configuration space.
105 * @size: Pointer to buffer containing the Size of the @buffer.
106 * HAL will return an error if the size is smaller than
107 * sizeof(vxge_hal_pci_config_t) and returns required size in this field
109 * Get PCI configuration. Permits to retrieve at run-time configuration
110 * values that were used to configure the device at load-time.
112 * Returns: VXGE_HAL_OK - success.
113 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
114 * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
115 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
119 vxge_hal_mgmt_pci_config(vxge_hal_device_h devh, u8 *buffer, u32 *size);
122 * struct vxge_hal_mgmt_pm_cap_t - Power Management Capabilities
123 * @pm_cap_ver: Version
124 * @pm_cap_pme_clock: PME clock required
125 * @pm_cap_aux_power: Auxilliary power support
126 * @pm_cap_dsi: Device specific initialization
127 * @pm_cap_aux_current: auxiliary current requirements
128 * @pm_cap_cap_d0: D1 power state support
129 * @pm_cap_cap_d1: D2 power state support
130 * @pm_cap_pme_d0: PME# can be asserted from D3hot
131 * @pm_cap_pme_d1: PME# can be asserted from D3hot
132 * @pm_cap_pme_d2: PME# can be asserted from D3hot
133 * @pm_cap_pme_d3_hot: PME# can be asserted from D3hot
134 * @pm_cap_pme_d3_cold: PME# can be asserted from D3cold
135 * @pm_ctrl_state: Current power state (D0 to D3)
136 * @pm_ctrl_no_soft_reset: Devices transitioning from D3hot to D0
137 * @pm_ctrl_pme_enable: PME pin enable
138 * @pm_ctrl_pme_data_sel: Data select
139 * @pm_ctrl_pme_data_scale: Data scale
140 * @pm_ctrl_pme_status: PME pin status
141 * @pm_ppb_ext_b2_b3: Stop clock when in D3hot
142 * @pm_ppb_ext_ecc_en: Bus power/clock control enable
143 * @pm_data_reg: state dependent data requested by pm_ctrl_pme_data_sel
145 * Power Management Capabilities structure
147 typedef struct vxge_hal_mgmt_pm_cap_t {
149 u32 pm_cap_pme_clock;
150 u32 pm_cap_aux_power;
152 u32 pm_cap_aux_current;
158 u32 pm_cap_pme_d3_hot;
159 u32 pm_cap_pme_d3_cold;
161 u32 pm_ctrl_no_soft_reset;
162 u32 pm_ctrl_pme_enable;
163 u32 pm_ctrl_pme_data_sel;
164 u32 pm_ctrl_pme_data_scale;
165 u32 pm_ctrl_pme_status;
166 u32 pm_ppb_ext_b2_b3;
167 u32 pm_ppb_ext_ecc_en;
169 } vxge_hal_mgmt_pm_cap_t;
172 * vxge_hal_mgmt_pm_capabilities_get - Returns the pm capabilities
173 * @devh: HAL device handle.
174 * @pm_cap: Power Management Capabilities
176 * Return the pm capabilities
179 vxge_hal_mgmt_pm_capabilities_get(vxge_hal_device_h devh,
180 vxge_hal_mgmt_pm_cap_t *pm_cap);
183 * struct vxge_hal_mgmt_sid_cap_t - Slot ID Capabilities
184 * @sid_number_of_slots: Number of solts
185 * @sid_first_in_chasis: First in chasis flag
186 * @sid_chasis_number: Chasis Number
188 * Slot ID Capabilities structure
190 typedef struct vxge_hal_mgmt_sid_cap_t {
191 u32 sid_number_of_slots;
192 u32 sid_first_in_chasis;
193 u32 sid_chasis_number;
194 } vxge_hal_mgmt_sid_cap_t;
197 * vxge_hal_mgmt_sid_capabilities_get - Returns the sid capabilities
198 * @devh: HAL device handle.
199 * @sid_cap: Slot Id Capabilities
201 * Return the pm capabilities
204 vxge_hal_mgmt_sid_capabilities_get(vxge_hal_device_h devh,
205 vxge_hal_mgmt_sid_cap_t *sid_cap);
208 * struct vxge_hal_mgmt_msi_cap_t - MSI Capabilities
209 * @enable: 1 - MSI enabled, 0 - MSI not enabled
210 * @is_pvm_capable: 1 - PVM capable, 0 - Not PVM Capable (valid for get only)
211 * @is_64bit_addr_capable: 1 - 64 bit address capable, 0 - 32 bit address only
212 * (valid for get only)
213 * @vectors_allocated: Number of vectors allocated
220 * @max_vectors_capable: Maximum number of vectors that can be allocated
221 * (valid for get only)
228 * @address: MSI address
230 * @mask_bits: For each Mask bit that is set, the function is prohibited from
231 * sending the associated message
232 * @pending_bits: For each Pending bit that is set, the function has a
233 * pending associated message.
235 * MSI Capabilities structure
237 typedef struct vxge_hal_mgmt_msi_cap_t {
240 u32 is_64bit_addr_capable;
241 u32 vectors_allocated;
242 u32 max_vectors_capable;
243 #define VXGE_HAL_MGMT_MSI_CAP_VECTORS_1 0
244 #define VXGE_HAL_MGMT_MSI_CAP_VECTORS_2 1
245 #define VXGE_HAL_MGMT_MSI_CAP_VECTORS_4 2
246 #define VXGE_HAL_MGMT_MSI_CAP_VECTORS_8 3
247 #define VXGE_HAL_MGMT_MSI_CAP_VECTORS_16 4
248 #define VXGE_HAL_MGMT_MSI_CAP_VECTORS_32 5
253 } vxge_hal_mgmt_msi_cap_t;
256 * vxge_hal_mgmt_msi_capabilities_get - Returns the msi capabilities
257 * @devh: HAL device handle.
258 * @msi_cap: MSI Capabilities
260 * Return the msi capabilities
263 vxge_hal_mgmt_msi_capabilities_get(vxge_hal_device_h devh,
264 vxge_hal_mgmt_msi_cap_t *msi_cap);
267 * vxge_hal_mgmt_msi_capabilities_set - Sets the msi capabilities
268 * @devh: HAL device handle.
269 * @msi_cap: MSI Capabilities
271 * Sets the msi capabilities
274 vxge_hal_mgmt_msi_capabilities_set(vxge_hal_device_h devh,
275 vxge_hal_mgmt_msi_cap_t *msi_cap);
278 * struct vxge_hal_mgmt_msix_cap_t - MSIX Capabilities
279 * @enable: 1 - MSIX enabled, 0 - MSIX not enabled
280 * @mask_all_vect: 1 - Mask all vectors, 0 - Do not mask all vectors
281 * @table_size: MSIX Table Size-1
282 * @table_offset: Offset of the table from the table_bir
283 * @table_bir: Table Bar address register number 0-BAR0, 2-BAR1, 4-BAR2
284 * @pba_offset: Offset of the PBA from the pba_bir
285 * @pba_bir: PBA Bar address register number 0-BAR0, 2-BAR1, 4-BAR2
287 * MSIS Capabilities structure
289 typedef struct vxge_hal_mgmt_msix_cap_t {
295 #define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR0 0
296 #define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR1 2
297 #define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR2 4
300 #define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR0 0
301 #define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR1 2
302 #define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR2 4
303 } vxge_hal_mgmt_msix_cap_t;
306 * vxge_hal_mgmt_msix_capabilities_get - Returns the msix capabilities
307 * @devh: HAL device handle.
308 * @msix_cap: MSIX Capabilities
310 * Return the msix capabilities
313 vxge_hal_mgmt_msix_capabilities_get(vxge_hal_device_h devh,
314 vxge_hal_mgmt_msix_cap_t *msix_cap);
317 * struct vxge_hal_pci_err_cap_t - PCI Error Capabilities
318 * @pci_err_header: Error header
319 * @pci_err_uncor_status: Uncorrectable error status
320 * 0x00000001 - Training
321 * 0x00000010 - Data Link Protocol
322 * 0x00001000 - Poisoned TLP
323 * 0x00002000 - Flow Control Protocol
324 * 0x00004000 - Completion Timeout
325 * 0x00008000 - Completer Abort
326 * 0x00010000 - Unexpected Completion
327 * 0x00020000 - Receiver Overflow
328 * 0x00040000 - Malformed TLP
329 * 0x00080000 - ECRC Error Status
330 * 0x00100000 - Unsupported Request
331 * @pci_err_uncor_mask: Uncorrectable mask
332 * @pci_err_uncor_server: Uncorrectable server
333 * @pci_err_cor_status: Correctable status
334 * 0x00000001 - Receiver Error Status
335 * 0x00000040 - Bad TLP Status
336 * 0x00000080 - Bad DLLP Status
337 * 0x00000100 - REPLAY_NUM Rollover
338 * 0x00001000 - Replay Timer Timeout
339 * VXGE_HAL_PCI_ERR_COR_MASK 20
340 * @pci_err_cap: Error capability
341 * 0x00000020 - ECRC Generation Capable
342 * 0x00000040 - ECRC Generation Enable
343 * 0x00000080 - ECRC Check Capable
344 * 0x00000100 - ECRC Check Enable
345 * @err_header_log: Error header log
347 * @pci_err_root_command: Error root command
348 * @pci_err_root_status: Error root status
349 * @pci_err_root_cor_src: Error root correctible source
350 * @pci_err_root_src: Error root source
352 * MSIS Capabilities structure
354 typedef struct vxge_hal_pci_err_cap_t {
356 u32 pci_err_uncor_status;
357 #define VXGE_HAL_PCI_ERR_CAP_UNC_TRAIN 0x00000001 /* Training */
358 #define VXGE_HAL_PCI_ERR_CAP_UNC_DLP 0x00000010 /* Data Link Protocol */
359 #define VXGE_HAL_PCI_ERR_CAP_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
360 #define VXGE_HAL_PCI_ERR_CAP_UNC_FCP 0x00002000 /* Flow Ctrl Protocol */
361 #define VXGE_HAL_PCI_ERR_CAP_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
362 #define VXGE_HAL_PCI_ERR_CAP_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
363 #define VXGE_HAL_PCI_ERR_CAP_UNC_UNX_COMP 0x00010000 /* Unexpected Compl */
364 #define VXGE_HAL_PCI_ERR_CAP_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
365 #define VXGE_HAL_PCI_ERR_CAP_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
366 #define VXGE_HAL_PCI_ERR_CAP_UNC_ECRC 0x00080000 /* ECRC Error Status */
367 #define VXGE_HAL_PCI_ERR_CAP_UNC_UNSUP 0x00100000 /* Unsupported Request */
368 u32 pci_err_uncor_mask;
369 u32 pci_err_uncor_server;
370 u32 pci_err_cor_status;
371 #define VXGE_HAL_PCI_ERR_CAP_COR_RCVR 0x00000001 /* Recv Err Status */
372 #define VXGE_HAL_PCI_ERR_CAP_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
373 #define VXGE_HAL_PCI_ERR_CAP_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
374 #define VXGE_HAL_PCI_ERR_CAP_COR_REP_ROLL 0x00000100 /* REPLAY Rollover */
375 #define VXGE_HAL_PCI_ERR_CAP_COR_REP_TIMER 0x00001000 /* Replay Timeout */
376 #define VXGE_HAL_PCI_ERR_CAP_COR_MASK 20 /* Corrble Err Mask */
378 #define VXGE_HAL_PCI_ERR_CAP_CAP_FEP(x) ((x) & 31) /* First Err Ptr */
379 #define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_GENC 0x00000020 /* ECRC Gen Capable */
380 #define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_GENE 0x00000040 /* ECRC Gen Enable */
381 #define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_CHKC 0x00000080 /* ECRC Chk Capable */
382 #define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_CHKE 0x00000100 /* ECRC Chk Enable */
384 #define VXGE_HAL_PCI_ERR_CAP_HEADER_LOG(x) ((x) >> 31) /* Error Hdr Log */
386 u32 pci_err_root_command;
387 u32 pci_err_root_status;
388 u32 pci_err_root_cor_src;
389 u32 pci_err_root_src;
390 } vxge_hal_pci_err_cap_t;
393 * vxge_hal_mgmt_pci_err_capabilities_get - Returns the pci error capabilities
394 * @devh: HAL device handle.
395 * @err_cap: PCI-E Extended Error Capabilities
397 * Return the PCI-E Extended Error capabilities
400 vxge_hal_mgmt_pci_err_capabilities_get(vxge_hal_device_h devh,
401 vxge_hal_pci_err_cap_t *err_cap);
404 * vxge_hal_mgmt_driver_config - Retrieve driver configuration.
405 * @drv_config: Device configuration, see vxge_hal_driver_config_t {}.
406 * @size: Pointer to buffer containing the Size of the @drv_config.
407 * HAL will return an error if the size is smaller than
408 * sizeof(vxge_hal_driver_config_t) and returns required size in this field
410 * Get driver configuration. Permits to retrieve at run-time configuration
411 * values that were used to configure the device at load-time.
413 * Returns: VXGE_HAL_OK - success.
414 * VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED - HAL is not initialized.
415 * VXGE_HAL_ERR_VERSION_CONFLICT - Version is not maching.
416 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
418 * See also: vxge_hal_driver_config_t {}, vxge_hal_mgmt_device_config().
421 vxge_hal_mgmt_driver_config(vxge_hal_driver_config_t *drv_config, u32 *size);
423 #if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
426 * vxge_hal_mgmt_trace_read - Read trace buffer contents.
427 * @buffer: Buffer to store the trace buffer contents.
428 * @buf_size: Size of the buffer.
429 * @offset: Offset in the internal trace buffer to read data.
430 * @read_length: Size of the valid data in the buffer.
432 * Read HAL trace buffer contents starting from the offset
433 * upto the size of the buffer or till EOF is reached.
435 * Returns: VXGE_HAL_OK - success.
436 * VXGE_HAL_EOF_TRACE_BUF - No more data in the trace buffer.
440 vxge_hal_mgmt_trace_read(char *buffer,
443 unsigned *read_length);
448 * vxge_hal_mgmt_device_config - Retrieve device configuration.
449 * @devh: HAL device handle.
450 * @dev_config: Device configuration, see vxge_hal_device_config_t {}.
451 * @size: Pointer to buffer containing the Size of the @dev_config.
452 * HAL will return an error if the size is smaller than
453 * sizeof(vxge_hal_device_config_t) and returns required size in this field
455 * Get device configuration. Permits to retrieve at run-time configuration
456 * values that were used to initialize and configure the device.
458 * Returns: VXGE_HAL_OK - success.
459 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
460 * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
461 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
463 * See also: vxge_hal_device_config_t {}, vxge_hal_mgmt_driver_config().
466 vxge_hal_mgmt_device_config(vxge_hal_device_h devh,
467 vxge_hal_device_config_t *dev_config, u32 *size);
471 * vxge_hal_mgmt_pcireg_read - Read PCI configuration at a specified
473 * @devh: HAL device handle.
474 * @offset: Offset in the 256 byte PCI configuration space.
475 * @value_bits: 8, 16, or 32 (bits) to read.
476 * @value: Value returned by HAL.
478 * Read PCI configuration, given device and offset in the PCI space.
480 * Returns: VXGE_HAL_OK - success.
481 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
482 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
484 * VXGE_HAL_ERR_INVALID_VALUE_BIT_SIZE - Invalid bits size. Valid
489 vxge_hal_mgmt_pcireg_read(vxge_hal_device_h devh, unsigned int offset,
490 int value_bits, u32 *value);
493 * enum vxge_hal_mgmt_reg_type_e - Register types.
495 * @vxge_hal_mgmt_reg_type_legacy: Legacy registers
496 * @vxge_hal_mgmt_reg_type_toc: TOC Registers
497 * @vxge_hal_mgmt_reg_type_common: Common Registers
498 * @vxge_hal_mgmt_reg_type_memrepair: Memrepair Registers
499 * @vxge_hal_mgmt_reg_type_pcicfgmgmt: pci cfg management registers
500 * @vxge_hal_mgmt_reg_type_mrpcim: mrpcim registers
501 * @vxge_hal_mgmt_reg_type_srpcim: srpcim registers
502 * @vxge_hal_mgmt_reg_type_vpmgmt: vpath management registers
503 * @vxge_hal_mgmt_reg_type_vpath: vpath registers
505 * Register type enumaration
507 typedef enum vxge_hal_mgmt_reg_type_e {
508 vxge_hal_mgmt_reg_type_legacy = 0,
509 vxge_hal_mgmt_reg_type_toc = 1,
510 vxge_hal_mgmt_reg_type_common = 2,
511 vxge_hal_mgmt_reg_type_memrepair = 3,
512 vxge_hal_mgmt_reg_type_pcicfgmgmt = 4,
513 vxge_hal_mgmt_reg_type_mrpcim = 5,
514 vxge_hal_mgmt_reg_type_srpcim = 6,
515 vxge_hal_mgmt_reg_type_vpmgmt = 7,
516 vxge_hal_mgmt_reg_type_vpath = 8
517 } vxge_hal_mgmt_reg_type_e;
520 * vxge_hal_mgmt_reg_read - Read X3100 register.
521 * @devh: HAL device handle.
522 * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
523 * @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
525 * @offset: Register offset in the register space qualified by the type and
527 * @value: Register value. Returned by HAL.
528 * Read X3100 register.
530 * Returns: VXGE_HAL_OK - success.
531 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
532 * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
533 * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
534 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
538 vxge_hal_mgmt_reg_read(vxge_hal_device_h devh,
539 vxge_hal_mgmt_reg_type_e type,
545 * vxge_hal_mgmt_reg_Write - Write X3100 register.
546 * @devh: HAL device handle.
547 * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
548 * @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
550 * @offset: Register offset in the register space qualified by the type and
552 * @value: Register value to be written.
553 * Write X3100 register.
555 * Returns: VXGE_HAL_OK - success.
556 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
557 * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
558 * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
559 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
563 vxge_hal_mgmt_reg_write(vxge_hal_device_h devh,
564 vxge_hal_mgmt_reg_type_e type,
570 * vxge_hal_mgmt_bar0_read - Read X3100 register located at the offset
572 * @devh: HAL device handle.
573 * @offset: Register offset from bar0
574 * @value: Register value. Returned by HAL.
575 * Read X3100 register.
577 * Returns: VXGE_HAL_OK - success.
578 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
579 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
583 vxge_hal_mgmt_bar0_read(vxge_hal_device_h devh,
588 * vxge_hal_mgmt_bar1_read - Read X3100 register located at the offset
590 * @devh: HAL device handle.
591 * @offset: Register offset from bar1
592 * @value: Register value. Returned by HAL.
593 * Read X3100 register.
595 * Returns: VXGE_HAL_OK - success.
596 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
597 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
601 vxge_hal_mgmt_bar1_read(vxge_hal_device_h devh,
606 * vxge_hal_mgmt_bar0_Write - Write X3100 register located at the offset
608 * @devh: HAL device handle.
609 * @offset: Register offset from bar0
610 * @value: Register value to be written.
611 * Write X3100 register.
613 * Returns: VXGE_HAL_OK - success.
614 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
615 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
619 vxge_hal_mgmt_bar0_write(vxge_hal_device_h devh,
624 * vxge_hal_mgmt_register_config - Retrieve register configuration.
625 * @devh: HAL device handle.
626 * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
627 * @Index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
629 * @config: Device configuration, see vxge_hal_device_config_t {}.
630 * @size: Pointer to buffer containing the Size of the @reg_config.
631 * HAL will return an error if the size is smaller than
632 * requested register space and returns required size in this field
634 * Get register configuration. Permits to retrieve register values.
636 * Returns: VXGE_HAL_OK - success.
637 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
638 * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
639 * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
640 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
644 vxge_hal_mgmt_register_config(vxge_hal_device_h devh,
645 vxge_hal_mgmt_reg_type_e type,
651 * vxge_hal_mgmt_read_xfp_current_temp - Read current temparature of given port
652 * @devh: HAL device handle.
655 * This routine only gets the temperature for XFP modules. Also, updating of the
656 * NVRAM can sometimes fail and so the reading we might get may not be uptodate.
658 u32 vxge_hal_mgmt_read_xfp_current_temp(vxge_hal_device_h devh, u32 port);
661 * vxge_hal_mgmt_pma_loopback - Enable or disable PMA loopback
662 * @devh: HAL device handle.
664 * @enable:Boolean set to 1 to enable and 0 to disable.
666 * Enable or disable PMA loopback.
671 vxge_hal_mgmt_pma_loopback(vxge_hal_device_h devh, u32 port, u32 enable);
674 * vxge_hal_mgmt_xgmii_loopback - Enable or disable xgmii loopback
675 * @devh: HAL device handle.
677 * @enable:Boolean set to 1 to enable and 0 to disable.
679 * Enable or disable xgmii loopback.
684 vxge_hal_mgmt_xgmii_loopback(vxge_hal_device_h devh, u32 port, u32 enable);
688 #endif /* VXGE_HAL_MGMT_H */