2 * Copyright(c) 2002-2011 Exar Corp.
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9 * this list of conditions and the following disclaimer.
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29 * POSSIBILITY OF SUCH DAMAGE.
33 #ifndef VXGE_HAL_REGS_H
34 #define VXGE_HAL_REGS_H
39 /* Using this strcture to calculate offsets */
40 typedef struct vxge_hal_pci_config_le_t {
41 u16 vendor_id; /* 0x00 */
42 u16 device_id; /* 0x02 */
44 u16 command; /* 0x04 */
45 u16 status; /* 0x06 */
47 u8 revision; /* 0x08 */
48 u8 pciClass[3]; /* 0x09 */
50 u8 cache_line_size; /* 0x0c */
51 u8 latency_timer; /* 0x0d */
52 u8 header_type; /* 0x0e */
55 u32 base_addr0_lo; /* 0x10 */
56 u32 base_addr0_hi; /* 0x14 */
58 u32 base_addr1_lo; /* 0x18 */
59 u32 base_addr1_hi; /* 0x1C */
61 u32 base_addr2_lo; /* 0x20 */
62 u32 base_addr2_hi; /* 0x24 */
64 u32 cardbus_cis_pointer; /* 0x28 */
66 u16 subsystem_vendor_id; /* 0x2c */
67 u16 subsystem_id; /* 0x2e */
69 u32 rom_base; /* 0x30 */
70 u8 capabilities_pointer; /* 0x34 */
71 u8 rsvd_35[3]; /* 0x35 */
72 u32 rsvd_38; /* 0x38 */
74 u8 interrupt_line; /* 0x3c */
75 u8 interrupt_pin; /* 0x3d */
76 u8 min_grant; /* 0x3e */
77 u8 max_latency; /* 0x3f */
79 u8 rsvd_b1[VXGE_HAL_PCI_CONFIG_SPACE_SIZE - 0x40];
80 } vxge_hal_pci_config_le_t; /* 0x100 */
82 typedef struct vxge_hal_pci_config_t {
83 #if defined(VXGE_OS_HOST_BIG_ENDIAN)
84 u16 device_id; /* 0x02 */
85 u16 vendor_id; /* 0x00 */
87 u16 status; /* 0x06 */
88 u16 command; /* 0x04 */
90 u8 pciClass[3]; /* 0x09 */
91 u8 revision; /* 0x08 */
94 u8 header_type; /* 0x0e */
95 u8 latency_timer; /* 0x0d */
96 u8 cache_line_size; /* 0x0c */
98 u32 base_addr0_lo; /* 0x10 */
99 u32 base_addr0_hi; /* 0x14 */
101 u32 base_addr1_lo; /* 0x18 */
102 u32 base_addr1_hi; /* 0x1C */
104 u32 not_Implemented1; /* 0x20 */
105 u32 not_Implemented2; /* 0x24 */
107 u32 cardbus_cis_pointer; /* 0x28 */
109 u16 subsystem_id; /* 0x2e */
110 u16 subsystem_vendor_id; /* 0x2c */
112 u32 rom_base; /* 0x30 */
113 u8 rsvd_35[3]; /* 0x35 */
114 u8 capabilities_pointer; /* 0x34 */
115 u32 rsvd_38; /* 0x38 */
117 u8 max_latency; /* 0x3f */
118 u8 min_grant; /* 0x3e */
119 u8 interrupt_pin; /* 0x3d */
120 u8 interrupt_line; /* 0x3c */
122 u16 vendor_id; /* 0x00 */
123 u16 device_id; /* 0x02 */
125 u16 command; /* 0x04 */
126 u16 status; /* 0x06 */
128 u8 revision; /* 0x08 */
129 u8 pciClass[3]; /* 0x09 */
131 u8 cache_line_size; /* 0x0c */
132 u8 latency_timer; /* 0x0d */
133 u8 header_type; /* 0x0e */
136 u32 base_addr0_lo; /* 0x10 */
137 u32 base_addr0_hi; /* 0x14 */
139 u32 base_addr1_lo; /* 0x18 */
140 u32 base_addr1_hi; /* 0x1C */
142 u32 not_Implemented1; /* 0x20 */
143 u32 not_Implemented2; /* 0x24 */
145 u32 cardbus_cis_pointer; /* 0x28 */
147 u16 subsystem_vendor_id; /* 0x2c */
148 u16 subsystem_id; /* 0x2e */
150 u32 rom_base; /* 0x30 */
151 u8 capabilities_pointer; /* 0x34 */
152 u8 rsvd_35[3]; /* 0x35 */
153 u32 rsvd_38; /* 0x38 */
155 u8 interrupt_line; /* 0x3c */
156 u8 interrupt_pin; /* 0x3d */
157 u8 min_grant; /* 0x3e */
158 u8 max_latency; /* 0x3f */
161 u8 rsvd_b1[VXGE_HAL_PCI_CONFIG_SPACE_SIZE - 0x40];
162 } vxge_hal_pci_config_t; /* 0x100 */
164 #define VXGE_HAL_EEPROM_SIZE (0x01 << 11)
166 #if defined(VXGE_OS_HOST_BIG_ENDIAN)
167 #define VXGE_HAL_PCI_CAP_ID(ptr) *((ptr) + 3)
168 #define VXGE_HAL_PCI_CAP_NEXT(ptr) *((ptr) + 2)
170 #define VXGE_HAL_PCI_CAP_ID(ptr) *(ptr)
171 #define VXGE_HAL_PCI_CAP_NEXT(ptr) *((ptr) + 1)
174 /* Capability lists */
176 #define VXGE_HAL_PCI_CAP_LIST_ID 0 /* Capability ID */
177 #define VXGE_HAL_PCI_CAP_ID_PM 0x01 /* Power Management */
178 #define VXGE_HAL_PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
179 #define VXGE_HAL_PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
180 #define VXGE_HAL_PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
181 #define VXGE_HAL_PCI_CAP_ID_MSI 0x05 /* Message Signalled Intr */
182 #define VXGE_HAL_PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
183 #define VXGE_HAL_PCI_CAP_ID_PCIX 0x07 /* PCIX */
184 #define VXGE_HAL_PCI_CAP_ID_HT 0x08 /* Hypertransport */
185 #define VXGE_HAL_PCI_CAP_ID_VS 0x09 /* Vendor Specific */
186 #define VXGE_HAL_PCI_CAP_ID_DBGPORT 0x0A /* Debug Port */
187 #define VXGE_HAL_PCI_CAP_ID_CPCICSR 0x0B /* CompPCI central res ctrl */
188 #define VXGE_HAL_PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Ctrl */
189 #define VXGE_HAL_PCI_CAP_ID_PCIBSVID 0x0D /* PCI Bridge Subsys Vendr Id */
190 #define VXGE_HAL_PCI_CAP_ID_AGP8X 0x0E /* AGP 8x */
191 #define VXGE_HAL_PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
192 #define VXGE_HAL_PCI_CAP_ID_PCIE 0x10 /* PCI Express */
193 #define VXGE_HAL_PCI_CAP_ID_MSIX 0x11 /* MSI-X */
194 #define VXGE_HAL_PCI_CAP_LIST_NEXT 1 /* Next cap in the list */
195 #define VXGE_HAL_PCI_CAP_FLAGS 2 /* Cap defined flags(16 bits) */
197 typedef struct vxge_hal_pm_capability_le_t {
199 u8 next_capability_ptr;
200 u16 capabilities_reg;
201 #define VXGE_HAL_PCI_PM_CAP_VER_MASK 0x0007 /* Version */
202 #define VXGE_HAL_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
203 #define VXGE_HAL_PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
204 #define VXGE_HAL_PCI_PM_CAP_DSI 0x0020 /* Device specific init */
205 #define VXGE_HAL_PCI_PM_AUX_CURRENT 0x01C0 /* Auxiliary current reqs */
206 #define VXGE_HAL_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
207 #define VXGE_HAL_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
208 #define VXGE_HAL_PCI_PM_CAP_PME_D0 0x0800 /* PME# assertable from D0 */
209 #define VXGE_HAL_PCI_PM_CAP_PME_D1 0x1000 /* PME# assertable from D1 */
210 #define VXGE_HAL_PCI_PM_CAP_PME_D2 0x2000 /* PME# assertable from D2 */
211 #define VXGE_HAL_PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME# assertable from D3hot */
212 #define VXGE_HAL_PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME# assertable from D3cold */
214 #define VXGE_HAL_PCI_PM_CTRL_STATE_MASK 0x0003 /* Curr power state(D0 to D3) */
215 #define VXGE_HAL_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* trans from D3hot to D0 */
216 #define VXGE_HAL_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
217 #define VXGE_HAL_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
218 #define VXGE_HAL_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
219 #define VXGE_HAL_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
221 #define VXGE_HAL_PCI_PM_PPB_B2_B3 0x40 /* Stop clk when in D3hot(??) */
222 #define VXGE_HAL_PCI_PM_BPCC_ENABLE 0x80 /* Bus pwr/clk ctrl enable(??) */
224 } vxge_hal_pm_capability_le_t;
226 typedef struct vxge_hal_pm_capability_t {
227 #if defined(VXGE_OS_HOST_BIG_ENDIAN)
228 u16 capabilities_reg;
229 #define VXGE_HAL_PCI_PM_CAP_VER_MASK 0x0007 /* Version */
230 #define VXGE_HAL_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
231 #define VXGE_HAL_PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
232 #define VXGE_HAL_PCI_PM_CAP_DSI 0x0020 /* Dev specific init */
233 #define VXGE_HAL_PCI_PM_AUX_CURRENT 0x01C0 /* Auxiliary current reqs */
234 #define VXGE_HAL_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
235 #define VXGE_HAL_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
236 #define VXGE_HAL_PCI_PM_CAP_PME_D0 0x0800 /* PME# assertable from D0 */
237 #define VXGE_HAL_PCI_PM_CAP_PME_D1 0x1000 /* PME# assertable from D1 */
238 #define VXGE_HAL_PCI_PM_CAP_PME_D2 0x2000 /* PME# assertable from D2 */
239 #define VXGE_HAL_PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME# assertable from D3hot */
240 #define VXGE_HAL_PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME# assertable from D3cold */
241 u8 next_capability_ptr;
245 #define VXGE_HAL_PCI_PM_PPB_B2_B3 0x40 /* Stop clk when in D3hot(??) */
246 #define VXGE_HAL_PCI_PM_BPCC_ENABLE 0x80 /* Bus pwr/clk ctrl enable(??) */
248 #define VXGE_HAL_PCI_PM_CTRL_STATE_MASK 0x0003 /* Curr pwr state (D0 to D3) */
249 #define VXGE_HAL_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* dev trans D3hot to D0 */
250 #define VXGE_HAL_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
251 #define VXGE_HAL_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
252 #define VXGE_HAL_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
253 #define VXGE_HAL_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
256 u8 next_capability_ptr;
257 u16 capabilities_reg;
258 #define VXGE_HAL_PCI_PM_CAP_VER_MASK 0x0007 /* Version */
259 #define VXGE_HAL_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
260 #define VXGE_HAL_PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
261 #define VXGE_HAL_PCI_PM_CAP_DSI 0x0020 /* Dev specific init */
262 #define VXGE_HAL_PCI_PM_AUX_CURRENT 0x01C0 /* Auxiliary curr reqs */
263 #define VXGE_HAL_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
264 #define VXGE_HAL_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
265 #define VXGE_HAL_PCI_PM_CAP_PME_D0 0x0800 /* PME# assertable from D0 */
266 #define VXGE_HAL_PCI_PM_CAP_PME_D1 0x1000 /* PME# assertable from D1 */
267 #define VXGE_HAL_PCI_PM_CAP_PME_D2 0x2000 /* PME# assertable from D2 */
268 #define VXGE_HAL_PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME# assertable from D3hot */
269 #define VXGE_HAL_PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME# assertable from D3cold */
271 #define VXGE_HAL_PCI_PM_CTRL_STATE_MASK 0x0003 /* Curr pwr state (D0 to D3) */
272 #define VXGE_HAL_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* dev trans D3hot to D0 */
273 #define VXGE_HAL_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
274 #define VXGE_HAL_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
275 #define VXGE_HAL_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
276 #define VXGE_HAL_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
278 #define VXGE_HAL_PCI_PM_PPB_B2_B3 0x40 /* Stop clk when in D3hot(??) */
279 #define VXGE_HAL_PCI_PM_BPCC_ENABLE 0x80 /* Bus pwr/clk ctrl enable(??) */
282 } vxge_hal_pm_capability_t;
284 typedef struct vxge_hal_vpid_capability_le_t {
286 u8 next_capability_ptr;
288 #define VXGE_HAL_PCI_VPID_COMPL_FALG 0x8000 /* Read Completion Flag */
290 } vxge_hal_vpid_capability_le_t;
292 typedef struct vxge_hal_vpid_capability_t {
293 #if defined(VXGE_OS_HOST_BIG_ENDIAN)
295 #define VXGE_HAL_PCI_VPID_COMPL_FALG 0x8000 /* Read Completion Flag */
296 u8 next_capability_ptr;
301 u8 next_capability_ptr;
303 #define VXGE_HAL_PCI_VPID_COMPL_FALG 0x8000 /* Read Completion Flag */
306 } vxge_hal_vpid_capability_t;
308 typedef struct vxge_hal_sid_capability_le_t {
310 u8 next_capability_ptr;
312 #define VXGE_HAL_PCI_SID_ESR_NSLOTS 0x1f /* Num of exp slots avail */
313 #define VXGE_HAL_PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
315 } vxge_hal_sid_capability_le_t;
317 typedef struct vxge_hal_sid_capability_t {
318 #if defined(VXGE_OS_HOST_BIG_ENDIAN)
321 #define VXGE_HAL_PCI_SID_ESR_NSLOTS 0x1f /* Num of exp slots avail */
322 #define VXGE_HAL_PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
323 u8 next_capability_ptr;
327 u8 next_capability_ptr;
329 #define VXGE_HAL_PCI_SID_ESR_NSLOTS 0x1f /* Num of exp slots avail */
330 #define VXGE_HAL_PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
333 } vxge_hal_sid_capability_t;
335 typedef struct vxge_hal_msi_capability_le_t {
337 u8 next_capability_ptr;
339 #define VXGE_HAL_PCI_MSI_FLAGS_PVMASK 0x0100 /* Per Vector Masking Capable */
340 #define VXGE_HAL_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
341 #define VXGE_HAL_PCI_MSI_FLAGS_QSIZE 0x0070 /* Msg queue size configured */
342 #define VXGE_HAL_PCI_MSI_FLAGS_QMASK 0x000e /* Max queue size available */
343 #define VXGE_HAL_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
372 } vxge_hal_msi_capability_le_t;
374 typedef struct vxge_hal_msi_capability_t {
375 #if defined(VXGE_OS_HOST_BIG_ENDIAN)
377 #define VXGE_HAL_PCI_MSI_FLAGS_PVMASK 0x0100 /* Per Vector Masking Capable */
378 #define VXGE_HAL_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
379 #define VXGE_HAL_PCI_MSI_FLAGS_QSIZE 0x0070 /* Msg queue size configured */
380 #define VXGE_HAL_PCI_MSI_FLAGS_QMASK 0x000e /* Max queue size available */
381 #define VXGE_HAL_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
382 u8 next_capability_ptr;
414 u8 next_capability_ptr;
416 #define VXGE_HAL_PCI_MSI_FLAGS_PVMASK 0x0100 /* Per Vector Masking Capable */
417 #define VXGE_HAL_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
418 #define VXGE_HAL_PCI_MSI_FLAGS_QSIZE 0x0070 /* Msg queue size configured */
419 #define VXGE_HAL_PCI_MSI_FLAGS_QMASK 0x000e /* Max queue size available */
420 #define VXGE_HAL_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
450 } vxge_hal_msi_capability_t;
452 typedef struct vxge_hal_chswp_capability_le_t {
454 u8 next_capability_ptr;
456 #define VXGE_HAL_PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
457 #define VXGE_HAL_PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
458 #define VXGE_HAL_PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
459 #define VXGE_HAL_PCI_CHSWP_LOO 0x08 /* LED On / Off */
460 #define VXGE_HAL_PCI_CHSWP_PI 0x30 /* Programming Interface */
461 #define VXGE_HAL_PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
462 #define VXGE_HAL_PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
463 } vxge_hal_chswp_capability_le_t;
465 typedef struct vxge_hal_chswp_capability_t {
466 #if defined(VXGE_OS_HOST_BIG_ENDIAN)
468 #define VXGE_HAL_PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
469 #define VXGE_HAL_PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
470 #define VXGE_HAL_PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
471 #define VXGE_HAL_PCI_CHSWP_LOO 0x08 /* LED On / Off */
472 #define VXGE_HAL_PCI_CHSWP_PI 0x30 /* Programming Interface */
473 #define VXGE_HAL_PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
474 #define VXGE_HAL_PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
475 u8 next_capability_ptr;
479 u8 next_capability_ptr;
481 #define VXGE_HAL_PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
482 #define VXGE_HAL_PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
483 #define VXGE_HAL_PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
484 #define VXGE_HAL_PCI_CHSWP_LOO 0x08 /* LED On / Off */
485 #define VXGE_HAL_PCI_CHSWP_PI 0x30 /* Programming Interface */
486 #define VXGE_HAL_PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
487 #define VXGE_HAL_PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
489 } vxge_hal_chswp_capability_t;
491 typedef struct vxge_hal_shpc_capability_le_t {
493 u8 next_capability_ptr;
494 } vxge_hal_shpc_capability_le_t;
496 typedef struct vxge_hal_shpc_capability_t {
497 #if defined(VXGE_OS_HOST_BIG_ENDIAN)
498 u8 next_capability_ptr;
502 u8 next_capability_ptr;
504 } vxge_hal_shpc_capability_t;
506 typedef struct vxge_hal_msix_capability_le_t {
508 u8 next_capability_ptr;
510 #define VXGE_HAL_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSIX Enable */
511 #define VXGE_HAL_PCI_MSIX_FLAGS_MASK 0x4000 /* Mask all vectors */
512 #define VXGE_HAL_PCI_MSIX_FLAGS_TSIZE 0x001f /* Table Size */
514 #define VXGE_HAL_PCI_MSIX_TABLE_OFFSET 0xFFFFFFF8 /* Table offset mask */
515 #define VXGE_HAL_PCI_MSIX_TABLE_BIR 0x00000007 /* Table BIR mask */
517 #define VXGE_HAL_PCI_MSIX_PBA_OFFSET 0xFFFFFFF8 /* Table offset mask */
518 #define VXGE_HAL_PCI_MSIX_PBA_BIR 0x00000007 /* Table BIR mask */
519 } vxge_hal_msix_capability_le_t;
521 typedef struct vxge_hal_msix_capability_t {
522 #if defined(VXGE_OS_HOST_BIG_ENDIAN)
524 #define VXGE_HAL_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSIX Enable */
525 #define VXGE_HAL_PCI_MSIX_FLAGS_MASK 0x4000 /* Mask all vectors */
526 #define VXGE_HAL_PCI_MSIX_FLAGS_TSIZE 0x001f /* Table Size */
527 u8 next_capability_ptr;
530 #define VXGE_HAL_PCI_MSIX_TABLE_OFFSET 0xFFFFFFF8 /* Table offset mask */
531 #define VXGE_HAL_PCI_MSIX_TABLE_BIR 0x00000007 /* Table BIR mask */
533 #define VXGE_HAL_PCI_MSIX_PBA_OFFSET 0xFFFFFFF8 /* Table offset mask */
534 #define VXGE_HAL_PCI_MSIX_PBA_BIR 0x00000007 /* Table BIR mask */
537 u8 next_capability_ptr;
539 #define VXGE_HAL_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSIX Enable */
540 #define VXGE_HAL_PCI_MSIX_FLAGS_MASK 0x4000 /* Mask all vectors */
541 #define VXGE_HAL_PCI_MSIX_FLAGS_TSIZE 0x001f /* Table Size */
543 #define VXGE_HAL_PCI_MSIX_TABLE_OFFSET 0xFFFFFFF8 /* Table offset mask */
544 #define VXGE_HAL_PCI_MSIX_TABLE_BIR 0x00000007 /* Table BIR mask */
546 #define VXGE_HAL_PCI_MSIX_PBA_OFFSET 0xFFFFFFF8 /* Table offset mask */
547 #define VXGE_HAL_PCI_MSIX_PBA_BIR 0x00000007 /* Table BIR mask */
549 } vxge_hal_msix_capability_t;
551 typedef struct vxge_hal_pci_caps_offset_t {
559 } vxge_hal_pci_caps_offset_t;
561 typedef struct vxge_hal_pci_e_capability_le_t {
563 u8 next_capability_ptr;
565 #define VXGE_HAL_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
566 #define VXGE_HAL_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
567 #define VXGE_HAL_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
568 #define VXGE_HAL_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
569 #define VXGE_HAL_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
570 #define VXGE_HAL_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
571 #define VXGE_HAL_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
572 #define VXGE_HAL_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
573 #define VXGE_HAL_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
574 #define VXGE_HAL_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt msg number */
576 #define VXGE_HAL_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
577 #define VXGE_HAL_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
578 #define VXGE_HAL_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
579 #define VXGE_HAL_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
580 #define VXGE_HAL_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
581 #define VXGE_HAL_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
582 #define VXGE_HAL_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Ind Present */
583 #define VXGE_HAL_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
584 #define VXGE_HAL_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
585 #define VXGE_HAL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
587 #define VXGE_HAL_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Err Report En. */
588 #define VXGE_HAL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Err Report En */
589 #define VXGE_HAL_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Report En */
590 #define VXGE_HAL_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Req Report En. */
591 #define VXGE_HAL_PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
592 #define VXGE_HAL_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
593 #define VXGE_HAL_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
594 #define VXGE_HAL_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
595 #define VXGE_HAL_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
596 #define VXGE_HAL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
597 #define VXGE_HAL_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
599 #define VXGE_HAL_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
600 #define VXGE_HAL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
601 #define VXGE_HAL_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
602 #define VXGE_HAL_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Req Detected */
603 #define VXGE_HAL_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
604 #define VXGE_HAL_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
606 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_SPEED 0xf /* Supported Link speeds. */
607 #define VXGE_HAL_PCI_EXP_LNKCAP_LS_2_5 0x1 /* 2.5 Gb/s supported. */
608 #define VXGE_HAL_PCI_EXP_LNKCAP_LS_5 0x2 /* 5 and 2.5 Gb/s supported. */
609 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_WIDTH 0x3f0 /* Supported Link speeds. */
610 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_RES 0x0 /* Reserved. */
611 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X1 0x1 /* Reserved. */
612 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X2 0x2 /* Reserved. */
613 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X4 0x4 /* Reserved. */
614 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X8 0x8 /* Reserved. */
615 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X12 0xa /* Reserved. */
616 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X16 0x10 /* Reserved. */
617 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X32 0x20 /* Reserved. */
618 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ASPM 0xc00 /* Supported Link speeds. */
619 #define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES1 0x0 /* Reserved. */
620 #define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_LO 0x1 /* Reserved. */
621 #define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES2 0x2 /* Reserved. */
622 #define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_L0_L1 0x3 /* Reserved. */
623 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_LAT 0x7000 /* Supported Link speeds. */
624 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_LT_64 0x0 /* Less than 64ns. */
625 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_64_128 0x1 /* 64ns to less than 128ns. */
626 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_128_256 0x2 /* 128ns to less than 256ns. */
627 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_256_512 0x3 /* 256ns to less than 512ns. */
628 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_512_1us 0x4 /* 512ns to less than 1s. */
629 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_1us_2us 0x5 /* 1s to less than 2s. */
630 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_2us_4us 0x6 /* 2s-4s. */
631 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_GT_4us 0x7 /* More than 4s. */
632 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_LAT 0x38000 /* Supported Link speeds. */
633 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_LT_1us 0x0 /* Less than 1us. */
634 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_1us_2us 0x1 /* 1us to less than 2us. */
635 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_2us_4us 0x2 /* 2us to less than 4us. */
636 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_4us_8us 0x3 /* 4us to less than 8us. */
637 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_8us_16us 0x4 /* 8us to less than 16us. */
638 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_16us_32us 0x5 /* 16us to less than 32us. */
639 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_32us_64us 0x6 /* 32us-64us. */
640 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_GT_64us 0x7 /* More than 64us. */
641 #define VXGE_HAL_PCI_EXP_LNKCAP_CLK_PWR_MGMT 0x40000 /* Clk power management. */
642 #define VXGE_HAL_PCI_EXP_LNKCAP_DOWN_ERR_CAP 0x80000 /* Down error capable. */
643 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ACT_CAP 0x100000 /* DL active rep cap. */
644 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_BW_CAP 0x200000 /* DL bw reporting cap. */
645 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_PORT_NUM 0xff000000 /* Port number. */
647 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM 0x3 /* ASPM Control. */
648 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_DISABLED 0x0 /* Disabled. */
649 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_EN 0x1 /* L0 entry enabled. */
650 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L1_EN 0x2 /* L1 entry enabled. */
651 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_L1_EN 0x3 /* L0 & L1 entry enabled. */
652 #define VXGE_HAL_PCI_EXP_LNKCTL_RCB 0x8 /* Read Completion Boundary. */
653 #define VXGE_HAL_PCI_EXP_LNKCTL_RCB_64 0x0 /* RCB 64 bytes. */
654 #define VXGE_HAL_PCI_EXP_LNKCTL_RCB_128 0x1 /* RCB 128 bytes. */
655 #define VXGE_HAL_PCI_EXP_LNKCTL_DISABLED 0x10 /* Disables the link. */
656 #define VXGE_HAL_PCI_EXP_LNKCTL_RETRAIN 0x20 /* Retrain the link. */
657 #define VXGE_HAL_PCI_EXP_LNKCTL_CCCFG 0x40 /* Common clock config. */
658 #define VXGE_HAL_PCI_EXP_LNKCTL_EXT_SYNC 0x80 /* Extended Sync. */
659 #define VXGE_HAL_PCI_EXP_LNKCTL_CLK_PWRMGMT 0x100 /* Enable clk pwr mgmt. */
660 #define VXGE_HAL_PCI_EXP_LNKCTL_HW_AUTO_DIS 0x200 /* Hw autonomous with dis */
661 #define VXGE_HAL_PCI_EXP_LNKCTL_BWM_INTR_EN 0x400 /* Bw mgt interrupt enable */
662 #define VXGE_HAL_PCI_EXP_LNKCTL_ABW_INTR_EN 0x800 /* Autonomous BW intr en */
664 #define VXGE_HAL_PCI_EXP_LNKSTA_LNK_SPEED 0xf /* Supported Link speeds. */
665 #define VXGE_HAL_PCI_EXP_LNKSTA_LS_2_5 0x1 /* 2.5 Gb/s supported. */
666 #define VXGE_HAL_PCI_EXP_LNKSTA_LS_5 0x2 /* 5 2.5 Gb/s supported. */
667 #define VXGE_HAL_PCI_EXP_LNKSTA_LNK_WIDTH 0x3f0 /* Supported Link speeds. */
668 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_RES 0x0 /* Reserved. */
669 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X1 0x1 /* Reserved. */
670 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X2 0x2 /* Reserved. */
671 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X4 0x4 /* Reserved. */
672 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X8 0x8 /* Reserved. */
673 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X12 0xa /* Reserved. */
674 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X16 0x10 /* Reserved. */
675 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X32 0x20 /* Reserved. */
676 #define VXGE_HAL_PCI_EXP_LNKSTA_LNK_TRAIN 0x800 /* Link training. */
677 #define VXGE_HAL_PCI_EXP_LNKSTA_SCLK_CFG 0x1000 /* Slot Clock Config. */
678 #define VXGE_HAL_PCI_EXP_LNKSTA_DLL_ACTIVE 0x2000 /* Data LL Active. */
679 #define VXGE_HAL_PCI_EXP_LNKSTA_BWM_STA 0x4000 /* Bw mgmt intr enable */
680 #define VXGE_HAL_PCI_EXP_LNKSTA_ABW_STA 0x8000 /* Autonomous BW intr en */
682 #define VXGE_HAL_PCI_EXP_STLCAP_ATTN_BTTN 0x1 /* Attention Button Present */
683 #define VXGE_HAL_PCI_EXP_STLCAP_PWR_CTRL 0x2 /* Power Control Present */
684 #define VXGE_HAL_PCI_EXP_STLCAP_MRL_SENS 0x4 /* MRL Sesor Present */
685 #define VXGE_HAL_PCI_EXP_STLCAP_ATTN_IND 0x8 /* Attention Ind Present */
686 #define VXGE_HAL_PCI_EXP_STLCAP_PWR_IND 0x10 /* Power Indicator Present */
687 #define VXGE_HAL_PCI_EXP_STLCAP_HP_SURP 0x20 /* Hot-Plug Surprise */
688 #define VXGE_HAL_PCI_EXP_STLCAP_HP_CAP 0x40 /* Hot-Plug Surprise */
689 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_VAL 0x7F80 /* Hot-Plug Surprise */
690 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_250 0xF0 /* 250 W Slot Power Limit */
691 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_275 0xF1 /* 275 W Slot Power Limit */
692 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_300 0xF2 /* 300 W Slot Power Limit */
693 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_LIM 0x18000 /* Hot-Plug Surprise */
694 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_1X 0x0 /* 1.0x */
695 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY10 0x1 /* 0.1x */
696 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY100 0x2 /* 0.01x */
697 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY1000 0x3 /* 0.001x */
698 #define VXGE_HAL_PCI_EXP_STLCAP_EM_INTR_LOCK 0x20000 /* Ele-mec Intrlock Pres */
699 #define VXGE_HAL_PCI_EXP_STLCAP_NO_CMD_CMPL 0x40000 /* No Cmd Compl Support */
700 #define VXGE_HAL_PCI_EXP_STLCAP_PHY_SL_NO 0xFFF80000 /* Phys Slot Number */
702 #define VXGE_HAL_PCI_EXP_STLCTL_ATTN_BTN_EN 0x1 /* Atten Btn pressed enable */
703 #define VXGE_HAL_PCI_EXP_STLCTL_PF_DET_EN 0x2 /* Power Fault Detected En */
704 #define VXGE_HAL_PCI_EXP_STLCTL_MRL_SENS_EN 0x4 /* MRL Sensor Changed Enable */
705 #define VXGE_HAL_PCI_EXP_STLCTL_PDET_CH_EN 0x8 /* Presence Detect Change En */
706 #define VXGE_HAL_PCI_EXP_STLCTL_CC_INTR_EN 0x10 /* Cmd Compl Intr Enable */
707 #define VXGE_HAL_PCI_EXP_STLCTL_HP_INTR_EN 0x20 /* Hot-Plug Intr Enable */
708 #define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_CTRL 0xC0 /* Attention Ind Control */
709 #define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_RES 0x0 /* Reserved */
710 #define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_ON 0x1 /* On */
711 #define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_BLNK 0x2 /* Blink */
712 #define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_OFF 0x3 /* Off */
713 #define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_CTRL 0x300 /* POwer Indicator Control */
714 #define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_RES 0x0 /* Reserved */
715 #define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_ON 0x1 /* On */
716 #define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_BLNK 0x2 /* Blink */
717 #define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_OFF 0x3 /* Off */
718 #define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_CTRL 0x400 /* Power Controller Ctrl */
719 #define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_on 0x0 /* Power on */
720 #define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_off 0x1 /* Power off */
721 #define VXGE_HAL_PCI_EXP_STLCTL_EM_IL_CTRL 0x800 /* Ele-mec Interlock Crl */
722 #define VXGE_HAL_PCI_EXP_STLCTL_DLL_ST_CH_EN 0x1000 /* DL Layer State Ch En */
724 #define VXGE_HAL_PCI_EXP_STLSTA_ATTN_BTN 0x1 /* Attention Button Pressed */
725 #define VXGE_HAL_PCI_EXP_STLSTA_PF_DET 0x2 /* Power Fault Detected */
726 #define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CH 0x4 /* MRL Sensor Changed */
727 #define VXGE_HAL_PCI_EXP_STLSTA_PDET_CH 0x8 /* Presence Detect Changed */
728 #define VXGE_HAL_PCI_EXP_STLSTA_CMD_COMPL 0x10 /* Command Completed */
729 #define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_STA 0x20 /* MRL Sensor State */
730 #define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CL 0x0 /* MRL Sensor State - closed */
731 #define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_OP 0x1 /* MRL Sensor State - open */
732 #define VXGE_HAL_PCI_EXP_STLSTA_PDET_STA 0x400 /* Presence Detect State */
733 #define VXGE_HAL_PCI_EXP_STLSTA_PDET_EMPTY 0x0 /* Clost Empty */
734 #define VXGE_HAL_PCI_EXP_STLSTA_PDET_PRESENT 0x1 /* Card Present */
735 #define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_STA 0x80 /* Ele-mec Intrlock Control */
736 #define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_DIS 0x0 /* Disengaged */
737 #define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_EN 0x1 /* Engaged */
738 #define VXGE_HAL_PCI_EXP_STLSTA_DLL_ST_CH 0x100 /* DL Layer State Changed */
740 #define VXGE_HAL_PCI_EXP_RTCTL_SECEE 0x01 /* Sys Err on Correctable Error */
741 #define VXGE_HAL_PCI_EXP_RTCTL_SENFEE 0x02 /* Sys Err on Non-Fatal Error */
742 #define VXGE_HAL_PCI_EXP_RTCTL_SEFEE 0x04 /* Sys Err on Fatal Error */
743 #define VXGE_HAL_PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
744 #define VXGE_HAL_PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS SW Visibility Enable */
746 #define VXGE_HAL_PCI_EXP_RTCAP_CRS_SW_VIS 0x01 /* CRS SW Visibility */
748 #define VXGE_HAL_PCI_EXP_RTSTA_PME_REQ_ID 0xFFFF /* PME Requestor ID */
749 #define VXGE_HAL_PCI_EXP_RTSTA_PME_STATUS 0x10000 /* PME status */
750 #define VXGE_HAL_PCI_EXP_RTSTA_PME_PENDING 0x20000 /* PME Pending */
751 } vxge_hal_pci_e_capability_le_t;
753 typedef struct vxge_hal_pci_e_capability_t {
754 #if defined(VXGE_OS_HOST_BIG_ENDIAN)
756 #define VXGE_HAL_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
757 #define VXGE_HAL_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
758 #define VXGE_HAL_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
759 #define VXGE_HAL_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
760 #define VXGE_HAL_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
761 #define VXGE_HAL_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
762 #define VXGE_HAL_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
763 #define VXGE_HAL_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
764 #define VXGE_HAL_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
765 #define VXGE_HAL_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
766 u8 next_capability_ptr;
769 #define VXGE_HAL_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
770 #define VXGE_HAL_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
771 #define VXGE_HAL_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
772 #define VXGE_HAL_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
773 #define VXGE_HAL_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
774 #define VXGE_HAL_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
775 #define VXGE_HAL_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Ind Present */
776 #define VXGE_HAL_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
777 #define VXGE_HAL_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
778 #define VXGE_HAL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
780 #define VXGE_HAL_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Err Detected */
781 #define VXGE_HAL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
782 #define VXGE_HAL_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
783 #define VXGE_HAL_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Req Detected */
784 #define VXGE_HAL_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
785 #define VXGE_HAL_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
787 #define VXGE_HAL_PCI_EXP_DEVCTL_CERE 0x0001 /* Corr'ble Err Reporting En. */
788 #define VXGE_HAL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Err Reporting En */
789 #define VXGE_HAL_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting En */
790 #define VXGE_HAL_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupp Req Reporting En. */
791 #define VXGE_HAL_PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
792 #define VXGE_HAL_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
793 #define VXGE_HAL_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
794 #define VXGE_HAL_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
795 #define VXGE_HAL_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
796 #define VXGE_HAL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
797 #define VXGE_HAL_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
799 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_SPEED 0xf /* Supported Link speeds. */
800 #define VXGE_HAL_PCI_EXP_LNKCAP_LS_2_5 0x1 /* 2.5 Gb/s supported. */
801 #define VXGE_HAL_PCI_EXP_LNKCAP_LS_5 0x2 /* 5 2.5 Gb/s supported. */
802 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_WIDTH 0x3f0 /* Supported Link speeds. */
803 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_RES 0x0 /* Reserved. */
804 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X1 0x1 /* Reserved. */
805 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X2 0x2 /* Reserved. */
806 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X4 0x4 /* Reserved. */
807 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X8 0x8 /* Reserved. */
808 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X12 0xa /* Reserved. */
809 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X16 0x10 /* Reserved. */
810 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X32 0x20 /* Reserved. */
811 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ASPM 0xc00 /* Supported Link speeds. */
812 #define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES1 0x0 /* Reserved. */
813 #define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_LO 0x1 /* Reserved. */
814 #define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES2 0x2 /* Reserved. */
815 #define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_L0_L1 0x3 /* Reserved. */
816 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_LAT 0x7000 /* Supported Link speeds. */
817 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_LT_64 0x0 /* Less than 64 ns. */
818 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_64_128 0x1 /* 64 ns to less than 128 ns. */
819 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_128_256 0x2 /* 128 ns to less than 256 ns. */
820 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_256_512 0x3 /* 256 ns to less than 512 ns. */
821 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_512_1us 0x4 /* 512 ns to less than 1us. */
822 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_1us_2us 0x5 /* 1us to less than 2us. */
823 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_2us_4us 0x6 /* 2us-4us. */
824 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_GT_4us 0x7 /* More than 4us. */
825 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_LAT 0x38000 /* Supported Link speeds. */
826 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_LT_1us 0x0 /* Less than 1us. */
827 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_1us_2us 0x1 /* 1us to less than 2us. */
828 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_2us_4us 0x2 /* 2us to less than 4us. */
829 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_4us_8us 0x3 /* 4us to less than 8us. */
830 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_8us_16us 0x4 /* 8us to less than 16us. */
831 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_16us_32us 0x5 /* 16us to less than 32us. */
832 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_32us_64us 0x6 /* 32us-64s. */
833 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_GT_64us 0x7 /* More than 64us. */
834 #define VXGE_HAL_PCI_EXP_LNKCAP_CLK_PWR_MGMT 0x40000 /* Clk power management. */
835 #define VXGE_HAL_PCI_EXP_LNKCAP_DOWN_ERR_CAP 0x80000 /* Down error capable. */
836 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ACT_CAP 0x100000 /* DL active rep cap. */
837 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_BW_CAP 0x200000 /* DL bw rep cap. */
838 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_PORT_NUM 0xff000000 /* Port number. */
840 #define VXGE_HAL_PCI_EXP_LNKSTA_LNK_SPEED 0xf /* Supported Link speeds. */
841 #define VXGE_HAL_PCI_EXP_LNKSTA_LS_2_5 0x1 /* 2.5 Gb/s supported. */
842 #define VXGE_HAL_PCI_EXP_LNKSTA_LS_5 0x2 /* 5 2.5 Gb/s supported. */
843 #define VXGE_HAL_PCI_EXP_LNKSTA_LNK_WIDTH 0x3f0 /* Supported Link speeds. */
844 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_RES 0x0 /* Reserved. */
845 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X1 0x1 /* Reserved. */
846 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X2 0x2 /* Reserved. */
847 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X4 0x4 /* Reserved. */
848 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X8 0x8 /* Reserved. */
849 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X12 0xa /* Reserved. */
850 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X16 0x10 /* Reserved. */
851 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X32 0x20 /* Reserved. */
852 #define VXGE_HAL_PCI_EXP_LNKSTA_LNK_TRAIN 0x800 /* Link training. */
853 #define VXGE_HAL_PCI_EXP_LNKSTA_SCLK_CFG 0x1000 /* Slot Clock Config. */
854 #define VXGE_HAL_PCI_EXP_LNKSTA_DLL_ACTIVE 0x2000 /* Data LL Active. */
855 #define VXGE_HAL_PCI_EXP_LNKSTA_BWM_STA 0x4000 /* Bw mgmt interrupt enable */
856 #define VXGE_HAL_PCI_EXP_LNKSTA_ABW_STA 0x8000 /* Autonomous BW intr en */
858 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM 0x3 /* ASPM Control. */
859 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_DISABLED 0x0 /* Disabled. */
860 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_EN 0x1 /* L0 entry enabled. */
861 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L1_EN 0x2 /* L1 entry enabled. */
862 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_L1_EN 0x3 /* L0 & L1 entry enabled. */
863 #define VXGE_HAL_PCI_EXP_LNKCTL_RCB 0x8 /* Read Compl Boundary. */
864 #define VXGE_HAL_PCI_EXP_LNKCTL_RCB_64 0x0 /* RCB 64 bytes. */
865 #define VXGE_HAL_PCI_EXP_LNKCTL_RCB_128 0x1 /* RCB 128 bytes. */
866 #define VXGE_HAL_PCI_EXP_LNKCTL_DISABLED 0x10 /* Disables the link. */
867 #define VXGE_HAL_PCI_EXP_LNKCTL_RETRAIN 0x20 /* Retrain the link. */
868 #define VXGE_HAL_PCI_EXP_LNKCTL_CCCFG 0x40 /* Common clock config. */
869 #define VXGE_HAL_PCI_EXP_LNKCTL_EXT_SYNC 0x80 /* Extended Sync. */
870 #define VXGE_HAL_PCI_EXP_LNKCTL_CLK_PWRMGMT 0x100 /* Enable clk pwr mgmt. */
871 #define VXGE_HAL_PCI_EXP_LNKCTL_HW_AUTO_DIS 0x200 /* Hw autonomous w/dis */
872 #define VXGE_HAL_PCI_EXP_LNKCTL_BWM_INTR_EN 0x400 /* Bw mgmt intr enable */
873 #define VXGE_HAL_PCI_EXP_LNKCTL_ABW_INTR_EN 0x800 /* Autonomous BW int en */
875 #define VXGE_HAL_PCI_EXP_STLCAP_ATTN_BTTN 0x1 /* Attention Button Present */
876 #define VXGE_HAL_PCI_EXP_STLCAP_PWR_CTRL 0x2 /* Power Control Present */
877 #define VXGE_HAL_PCI_EXP_STLCAP_MRL_SENS 0x4 /* MRL Sesor Present */
878 #define VXGE_HAL_PCI_EXP_STLCAP_ATTN_IND 0x8 /* Attention Ind Present */
879 #define VXGE_HAL_PCI_EXP_STLCAP_PWR_IND 0x10 /* Power Indicator Present */
880 #define VXGE_HAL_PCI_EXP_STLCAP_HP_SURP 0x20 /* Hot-Plug Surprise */
881 #define VXGE_HAL_PCI_EXP_STLCAP_HP_CAP 0x40 /* Hot-Plug Surprise */
882 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_VAL 0x7F80 /* Hot-Plug Surprise */
883 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_250 0xF0 /* 250 W Slot Power Limit */
884 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_275 0xF1 /* 275 W Slot Power Limit */
885 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_300 0xF2 /* 300 W Slot Power Limit */
886 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_LIM 0x18000 /* Hot-Plug Surprise */
887 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_1X 0x0 /* 1.0x */
888 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY10 0x1 /* 0.1x */
889 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY100 0x2 /* 0.01x */
890 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY1000 0x3 /* 0.001x */
891 #define VXGE_HAL_PCI_EXP_STLCAP_EM_INTR_LOCK 0x20000 /* Ele-mec Intrlock Pres */
892 #define VXGE_HAL_PCI_EXP_STLCAP_NO_CMD_CMPL 0x40000 /* No Command Compl Supp */
893 #define VXGE_HAL_PCI_EXP_STLCAP_PHY_SL_NO 0xFFF80000 /* Phy Slot Number */
895 #define VXGE_HAL_PCI_EXP_STLSTA_ATTN_BTN 0x1 /* Attention Button Pressed */
896 #define VXGE_HAL_PCI_EXP_STLSTA_PF_DET 0x2 /* Power Fault Detected */
897 #define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CH 0x4 /* MRL Sensor Changed */
898 #define VXGE_HAL_PCI_EXP_STLSTA_PDET_CH 0x8 /* Presence Detect Changed */
899 #define VXGE_HAL_PCI_EXP_STLSTA_CMD_COMPL 0x10 /* Command Completed */
900 #define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_STA 0x20 /* MRL Sensor State */
901 #define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CL 0x0 /* MRL Sensor State - closed */
902 #define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_OP 0x1 /* MRL Sensor State - open */
903 #define VXGE_HAL_PCI_EXP_STLSTA_PDET_STA 0x400 /* Presence Detect State */
904 #define VXGE_HAL_PCI_EXP_STLSTA_PDET_EMPTY 0x0 /* Clost Empty */
905 #define VXGE_HAL_PCI_EXP_STLSTA_PDET_PRESENT 0x1 /* Card Present */
906 #define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_STA 0x80 /* Ele-mec Intrlock Ctrl */
907 #define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_DIS 0x0 /* Disengaged */
908 #define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_EN 0x1 /* Engaged */
909 #define VXGE_HAL_PCI_EXP_STLSTA_DLL_ST_CH 0x100 /* DL State Changed */
911 #define VXGE_HAL_PCI_EXP_STLCTL_ATTN_BTN_EN 0x1 /* Atten Btn pressed en */
912 #define VXGE_HAL_PCI_EXP_STLCTL_PF_DET_EN 0x2 /* Pwr Fault Detected En */
913 #define VXGE_HAL_PCI_EXP_STLCTL_MRL_SENS_EN 0x4 /* MRL Sensor Changed En */
914 #define VXGE_HAL_PCI_EXP_STLCTL_PDET_CH_EN 0x8 /* Presence Detect Changed En */
915 #define VXGE_HAL_PCI_EXP_STLCTL_CC_INTR_EN 0x10 /* Cmmd Completed Intr En */
916 #define VXGE_HAL_PCI_EXP_STLCTL_HP_INTR_EN 0x20 /* Hot-Plug Intr Enable */
917 #define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_CTRL 0xC0 /* Attention Ind Ctrl */
918 #define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_RES 0x0 /* Reserved */
919 #define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_ON 0x1 /* On */
920 #define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_BLNK 0x2 /* Blink */
921 #define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_OFF 0x3 /* Off */
922 #define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_CTRL 0x300 /* POwer Ind Control */
923 #define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_RES 0x0 /* Reserved */
924 #define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_ON 0x1 /* On */
925 #define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_BLNK 0x2 /* Blink */
926 #define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_OFF 0x3 /* Off */
927 #define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_CTRL 0x400 /* Power Controller Ctrl */
928 #define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_on 0x0 /* Power on */
929 #define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_off 0x1 /* Power off */
930 #define VXGE_HAL_PCI_EXP_STLCTL_EM_IL_CTRL 0x800 /* Ele-mec Intrlock Ctrl */
931 #define VXGE_HAL_PCI_EXP_STLCTL_DLL_ST_CH_EN 0x1000 /* DL State Changed En */
933 #define VXGE_HAL_PCI_EXP_RTCAP_CRS_SW_VIS 0x01 /* CRS Software Visibility */
935 #define VXGE_HAL_PCI_EXP_RTCTL_SECEE 0x01 /* Sys Err on Correctable Error */
936 #define VXGE_HAL_PCI_EXP_RTCTL_SENFEE 0x02 /* Sys Err on Non-Fatal Error */
937 #define VXGE_HAL_PCI_EXP_RTCTL_SEFEE 0x04 /* Sys Err on Fatal Error */
938 #define VXGE_HAL_PCI_EXP_RTCTL_PMEIE 0x08 /* PME Intr Enable */
939 #define VXGE_HAL_PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS SW Visibility Enable */
941 #define VXGE_HAL_PCI_EXP_RTSTA_PME_REQ_ID 0xFFFF /* PME Requestor ID */
942 #define VXGE_HAL_PCI_EXP_RTSTA_PME_STATUS 0x10000 /* PME status */
943 #define VXGE_HAL_PCI_EXP_RTSTA_PME_PENDING 0x20000 /* PME Pending */
946 u8 next_capability_ptr;
948 #define VXGE_HAL_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
949 #define VXGE_HAL_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
950 #define VXGE_HAL_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
951 #define VXGE_HAL_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
952 #define VXGE_HAL_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
953 #define VXGE_HAL_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
954 #define VXGE_HAL_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
955 #define VXGE_HAL_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
956 #define VXGE_HAL_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
957 #define VXGE_HAL_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
959 #define VXGE_HAL_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
960 #define VXGE_HAL_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
961 #define VXGE_HAL_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
962 #define VXGE_HAL_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
963 #define VXGE_HAL_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
964 #define VXGE_HAL_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
965 #define VXGE_HAL_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Ind Present */
966 #define VXGE_HAL_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
967 #define VXGE_HAL_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
968 #define VXGE_HAL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
970 #define VXGE_HAL_PCI_EXP_DEVCTL_CERE 0x0001 /* Corr'ble Err Reporting En. */
971 #define VXGE_HAL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Err Reporting En */
972 #define VXGE_HAL_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Err Reporting En */
973 #define VXGE_HAL_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupp Req Reporting En. */
974 #define VXGE_HAL_PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
975 #define VXGE_HAL_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
976 #define VXGE_HAL_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
977 #define VXGE_HAL_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
978 #define VXGE_HAL_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
979 #define VXGE_HAL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
980 #define VXGE_HAL_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
982 #define VXGE_HAL_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
983 #define VXGE_HAL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
984 #define VXGE_HAL_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
985 #define VXGE_HAL_PCI_EXP_DEVSTA_URD 0x08 /* Unsupp Request Detected */
986 #define VXGE_HAL_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
987 #define VXGE_HAL_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
989 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_SPEED 0xf /* Supported Link speeds. */
990 #define VXGE_HAL_PCI_EXP_LNKCAP_LS_2_5 0x1 /* 2.5 Gb/s supported. */
991 #define VXGE_HAL_PCI_EXP_LNKCAP_LS_5 0x2 /* 5 and 2.5 Gb/s supported. */
992 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_WIDTH 0x3f0 /* Supported Link speeds. */
993 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_RES 0x0 /* Reserved. */
994 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X1 0x1 /* Reserved. */
995 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X2 0x2 /* Reserved. */
996 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X4 0x4 /* Reserved. */
997 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X8 0x8 /* Reserved. */
998 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X12 0xa /* Reserved. */
999 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X16 0x10 /* Reserved. */
1000 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X32 0x20 /* Reserved. */
1001 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ASPM 0xc00 /* Supported Link speeds. */
1002 #define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES1 0x0 /* Reserved. */
1003 #define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_LO 0x1 /* Reserved. */
1004 #define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES2 0x2 /* Reserved. */
1005 #define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_L0_L1 0x3 /* Reserved. */
1006 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_LAT 0x7000 /* Supported Link speeds. */
1007 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_LT_64 0x0 /* Less than 64 ns. */
1008 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_64_128 0x1 /* 64ns to less than 128ns. */
1009 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_128_256 0x2 /* 128ns to less than 256ns. */
1010 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_256_512 0x3 /* 256ns to less than 512ns. */
1011 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_512_1us 0x4 /* 512ns to less than 1us. */
1012 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_1us_2us 0x5 /* 1us to less than 2us. */
1013 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_2us_4us 0x6 /* 2us-4us. */
1014 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_GT_4us 0x7 /* More than 4us. */
1015 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_LAT 0x38000 /* Supported Link speeds. */
1016 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_LT_1us 0x0 /* Less than 1us. */
1017 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_1us_2us 0x1 /* 1us to less than 2us. */
1018 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_2us_4us 0x2 /* 2us to less than 4us. */
1019 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_4us_8us 0x3 /* 4us to less than 8us. */
1020 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_8us_16us 0x4 /* 8us to less than 16us. */
1021 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_16us_32us 0x5 /* 16us to less than 32us. */
1022 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_32us_64us 0x6 /* 32us-64us. */
1023 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_GT_64us 0x7 /* More than 64us. */
1024 #define VXGE_HAL_PCI_EXP_LNKCAP_CLK_PWR_MGMT 0x40000 /* Clock power mgmt */
1025 #define VXGE_HAL_PCI_EXP_LNKCAP_DOWN_ERR_CAP 0x80000 /* Down error capable. */
1026 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_ACT_CAP 0x100000 /* DL active rep cap. */
1027 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_BW_CAP 0x200000 /* DL bw rep cap. */
1028 #define VXGE_HAL_PCI_EXP_LNKCAP_LNK_PORT_NUM 0xff000000 /* Port number. */
1030 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM 0x3 /* ASPM Control. */
1031 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_DISABLED 0x0 /* Disabled. */
1032 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_EN 0x1 /* L0 entry enabled. */
1033 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L1_EN 0x2 /* L1 entry enabled. */
1034 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_L1_EN 0x3 /* L0 & L1 entry enabled. */
1035 #define VXGE_HAL_PCI_EXP_LNKCTL_RCB 0x8 /* Read Completion Boundary. */
1036 #define VXGE_HAL_PCI_EXP_LNKCTL_RCB_64 0x0 /* RCB 64 bytes. */
1037 #define VXGE_HAL_PCI_EXP_LNKCTL_RCB_128 0x1 /* RCB 128 bytes. */
1038 #define VXGE_HAL_PCI_EXP_LNKCTL_DISABLED 0x10 /* Disables the link. */
1039 #define VXGE_HAL_PCI_EXP_LNKCTL_RETRAIN 0x20 /* Retrain the link. */
1040 #define VXGE_HAL_PCI_EXP_LNKCTL_CCCFG 0x40 /* Common clock config. */
1041 #define VXGE_HAL_PCI_EXP_LNKCTL_EXT_SYNC 0x80 /* Extended Sync. */
1042 #define VXGE_HAL_PCI_EXP_LNKCTL_CLK_PWRMGMT 0x100 /* Enable clock power mgmt */
1043 #define VXGE_HAL_PCI_EXP_LNKCTL_HW_AUTO_DIS 0x200 /* HW autonomous with dis */
1044 #define VXGE_HAL_PCI_EXP_LNKCTL_BWM_INTR_EN 0x400 /* Bw mgmt interrupt enable */
1045 #define VXGE_HAL_PCI_EXP_LNKCTL_ABW_INTR_EN 0x800 /* Autonomous BW int enable */
1047 #define VXGE_HAL_PCI_EXP_LNKSTA_LNK_SPEED 0xf /* Supported Link speeds. */
1048 #define VXGE_HAL_PCI_EXP_LNKSTA_LS_2_5 0x1 /* 2.5 Gb/s supported. */
1049 #define VXGE_HAL_PCI_EXP_LNKSTA_LS_5 0x2 /* 5 and 2.5 Gb/s supported */
1050 /* Supported Link speeds. */
1051 #define VXGE_HAL_PCI_EXP_LNKSTA_LNK_WIDTH 0x3f0
1052 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_RES 0x0 /* Reserved. */
1053 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X1 0x1 /* Reserved. */
1054 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X2 0x2 /* Reserved. */
1055 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X4 0x4 /* Reserved. */
1056 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X8 0x8 /* Reserved. */
1057 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X12 0xa /* Reserved. */
1058 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X16 0x10 /* Reserved. */
1059 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X32 0x20 /* Reserved. */
1060 #define VXGE_HAL_PCI_EXP_LNKSTA_LNK_TRAIN 0x800 /* Link training. */
1061 #define VXGE_HAL_PCI_EXP_LNKSTA_SCLK_CFG 0x1000 /* Slot Clock Config. */
1062 #define VXGE_HAL_PCI_EXP_LNKSTA_DLL_ACTIVE 0x2000 /* Data LL Active. */
1063 #define VXGE_HAL_PCI_EXP_LNKSTA_BWM_STA 0x4000 /* Bw mgmt intr enable */
1064 #define VXGE_HAL_PCI_EXP_LNKSTA_ABW_STA 0x8000 /* Autonomous BW intr en */
1066 #define VXGE_HAL_PCI_EXP_STLCAP_ATTN_BTTN 0x1 /* Attention Button Present */
1067 #define VXGE_HAL_PCI_EXP_STLCAP_PWR_CTRL 0x2 /* Power Control Present */
1068 #define VXGE_HAL_PCI_EXP_STLCAP_MRL_SENS 0x4 /* MRL Sesor Present */
1069 #define VXGE_HAL_PCI_EXP_STLCAP_ATTN_IND 0x8 /* Attention Ind Present */
1070 /* Power Indicator Present */
1071 #define VXGE_HAL_PCI_EXP_STLCAP_PWR_IND 0x10
1072 #define VXGE_HAL_PCI_EXP_STLCAP_HP_SURP 0x20 /* Hot-Plug Surprise */
1073 #define VXGE_HAL_PCI_EXP_STLCAP_HP_CAP 0x40 /* Hot-Plug Surprise */
1074 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_VAL 0x7F80 /* Hot-Plug Surprise */
1075 /* 250 W Slot Power Limit */
1076 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_250 0xF0
1077 /* 275 W Slot Power Limit */
1078 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_275 0xF1
1079 /* 300 W Slot Power Limit */
1080 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_300 0xF2
1081 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_LIM 0x18000 /* Hot-Plug Surprise */
1082 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_1X 0x0 /* 1.0x */
1083 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY10 0x1 /* 0.1x */
1084 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY100 0x2 /* 0.01x */
1085 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY1000 0x3 /* 0.001x */
1086 #define VXGE_HAL_PCI_EXP_STLCAP_EM_INTR_LOCK 0x20000 /* Ele-mec Intrlock Pres */
1087 #define VXGE_HAL_PCI_EXP_STLCAP_NO_CMD_CMPL 0x40000 /* No Cmd Completed Supp */
1088 #define VXGE_HAL_PCI_EXP_STLCAP_PHY_SL_NO 0xFFF80000 /* Phys Slot Number */
1090 #define VXGE_HAL_PCI_EXP_STLCTL_ATTN_BTN_EN 0x1 /* Atten Bttn pressed en */
1091 #define VXGE_HAL_PCI_EXP_STLCTL_PF_DET_EN 0x2 /* Power Fault Detected En */
1092 #define VXGE_HAL_PCI_EXP_STLCTL_MRL_SENS_EN 0x4 /* MRL Sensor Changed Enable */
1093 #define VXGE_HAL_PCI_EXP_STLCTL_PDET_CH_EN 0x8 /* Presence Detect Changed En */
1094 #define VXGE_HAL_PCI_EXP_STLCTL_CC_INTR_EN 0x10 /* Cmd Compl Intr Enable */
1095 #define VXGE_HAL_PCI_EXP_STLCTL_HP_INTR_EN 0x20 /* Hot-Plug Intr Enable */
1096 #define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_CTRL 0xC0 /* Atten Ind Control */
1097 #define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_RES 0x0 /* Reserved */
1098 #define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_ON 0x1 /* On */
1099 #define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_BLNK 0x2 /* Blink */
1100 #define VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_OFF 0x3 /* Off */
1101 #define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_CTRL 0x300 /* Power Ind Control */
1102 #define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_RES 0x0 /* Reserved */
1103 #define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_ON 0x1 /* On */
1104 #define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_BLNK 0x2 /* Blink */
1105 #define VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_OFF 0x3 /* Off */
1106 #define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_CTRL 0x400 /* Power Controller Ctrl */
1107 #define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_on 0x0 /* Power on */
1108 #define VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_off 0x1 /* Power off */
1109 #define VXGE_HAL_PCI_EXP_STLCTL_EM_IL_CTRL 0x800 /* Ele-mec Intrlock Ctrl */
1110 #define VXGE_HAL_PCI_EXP_STLCTL_DLL_ST_CH_EN 0x1000 /* DL State Changed En */
1112 #define VXGE_HAL_PCI_EXP_STLSTA_ATTN_BTN 0x1 /* Attention Button Pressed */
1113 #define VXGE_HAL_PCI_EXP_STLSTA_PF_DET 0x2 /* Power Fault Detected */
1114 #define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CH 0x4 /* MRL Sensor Changed */
1115 #define VXGE_HAL_PCI_EXP_STLSTA_PDET_CH 0x8 /* Presence Detect Changed */
1116 #define VXGE_HAL_PCI_EXP_STLSTA_CMD_COMPL 0x10 /* Command Completed */
1117 #define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_STA 0x20 /* MRL Sensor State */
1118 #define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CL 0x0 /* MRL Sensor State - closed */
1119 #define VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_OP 0x1 /* MRL Sensor State - open */
1120 #define VXGE_HAL_PCI_EXP_STLSTA_PDET_STA 0x400 /* Presence Detect State */
1121 #define VXGE_HAL_PCI_EXP_STLSTA_PDET_EMPTY 0x0 /* Clost Empty */
1122 #define VXGE_HAL_PCI_EXP_STLSTA_PDET_PRESENT 0x1 /* Card Present */
1123 /* Ele-mec Interlock Control */
1124 #define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_STA 0x80
1125 #define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_DIS 0x0 /* Disengaged */
1126 #define VXGE_HAL_PCI_EXP_STLSTA_EM_IL_EN 0x1 /* Engaged */
1127 /* DL Layer State Changed */
1128 #define VXGE_HAL_PCI_EXP_STLSTA_DLL_ST_CH 0x100
1130 #define VXGE_HAL_PCI_EXP_RTCTL_SECEE 0x01 /* Sys Err on Correctable Error */
1131 #define VXGE_HAL_PCI_EXP_RTCTL_SENFEE 0x02 /* Sys Err on Non-Fatal Error */
1132 #define VXGE_HAL_PCI_EXP_RTCTL_SEFEE 0x04 /* Sys Err on Fatal Error */
1133 #define VXGE_HAL_PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
1134 #define VXGE_HAL_PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS SW Visibility Enable */
1136 #define VXGE_HAL_PCI_EXP_RTCAP_CRS_SW_VIS 0x01 /* CRS SW Visibility */
1138 #define VXGE_HAL_PCI_EXP_RTSTA_PME_REQ_ID 0xFFFF /* PME Requestor ID */
1139 #define VXGE_HAL_PCI_EXP_RTSTA_PME_STATUS 0x10000 /* PME status */
1140 #define VXGE_HAL_PCI_EXP_RTSTA_PME_PENDING 0x20000 /* PME Pending */
1142 } vxge_hal_pci_e_capability_t;
1144 typedef u32 vxge_hal_pci_e_caps_offset_t;
1146 #define VXGE_HAL_PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
1147 #define VXGE_HAL_PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
1148 #define VXGE_HAL_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
1150 #define VXGE_HAL_PCI_EXT_CAP_ID_ERR 1
1151 #define VXGE_HAL_PCI_EXT_CAP_ID_VC 2
1152 #define VXGE_HAL_PCI_EXT_CAP_ID_DSN 3
1153 #define VXGE_HAL_PCI_EXT_CAP_ID_PWR 4
1155 typedef struct vxge_hal_err_capability_t {
1157 u32 pci_err_uncor_status;
1158 #define VXGE_HAL_PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
1159 #define VXGE_HAL_PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
1160 #define VXGE_HAL_PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
1161 #define VXGE_HAL_PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
1162 #define VXGE_HAL_PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
1163 #define VXGE_HAL_PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
1164 #define VXGE_HAL_PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
1165 #define VXGE_HAL_PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
1166 #define VXGE_HAL_PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
1167 #define VXGE_HAL_PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
1168 #define VXGE_HAL_PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
1169 u32 pci_err_uncor_mask;
1170 u32 pci_err_uncor_server;
1171 u32 pci_err_cor_status;
1172 #define VXGE_HAL_PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
1173 #define VXGE_HAL_PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
1174 #define VXGE_HAL_PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
1175 #define VXGE_HAL_PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
1176 #define VXGE_HAL_PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
1177 #define VXGE_HAL_PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
1179 #define VXGE_HAL_PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
1180 /* ECRC Generation Capable */
1181 #define VXGE_HAL_PCI_ERR_CAP_ECRC_GENC 0x00000020
1183 #define VXGE_HAL_PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
1184 #define VXGE_HAL_PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
1185 #define VXGE_HAL_PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
1187 #define VXGE_HAL_PCI_ERR_HEADER_LOG(x) ((x) >> 31) /* Error Header Log */
1189 u32 pci_err_root_command;
1190 u32 pci_err_root_status;
1191 u32 pci_err_root_cor_src;
1192 u32 pci_err_root_src;
1193 } vxge_hal_err_capability_t;
1195 typedef struct vxge_hal_vc_capability_t {
1197 u32 pci_vc_port_reg1;
1198 u32 pci_vc_port_reg2;
1199 u32 pci_vc_port_ctrl;
1200 u32 pci_vc_port_status;
1202 u32 pci_vc_res_ctrl;
1203 u32 pci_vc_res_status;
1204 } vxge_hal_vc_capability_t;
1206 typedef struct vxge_hal_pwr_budget_capability_t {
1210 #define VXGE_HAL_PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
1211 #define VXGE_HAL_PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
1212 #define VXGE_HAL_PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
1213 #define VXGE_HAL_PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
1214 #define VXGE_HAL_PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
1215 #define VXGE_HAL_PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
1217 #define VXGE_HAL_PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Include in sys budget */
1218 } vxge_hal_pwr_budget_capability_t;
1220 typedef struct vxge_hal_pci_e_ext_caps_offset_t {
1224 u32 pwr_budget_cap_offset;
1225 } vxge_hal_pci_e_ext_caps_offset_t;
1231 #endif /* VXGE_HAL_REGS_H */