2 * Copyright (c) 2001-2005 Marcel Moolenaar
3 * Copyright (c) 2000 Doug Rabson
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include "opt_kstack_pages.h"
33 #include <sys/param.h>
34 #include <sys/systm.h>
38 #include <sys/kthread.h>
40 #include <sys/malloc.h>
41 #include <sys/mutex.h>
42 #include <sys/kernel.h>
44 #include <sys/sched.h>
46 #include <sys/sysctl.h>
49 #include <machine/atomic.h>
50 #include <machine/bootinfo.h>
51 #include <machine/cpu.h>
52 #include <machine/fpu.h>
53 #include <machine/intr.h>
54 #include <machine/mca.h>
55 #include <machine/md_var.h>
56 #include <machine/pal.h>
57 #include <machine/pcb.h>
58 #include <machine/sal.h>
59 #include <machine/smp.h>
63 #include <vm/vm_extern.h>
64 #include <vm/vm_kern.h>
66 extern uint64_t bdata[];
68 MALLOC_DEFINE(M_SMP, "SMP", "SMP related allocations");
70 void ia64_ap_startup(void);
72 #define SAPIC_ID_GET_ID(x) ((u_int)((x) >> 8) & 0xff)
73 #define SAPIC_ID_GET_EID(x) ((u_int)(x) & 0xff)
74 #define SAPIC_ID_SET(id, eid) ((u_int)(((id) & 0xff) << 8) | ((eid) & 0xff))
76 /* State used to wake and bootstrap APs. */
77 struct ia64_ap_state ia64_ap_state;
80 int ia64_ipi_hardclock;
93 shft = 12; /* Start with 4K */
103 ia64_ih_ast(struct thread *td, u_int xiv, struct trapframe *tf)
106 PCPU_INC(md.stats.pcs_nasts);
107 CTR1(KTR_SMP, "IPI_AST, cpuid=%d", PCPU_GET(cpuid));
112 ia64_ih_hardclock(struct thread *td, u_int xiv, struct trapframe *tf)
115 PCPU_INC(md.stats.pcs_nhardclocks);
116 CTR1(KTR_SMP, "IPI_HARDCLOCK, cpuid=%d", PCPU_GET(cpuid));
122 ia64_ih_highfp(struct thread *td, u_int xiv, struct trapframe *tf)
125 PCPU_INC(md.stats.pcs_nhighfps);
126 ia64_highfp_save_ipi();
131 ia64_ih_preempt(struct thread *td, u_int xiv, struct trapframe *tf)
134 PCPU_INC(md.stats.pcs_npreempts);
135 CTR1(KTR_SMP, "IPI_PREEMPT, cpuid=%d", PCPU_GET(cpuid));
136 sched_preempt(curthread);
141 ia64_ih_rndzvs(struct thread *td, u_int xiv, struct trapframe *tf)
144 PCPU_INC(md.stats.pcs_nrdvs);
145 CTR1(KTR_SMP, "IPI_RENDEZVOUS, cpuid=%d", PCPU_GET(cpuid));
146 smp_rendezvous_action();
151 ia64_ih_stop(struct thread *td, u_int xiv, struct trapframe *tf)
155 PCPU_INC(md.stats.pcs_nstops);
156 cpuid = PCPU_GET(cpuid);
158 savectx(PCPU_PTR(md.pcb));
160 CPU_SET_ATOMIC(cpuid, &stopped_cpus);
161 while (!CPU_ISSET(cpuid, &started_cpus))
163 CPU_CLR_ATOMIC(cpuid, &started_cpus);
164 CPU_CLR_ATOMIC(cpuid, &stopped_cpus);
172 return smp_topo_none();
176 ia64_store_mca_state(void* arg)
178 struct pcpu *pc = arg;
179 struct thread *td = curthread;
182 * ia64_mca_save_state() is CPU-sensitive, so bind ourself to our
186 sched_bind(td, pc->pc_cpuid);
192 * Get and save the CPU specific MCA records. Should we get the
193 * MCA state for each processor, or just the CMC state?
195 ia64_mca_save_state(SAL_INFO_MCA);
196 ia64_mca_save_state(SAL_INFO_CMC);
202 ia64_ap_startup(void)
206 ia64_ap_state.as_trace = 0x100;
208 ia64_set_rr(IA64_RR_BASE(5), (5 << 8) | (PAGE_SHIFT << 2) | 1);
209 ia64_set_rr(IA64_RR_BASE(6), (6 << 8) | (PAGE_SHIFT << 2));
210 ia64_set_rr(IA64_RR_BASE(7), (7 << 8) | (PAGE_SHIFT << 2));
213 pcpup = ia64_ap_state.as_pcpu;
214 ia64_set_k4((intptr_t)pcpup);
216 ia64_ap_state.as_trace = 0x108;
218 vhpt = PCPU_GET(md.vhpt);
220 ia64_set_pta(vhpt + (1 << 8) + (pmap_vhpt_log2size << 2) + 1);
223 ia64_ap_state.as_trace = 0x110;
225 ia64_ap_state.as_awake = 1;
226 ia64_ap_state.as_delay = 0;
231 ia64_set_fpsr(IA64_FPSR_DEFAULT);
233 /* Wait until it's time for us to be unleashed */
234 while (ia64_ap_state.as_spin)
237 /* Initialize curthread. */
238 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
239 PCPU_SET(curthread, PCPU_GET(idlethread));
241 atomic_add_int(&ia64_ap_state.as_awake, 1);
245 CTR1(KTR_SMP, "SMP: cpu%d launched", PCPU_GET(cpuid));
259 cpu_mp_setmaxid(void)
263 * Count the number of processors in the system by walking the ACPI
264 * tables. Note that we record the actual number of processors, even
265 * if this is larger than MAXCPU. We only activate MAXCPU processors.
267 mp_ncpus = ia64_count_cpus();
270 * Set the largest cpuid we're going to use. This is necessary for
273 mp_maxid = min(mp_ncpus, MAXCPU) - 1;
281 * If there's only 1 processor, or we don't have a wake-up vector,
282 * we're not going to enable SMP. Note that no wake-up vector can
283 * also mean that the wake-up mechanism is not supported. In this
284 * case we can have multiple processors, but we simply can't wake
287 return (mp_ncpus > 1 && ia64_ipi_wakeup != 0);
291 cpu_mp_add(u_int acpi_id, u_int id, u_int eid)
295 u_int cpuid, sapic_id;
297 sapic_id = SAPIC_ID_SET(id, eid);
298 cpuid = (IA64_LID_GET_SAPIC_ID(ia64_get_lid()) == sapic_id)
301 KASSERT(!CPU_ISSET(cpuid, &all_cpus),
302 ("%s: cpu%d already in CPU map", __func__, acpi_id));
305 pc = (struct pcpu *)malloc(sizeof(*pc), M_SMP, M_WAITOK);
306 pcpu_init(pc, cpuid, sizeof(*pc));
307 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
309 dpcpu_init(dpcpu, cpuid);
313 cpu_pcpu_setup(pc, acpi_id, sapic_id);
315 CPU_SET(pc->pc_cpuid, &all_cpus);
325 for (i = 0; i <= mp_maxid; i++) {
328 sapic_id = IA64_LID_GET_SAPIC_ID(pc->pc_md.lid);
329 printf("cpu%d: ACPI Id=%x, SAPIC Id=%x, SAPIC Eid=%x",
330 i, pc->pc_acpi_id, SAPIC_ID_GET_ID(sapic_id),
331 SAPIC_ID_GET_EID(sapic_id));
343 struct ia64_sal_result result;
344 struct ia64_fdesc *fd;
349 state = ia64_tpa((uintptr_t)&ia64_ap_state);
350 fd = (struct ia64_fdesc *) os_boot_rendez;
351 result = ia64_sal_entry(SAL_SET_VECTORS, SAL_OS_BOOT_RENDEZ,
352 ia64_tpa(fd->func), state, 0, 0, 0, 0);
354 ia64_ap_state.as_pgtbl_pte = PTE_PRESENT | PTE_MA_WB |
355 PTE_ACCESSED | PTE_DIRTY | PTE_PL_KERN | PTE_AR_RW |
356 (bootinfo->bi_pbvm_pgtbl & PTE_PPN_MASK);
357 ia64_ap_state.as_pgtbl_itir = sz2shft(bootinfo->bi_pbvm_pgtblsz) << 2;
358 ia64_ap_state.as_text_va = IA64_PBVM_BASE;
359 ia64_ap_state.as_text_pte = PTE_PRESENT | PTE_MA_WB |
360 PTE_ACCESSED | PTE_DIRTY | PTE_PL_KERN | PTE_AR_RX |
361 (ia64_tpa(IA64_PBVM_BASE) & PTE_PPN_MASK);
362 ia64_ap_state.as_text_itir = bootinfo->bi_text_mapped << 2;
363 ia64_ap_state.as_data_va = (uintptr_t)bdata;
364 ia64_ap_state.as_data_pte = PTE_PRESENT | PTE_MA_WB |
365 PTE_ACCESSED | PTE_DIRTY | PTE_PL_KERN | PTE_AR_RW |
366 (ia64_tpa((uintptr_t)bdata) & PTE_PPN_MASK);
367 ia64_ap_state.as_data_itir = bootinfo->bi_data_mapped << 2;
369 /* Keep 'em spinning until we unleash them... */
370 ia64_ap_state.as_spin = 1;
372 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
373 pc->pc_md.current_pmap = kernel_pmap;
374 /* The BSP is obviously running already. */
375 if (pc->pc_cpuid == 0) {
380 ia64_ap_state.as_pcpu = pc;
381 pc->pc_md.vhpt = pmap_alloc_vhpt();
382 if (pc->pc_md.vhpt == 0) {
383 printf("SMP: WARNING: unable to allocate VHPT"
384 " for cpu%d", pc->pc_cpuid);
388 stp = malloc(KSTACK_PAGES * PAGE_SIZE, M_SMP, M_WAITOK);
389 ia64_ap_state.as_kstack = stp;
390 ia64_ap_state.as_kstack_top = stp + KSTACK_PAGES * PAGE_SIZE;
392 ia64_ap_state.as_trace = 0;
393 ia64_ap_state.as_delay = 2000;
394 ia64_ap_state.as_awake = 0;
397 printf("SMP: waking up cpu%d\n", pc->pc_cpuid);
399 /* Here she goes... */
400 ipi_send(pc, ia64_ipi_wakeup);
403 } while (--ia64_ap_state.as_delay > 0);
405 pc->pc_md.awake = ia64_ap_state.as_awake;
407 if (!ia64_ap_state.as_awake) {
408 printf("SMP: WARNING: cpu%d did not wake up (code "
409 "%#lx)\n", pc->pc_cpuid,
410 ia64_ap_state.as_trace - state);
416 cpu_mp_unleash(void *dummy)
424 /* Allocate XIVs for IPIs */
425 ia64_ipi_ast = ia64_xiv_alloc(PI_DULL, IA64_XIV_IPI, ia64_ih_ast);
426 ia64_ipi_hardclock = ia64_xiv_alloc(PI_REALTIME, IA64_XIV_IPI,
428 ia64_ipi_highfp = ia64_xiv_alloc(PI_AV, IA64_XIV_IPI, ia64_ih_highfp);
429 ia64_ipi_preempt = ia64_xiv_alloc(PI_SOFT, IA64_XIV_IPI,
431 ia64_ipi_rndzvs = ia64_xiv_alloc(PI_AV, IA64_XIV_IPI, ia64_ih_rndzvs);
432 ia64_ipi_stop = ia64_xiv_alloc(PI_REALTIME, IA64_XIV_IPI, ia64_ih_stop);
434 /* Reserve the NMI vector for IPI_STOP_HARD if possible */
435 ia64_ipi_nmi = (ia64_xiv_reserve(2, IA64_XIV_IPI, ia64_ih_stop) != 0)
436 ? ia64_ipi_stop : 0x400; /* DM=NMI, Vector=n/a */
440 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
442 if (pc->pc_md.awake) {
443 kproc_create(ia64_store_mca_state, pc, NULL, 0, 0,
444 "mca %u", pc->pc_cpuid);
449 ia64_ap_state.as_awake = 1;
450 ia64_ap_state.as_spin = 0;
452 while (ia64_ap_state.as_awake != smp_cpus)
455 if (smp_cpus != cpus || cpus != mp_ncpus) {
456 printf("SMP: %d CPUs found; %d CPUs usable; %d CPUs woken\n",
457 mp_ncpus, cpus, smp_cpus);
464 * Now that all CPUs are up and running, bind interrupts to each of
469 SYSINIT(start_aps, SI_SUB_KICK_SCHEDULER, SI_ORDER_ANY, cpu_mp_unleash, NULL);
472 * send an IPI to a set of cpus.
475 ipi_selected(cpuset_t cpus, int ipi)
479 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
480 if (CPU_ISSET(pc->pc_cpuid, &cpus))
486 * send an IPI to a specific CPU.
489 ipi_cpu(int cpu, u_int ipi)
492 ipi_send(cpuid_to_pcpu[cpu], ipi);
496 * send an IPI to all CPUs EXCEPT myself.
499 ipi_all_but_self(int ipi)
503 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
510 * Send an IPI to the specified processor.
513 ipi_send(struct pcpu *cpu, int xiv)
517 KASSERT(xiv != 0, ("ipi_send"));
519 sapic_id = IA64_LID_GET_SAPIC_ID(cpu->pc_md.lid);
522 ia64_st8(&(ia64_pib->ib_ipi[sapic_id][0]), xiv);
524 CTR3(KTR_SMP, "ipi_send(%p, %d): cpuid=%d", cpu, xiv, PCPU_GET(cpuid));