2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Derived from uart_dev_ns8250.c
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
36 * 1. Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * 2. Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in the
40 * documentation and/or other materials provided with the distribution.
42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
43 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
44 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
45 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
46 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
47 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
48 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
49 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
50 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
51 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 #include <sys/cdefs.h>
58 __FBSDID("$FreeBSD$");
60 #include <sys/param.h>
61 #include <sys/systm.h>
64 #include <machine/bus.h>
65 #include <machine/pcpu.h>
67 #include <dev/uart/uart.h>
68 #include <dev/uart/uart_cpu.h>
69 #include <dev/uart/uart_bus.h>
71 #include <dev/ic/ns16550.h>
73 #include <mips/cavium/octeon_pcmap_regs.h>
75 #include <contrib/octeon-sdk/cvmx.h>
80 * Clear pending interrupts. THRE is cleared by reading IIR. Data
81 * that may have been received gets lost here.
84 oct16550_clrint (struct uart_bas *bas)
88 iir = uart_getreg(bas, REG_IIR);
89 while ((iir & IIR_NOPEND) == 0) {
92 (void)uart_getreg(bas, REG_LSR);
93 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
94 (void)uart_getreg(bas, REG_DATA);
95 else if (iir == IIR_MLSC)
96 (void)uart_getreg(bas, REG_MSR);
97 else if (iir == IIR_BUSY)
98 (void) uart_getreg(bas, REG_USR);
100 iir = uart_getreg(bas, REG_IIR);
104 static int delay_changed = 1;
107 oct16550_delay (struct uart_bas *bas)
111 static int delay = 0;
113 if (!delay_changed) return delay;
115 lcr = uart_getreg(bas, REG_LCR);
116 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
118 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
120 uart_setreg(bas, REG_LCR, lcr);
124 return 10; /* return an approx delay value */
126 /* 1/10th the time to transmit 1 character (estimate). */
128 return (16000000 * divisor / bas->rclk);
129 return (16000 * divisor / (bas->rclk / 1000));
134 oct16550_divisor (int rclk, int baudrate)
136 int actual_baud, divisor;
142 divisor = (rclk / (baudrate << 3) + 1) >> 1;
143 if (divisor == 0 || divisor >= 65536)
145 actual_baud = rclk / (divisor << 4);
147 /* 10 times error in percent: */
148 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
150 /* 3.0% maximum error tolerance: */
151 if (error < -30 || error > 30)
158 oct16550_drain (struct uart_bas *bas, int what)
162 delay = oct16550_delay(bas);
164 if (what & UART_DRAIN_TRANSMITTER) {
166 * Pick an arbitrary high limit to avoid getting stuck in
167 * an infinite loop when the hardware is broken. Make the
168 * limit high enough to handle large FIFOs.
170 limit = 10*10*10*1024;
171 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
174 /* printf("oct16550: transmitter appears stuck... "); */
179 if (what & UART_DRAIN_RECEIVER) {
181 * Pick an arbitrary high limit to avoid getting stuck in
182 * an infinite loop when the hardware is broken. Make the
183 * limit high enough to handle large FIFOs and integrated
184 * UARTs. The HP rx2600 for example has 3 UARTs on the
185 * management board that tend to get a lot of data send
186 * to it when the UART is first activated.
189 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
190 (void)uart_getreg(bas, REG_DATA);
195 /* printf("oct16550: receiver appears broken... "); */
204 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
205 * drained. WARNING: this function clobbers the FIFO setting!
208 oct16550_flush (struct uart_bas *bas, int what)
213 if (what & UART_FLUSH_TRANSMITTER)
215 if (what & UART_FLUSH_RECEIVER)
217 uart_setreg(bas, REG_FCR, fcr);
222 oct16550_param (struct uart_bas *bas, int baudrate, int databits, int stopbits,
231 else if (databits == 7)
233 else if (databits == 6)
243 divisor = oct16550_divisor(bas->rclk, baudrate);
246 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
248 uart_setreg(bas, REG_DLL, divisor & 0xff);
249 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
254 /* Set LCR and clear DLAB. */
255 uart_setreg(bas, REG_LCR, lcr);
261 * Low-level UART interface.
263 static int oct16550_probe(struct uart_bas *bas);
264 static void oct16550_init(struct uart_bas *bas, int, int, int, int);
265 static void oct16550_term(struct uart_bas *bas);
266 static void oct16550_putc(struct uart_bas *bas, int);
267 static int oct16550_rxready(struct uart_bas *bas);
268 static int oct16550_getc(struct uart_bas *bas, struct mtx *);
270 struct uart_ops uart_oct16550_ops = {
271 .probe = oct16550_probe,
272 .init = oct16550_init,
273 .term = oct16550_term,
274 .putc = oct16550_putc,
275 .rxready = oct16550_rxready,
276 .getc = oct16550_getc,
280 oct16550_probe (struct uart_bas *bas)
284 /* Check known 0 bits that don't depend on DLAB. */
285 val = uart_getreg(bas, REG_IIR);
288 val = uart_getreg(bas, REG_MCR);
291 val = uart_getreg(bas, REG_USR);
298 oct16550_init (struct uart_bas *bas, int baudrate, int databits, int stopbits,
303 oct16550_param(bas, baudrate, databits, stopbits, parity);
305 /* Disable all interrupt sources. */
306 ier = uart_getreg(bas, REG_IER) & 0x0;
307 uart_setreg(bas, REG_IER, ier);
310 /* Disable the FIFO (if present). */
311 // uart_setreg(bas, REG_FCR, 0);
315 uart_setreg(bas, REG_MCR, MCR_RTS | MCR_DTR);
318 oct16550_clrint(bas);
322 oct16550_term (struct uart_bas *bas)
325 /* Clear RTS & DTR. */
326 uart_setreg(bas, REG_MCR, 0);
330 static inline void oct16550_wait_txhr_empty (struct uart_bas *bas, int limit, int delay)
332 while (((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) &&
333 ((uart_getreg(bas, REG_USR) & USR_TXFIFO_NOTFULL) == 0))
338 oct16550_putc (struct uart_bas *bas, int c)
342 /* 1/10th the time to transmit 1 character (estimate). */
343 delay = oct16550_delay(bas);
344 oct16550_wait_txhr_empty(bas, 100, delay);
345 uart_setreg(bas, REG_DATA, c);
347 oct16550_wait_txhr_empty(bas, 100, delay);
351 oct16550_rxready (struct uart_bas *bas)
354 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
358 oct16550_getc (struct uart_bas *bas, struct mtx *hwmtx)
364 /* 1/10th the time to transmit 1 character (estimate). */
365 delay = oct16550_delay(bas);
367 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
373 c = uart_getreg(bas, REG_DATA);
381 * High-level UART interface.
383 struct oct16550_softc {
384 struct uart_softc base;
390 static int oct16550_bus_attach(struct uart_softc *);
391 static int oct16550_bus_detach(struct uart_softc *);
392 static int oct16550_bus_flush(struct uart_softc *, int);
393 static int oct16550_bus_getsig(struct uart_softc *);
394 static int oct16550_bus_ioctl(struct uart_softc *, int, intptr_t);
395 static int oct16550_bus_ipend(struct uart_softc *);
396 static int oct16550_bus_param(struct uart_softc *, int, int, int, int);
397 static int oct16550_bus_probe(struct uart_softc *);
398 static int oct16550_bus_receive(struct uart_softc *);
399 static int oct16550_bus_setsig(struct uart_softc *, int);
400 static int oct16550_bus_transmit(struct uart_softc *);
402 static kobj_method_t oct16550_methods[] = {
403 KOBJMETHOD(uart_attach, oct16550_bus_attach),
404 KOBJMETHOD(uart_detach, oct16550_bus_detach),
405 KOBJMETHOD(uart_flush, oct16550_bus_flush),
406 KOBJMETHOD(uart_getsig, oct16550_bus_getsig),
407 KOBJMETHOD(uart_ioctl, oct16550_bus_ioctl),
408 KOBJMETHOD(uart_ipend, oct16550_bus_ipend),
409 KOBJMETHOD(uart_param, oct16550_bus_param),
410 KOBJMETHOD(uart_probe, oct16550_bus_probe),
411 KOBJMETHOD(uart_receive, oct16550_bus_receive),
412 KOBJMETHOD(uart_setsig, oct16550_bus_setsig),
413 KOBJMETHOD(uart_transmit, oct16550_bus_transmit),
417 struct uart_class uart_oct16550_class = {
420 sizeof(struct oct16550_softc),
421 .uc_ops = &uart_oct16550_ops,
426 #define SIGCHG(c, i, s, d) \
428 i |= (i & s) ? s : s | d; \
430 i = (i & s) ? (i & ~s) | d : i; \
434 oct16550_bus_attach (struct uart_softc *sc)
436 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
437 struct uart_bas *bas;
440 unit = device_get_unit(sc->sc_dev);
443 oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
444 oct16550->mcr = uart_getreg(bas, REG_MCR);
445 oct16550->fcr = FCR_ENABLE | FCR_RX_HIGH;
446 uart_setreg(bas, REG_FCR, oct16550->fcr);
448 oct16550_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
450 if (oct16550->mcr & MCR_DTR)
451 sc->sc_hwsig |= SER_DTR;
452 if (oct16550->mcr & MCR_RTS)
453 sc->sc_hwsig |= SER_RTS;
454 oct16550_bus_getsig(sc);
456 oct16550_clrint(bas);
457 oct16550->ier = uart_getreg(bas, REG_IER) & 0xf0;
458 oct16550->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY;
459 uart_setreg(bas, REG_IER, oct16550->ier);
466 oct16550_bus_detach (struct uart_softc *sc)
468 struct uart_bas *bas;
472 ier = uart_getreg(bas, REG_IER) & 0xf0;
473 uart_setreg(bas, REG_IER, ier);
475 oct16550_clrint(bas);
480 oct16550_bus_flush (struct uart_softc *sc, int what)
482 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
483 struct uart_bas *bas;
487 uart_lock(sc->sc_hwmtx);
488 if (sc->sc_rxfifosz > 1) {
489 oct16550_flush(bas, what);
490 uart_setreg(bas, REG_FCR, oct16550->fcr);
494 error = oct16550_drain(bas, what);
495 uart_unlock(sc->sc_hwmtx);
500 oct16550_bus_getsig (struct uart_softc *sc)
502 uint32_t new, old, sig;
508 uart_lock(sc->sc_hwmtx);
509 msr = uart_getreg(&sc->sc_bas, REG_MSR);
510 uart_unlock(sc->sc_hwmtx);
511 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
512 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
513 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
514 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
515 new = sig & ~SER_MASK_DELTA;
516 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
521 oct16550_bus_ioctl (struct uart_softc *sc, int request, intptr_t data)
523 struct uart_bas *bas;
524 int baudrate, divisor, error;
529 uart_lock(sc->sc_hwmtx);
531 case UART_IOCTL_BREAK:
532 lcr = uart_getreg(bas, REG_LCR);
537 uart_setreg(bas, REG_LCR, lcr);
540 case UART_IOCTL_IFLOW:
541 lcr = uart_getreg(bas, REG_LCR);
543 uart_setreg(bas, REG_LCR, 0xbf);
545 efr = uart_getreg(bas, REG_EFR);
550 uart_setreg(bas, REG_EFR, efr);
552 uart_setreg(bas, REG_LCR, lcr);
555 case UART_IOCTL_OFLOW:
556 lcr = uart_getreg(bas, REG_LCR);
558 uart_setreg(bas, REG_LCR, 0xbf);
560 efr = uart_getreg(bas, REG_EFR);
565 uart_setreg(bas, REG_EFR, efr);
567 uart_setreg(bas, REG_LCR, lcr);
570 case UART_IOCTL_BAUD:
571 lcr = uart_getreg(bas, REG_LCR);
572 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
574 divisor = uart_getreg(bas, REG_DLL) |
575 (uart_getreg(bas, REG_DLH) << 8);
577 uart_setreg(bas, REG_LCR, lcr);
579 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
582 *(int*)data = baudrate;
590 uart_unlock(sc->sc_hwmtx);
596 oct16550_bus_ipend(struct uart_softc *sc)
598 struct uart_bas *bas;
603 uart_lock(sc->sc_hwmtx);
605 iir = uart_getreg(bas, REG_IIR) & IIR_IMASK;
606 if (iir != IIR_NOPEND) {
608 if (iir == IIR_RLS) {
609 lsr = uart_getreg(bas, REG_LSR);
611 ipend |= SER_INT_OVERRUN;
613 ipend |= SER_INT_BREAK;
615 ipend |= SER_INT_RXREADY;
617 } else if (iir == IIR_RXRDY) {
618 ipend |= SER_INT_RXREADY;
620 } else if (iir == IIR_RXTOUT) {
621 ipend |= SER_INT_RXREADY;
623 } else if (iir == IIR_TXRDY) {
624 ipend |= SER_INT_TXIDLE;
626 } else if (iir == IIR_MLSC) {
627 ipend |= SER_INT_SIGCHG;
629 } else if (iir == IIR_BUSY) {
630 (void) uart_getreg(bas, REG_USR);
633 uart_unlock(sc->sc_hwmtx);
639 oct16550_bus_param (struct uart_softc *sc, int baudrate, int databits,
640 int stopbits, int parity)
642 struct uart_bas *bas;
646 uart_lock(sc->sc_hwmtx);
647 error = oct16550_param(bas, baudrate, databits, stopbits, parity);
648 uart_unlock(sc->sc_hwmtx);
653 oct16550_bus_probe (struct uart_softc *sc)
655 struct uart_bas *bas;
659 bas->rclk = uart_oct16550_class.uc_rclk = cvmx_clock_get_rate(CVMX_CLOCK_SCLK);
661 error = oct16550_probe(bas);
666 uart_setreg(bas, REG_MCR, (MCR_DTR | MCR_RTS));
669 * Enable FIFOs. And check that the UART has them. If not, we're
670 * done. Since this is the first time we enable the FIFOs, we reset
673 oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
674 #define ENABLE_OCTEON_FIFO 1
675 #ifdef ENABLE_OCTEON_FIFO
676 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
680 oct16550_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
682 if (device_get_unit(sc->sc_dev)) {
683 device_set_desc(sc->sc_dev, "Octeon-16550 channel 1");
685 device_set_desc(sc->sc_dev, "Octeon-16550 channel 0");
687 #ifdef ENABLE_OCTEON_FIFO
688 sc->sc_rxfifosz = 64;
689 sc->sc_txfifosz = 64;
698 * XXX there are some issues related to hardware flow control and
699 * it's likely that uart(4) is the cause. This basicly needs more
700 * investigation, but we avoid using for hardware flow control
703 /* 16650s or higher have automatic flow control. */
704 if (sc->sc_rxfifosz > 16) {
714 oct16550_bus_receive (struct uart_softc *sc)
716 struct uart_bas *bas;
721 uart_lock(sc->sc_hwmtx);
722 lsr = uart_getreg(bas, REG_LSR);
724 while (lsr & LSR_RXRDY) {
725 if (uart_rx_full(sc)) {
726 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
729 xc = uart_getreg(bas, REG_DATA);
731 xc |= UART_STAT_FRAMERR;
733 xc |= UART_STAT_PARERR;
735 lsr = uart_getreg(bas, REG_LSR);
737 /* Discard everything left in the Rx FIFO. */
739 * First do a dummy read/discard anyway, in case the UART was lying to us.
740 * This problem was seen on board, when IIR said RBR, but LSR said no RXRDY
741 * Results in a stuck ipend loop.
743 (void)uart_getreg(bas, REG_DATA);
744 while (lsr & LSR_RXRDY) {
745 (void)uart_getreg(bas, REG_DATA);
747 lsr = uart_getreg(bas, REG_LSR);
749 uart_unlock(sc->sc_hwmtx);
754 oct16550_bus_setsig (struct uart_softc *sc, int sig)
756 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
757 struct uart_bas *bas;
764 if (sig & SER_DDTR) {
765 SIGCHG(sig & SER_DTR, new, SER_DTR,
768 if (sig & SER_DRTS) {
769 SIGCHG(sig & SER_RTS, new, SER_RTS,
772 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
773 uart_lock(sc->sc_hwmtx);
774 oct16550->mcr &= ~(MCR_DTR|MCR_RTS);
776 oct16550->mcr |= MCR_DTR;
778 oct16550->mcr |= MCR_RTS;
779 uart_setreg(bas, REG_MCR, oct16550->mcr);
781 uart_unlock(sc->sc_hwmtx);
786 oct16550_bus_transmit (struct uart_softc *sc)
788 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
789 struct uart_bas *bas;
793 uart_lock(sc->sc_hwmtx);
794 #ifdef NO_UART_INTERRUPTS
795 for (i = 0; i < sc->sc_txdatasz; i++) {
796 oct16550_putc(bas, sc->sc_txbuf[i]);
800 oct16550_wait_txhr_empty(bas, 100, oct16550_delay(bas));
801 uart_setreg(bas, REG_IER, oct16550->ier | IER_ETXRDY);
804 for (i = 0; i < sc->sc_txdatasz; i++) {
805 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
810 uart_unlock(sc->sc_hwmtx);