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30 #ifndef __NLM_UCORE_H__
31 #define __NLM_UCORE_H__
33 /* Microcode registers */
34 #define UCORE_OUTBUF_DONE 0x8000
35 #define UCORE_RX_PKT_RDY 0x8004
36 #define UCORE_RX_PKT_INFO 0x8008
37 #define UCORE_CAM0 0x800c
38 #define UCORE_CAM1 0x8010
39 #define UCORE_CAM2 0x8014
40 #define UCORE_CAM3 0x8018
41 #define UCORE_CAM_RESULT 0x801c
42 #define UCORE_CSUMINFO 0x8020
43 #define UCORE_CRCINFO 0x8024
44 #define UCORE_CRCPOS 0x8028
45 #define UCORE_FR_FIFOEMPTY 0x802c
46 #define UCORE_PKT_DISTR 0x8030
48 #define PACKET_MEMORY 0xFFE00
49 #define PACKET_DATA_OFFSET 64
50 #define SHARED_SCRATCH_MEM 0x18000
52 /* Distribution mode */
53 #define VAL_PDM(x) (((x) & 0x7) << 0)
55 /* Dest distribution or distribution list */
56 #define VAL_DEST(x) (((x) & 0x3ff) << 8)
57 #define VAL_PDL(x) (((x) & 0xf) << 4)
59 /*output buffer done*/
60 #define VAL_FSV(x) (x << 19)
61 #define VAL_FFS(x) (x << 14)
63 #define FWD_DEST_ONLY 1
64 #define FWD_ENQ_DIST_VEC 2
65 #define FWD_ENQ_DEST 3
66 #define FWD_DIST_VEC 4
67 #define FWD_ENQ_DIST_VEC_SER 6
68 #define FWD_ENQ_DEST_SER 7
70 #define USE_HASH_DST (1 << 20)
72 static __inline unsigned int
73 nlm_read_ucore_reg(int reg)
75 volatile unsigned int *addr = (volatile void *)reg;
81 nlm_write_ucore_reg(int reg, unsigned int val)
83 volatile unsigned int *addr = (volatile void *)reg;
88 #define NLM_DEFINE_UCORE(name, reg) \
89 static __inline unsigned int \
90 nlm_read_ucore_##name(void) \
92 return nlm_read_ucore_reg(reg); \
95 static __inline void \
96 nlm_write_ucore_##name(unsigned int v) \
98 nlm_write_ucore_reg(reg, v); \
102 NLM_DEFINE_UCORE(obufdone, UCORE_OUTBUF_DONE);
103 NLM_DEFINE_UCORE(rxpktrdy, UCORE_RX_PKT_RDY);
104 NLM_DEFINE_UCORE(rxpktinfo, UCORE_RX_PKT_INFO);
105 NLM_DEFINE_UCORE(cam0, UCORE_CAM0);
106 NLM_DEFINE_UCORE(cam1, UCORE_CAM1);
107 NLM_DEFINE_UCORE(cam2, UCORE_CAM2);
108 NLM_DEFINE_UCORE(cam3, UCORE_CAM3);
109 NLM_DEFINE_UCORE(camresult, UCORE_CAM_RESULT);
110 NLM_DEFINE_UCORE(csuminfo, UCORE_CSUMINFO);
111 NLM_DEFINE_UCORE(crcinfo, UCORE_CRCINFO);
112 NLM_DEFINE_UCORE(crcpos, UCORE_CRCPOS);
113 NLM_DEFINE_UCORE(freefifo_empty, UCORE_FR_FIFOEMPTY);
114 NLM_DEFINE_UCORE(pktdistr, UCORE_PKT_DISTR);
117 * l3cachelines - number of cache lines to allocate into l3
118 * fsv - 0 : use interface-id for selecting the free fifo pool
119 * 1 : use free fifo pool selected by FFS field
120 * ffs - selects which free fifo pool to use to take a free fifo
121 * prepad_en - If this field is set to 1, part or all of the
122 * 64 byte prepad seen by micro engines, is written
123 * infront of every packet.
124 * prepad_ovride - If this field is 1, the ucore system uses
125 * prepad configuration defined in this register,
126 * 0 means that it uses the configuration defined
127 * in NAE RX_CONFIG register
128 * prepad_size - number of 16 byte words in the 64-byte prepad
129 * seen by micro engines and dma'ed to memory as
130 * pkt prepad. This field is meaningful only if
131 * prepad_en and prepad_ovride is set.
136 * prepad[0-3]: writing 0 to this means that the 1st 16 byte offset
137 * of prepad in micro engine, gets setup as prepad0/1/2/3.
139 * 1 : means 2nd 16 byte chunk in prepad0/1/2/3
140 * 2 : means 3rd 16 byte chunk in prepad0/1/2/3
141 * 3 : means 4rth 16 byte chunk in prepad0/1/2/3
142 * pkt_discard - packet will be discarded if this is set to 1
143 * rd5 - value (single bit) to be inserted in bit 5, the unclassified
144 * pkt bit of receive descriptor. If this bit is set, HPRE bit
145 * should also be set in ucore_rxpktready register
147 static __inline__ void
148 nlm_ucore_pkt_done(int l3cachelines, int fsv, int ffs, int prepad_en,
149 int prepad_ovride, int prepad_size, int prepad0, int prepad1,
150 int prepad2, int prepad3, int pkt_discard, int rd5)
152 unsigned int val = 0;
154 val |= ((l3cachelines & 0xfff) << 20);
155 val |= ((fsv & 0x1) << 19);
156 val |= ((ffs & 0x1f) << 14);
157 val |= ((prepad_en & 0x1) << 3);
158 val |= ((prepad_ovride & 0x1) << 2);
159 val |= ((prepad_size & 0x3) << 12);
160 val |= ((prepad0 & 0x3) << 4);
161 val |= ((prepad1 & 0x3) << 6);
162 val |= ((prepad2 & 0x3) << 8);
163 val |= ((prepad3 & 0x3) << 10);
164 val |= ((pkt_discard & 0x1) << 1);
165 val |= ((rd5 & 0x1) << 0);
167 nlm_write_ucore_obufdone(val);
170 /* Get the class full vector field from POE.
171 * The POE maintains a threshold for each class.
172 * A bit in this field will be set corresponding to the class approaching
175 static __inline__ int
176 nlm_ucore_get_rxpkt_poeclassfullvec(unsigned int pktrdy)
178 return ((pktrdy >> 24) & 0xff);
181 /* This function returns 1 if the hardware parser extraction process
182 * resulted in an error. Else, returns 0.
184 static __inline__ int
185 nlm_ucore_get_rxpkt_hwparsererr(unsigned int pktrdy)
187 return ((pktrdy >> 23) & 0x1);
190 /* This function returns the context number assigned to incoming
193 static __inline__ int
194 nlm_ucore_get_rxpkt_context(unsigned int pktrdy)
196 return ((pktrdy >> 13) & 0x3ff);
199 /* this function returns the channel number of incoming packet,
200 * and applies only to interlaken.
202 static __inline__ int
203 nlm_ucore_get_rxpkt_channel(unsigned int pktrdy)
205 return ((pktrdy >> 5) & 0xff);
208 /* This function returns the interface number on which the pkt
211 static __inline__ int
212 nlm_ucore_get_rxpkt_interface(unsigned int pktrdy)
214 return (pktrdy & 0x1f);
217 /* This function returns 1 if end of packet (EOP) is set in
220 static __inline__ int
221 nlm_ucore_get_rxpkt_eop(unsigned int rxpkt_info)
223 return ((rxpkt_info >> 9) & 0x1);
226 /* This function returns packet length of received pkt */
227 static __inline__ int
228 nlm_ucore_get_rxpktlen(unsigned int rxpkt_info)
230 return (rxpkt_info & 0x1ff);
233 /* this function sets up the ucore TCAM keys. */
234 static __inline__ void
235 nlm_ucore_setup_camkey(unsigned int cam_key0, unsigned int cam_key1,
236 unsigned int cam_key2, unsigned int cam_key3)
238 nlm_write_ucore_cam0(cam_key0);
239 nlm_write_ucore_cam1(cam_key1);
240 nlm_write_ucore_cam2(cam_key2);
241 nlm_write_ucore_cam3(cam_key3);
244 /* This function checks if the cam result is valid or not.
245 * If valid, it returns the result, else it returns 0.
247 static __inline__ int
248 nlm_ucore_get_cam_result(unsigned int cam_result)
250 if (((cam_result >> 15) & 0x1) == 1) /* valid result */
251 return (cam_result & 0x3fff);
256 /* This function sets up the csum in ucore.
257 * iphdr_start - defines the start of ip header (to check - is this byte
259 * iphdr_len - This field is auto filled by h/w parser if zero, else
260 * the value defined will be used.
262 static __inline__ void
263 nlm_ucore_csum_setup(int iphdr_start, int iphdr_len)
265 unsigned int val = 0;
267 val |= ((iphdr_len & 0xff) << 8);
268 val |= (iphdr_len & 0xff);
269 nlm_write_ucore_csuminfo(val);
272 /* crcpos - position of crc in pkt. If crc position is within startcrc and
273 * endcrc, zero out these bytes in the packet before computing crc. This
274 * field is not needed for FCoE.
275 * cps - If 1, uses the polynomial in RX_CRC_POLY1 of NAE register.
276 * if 0, uses the polynomial in RX_CRC_POLY0 of NAE register.
277 * fcoe - If this is 1, crc calculation starts from 'startCRC' and the CRC
278 * engine ends calculation before the last byte.
279 * cbm - if 1, enables crc byte mirroring, where bits within a byte will get
280 * reversed (mirrored) during calculation of crc.
281 * cfi - If 1, performs a final inversion of crc before comarison is done during
283 * startcrc - This field is always required for both FCoE and SCTP crc.
284 * endcrc - This information needs to be setup only for SCTP. For FCoE this
285 * information is provided by hardware.
286 * valid - if set to 1, CRC status is placed into bit 2 of rx descriptor
287 * if set to 0, TCP checksum status is placed into bit 2 of rx descriptor
288 * keysize - defines the number of bytes in the pre-pad that contains the key
290 static __inline__ void
291 nlm_ucore_crc_setup(int crcpos, int cps, int cfi, int cbm, int fcoe,
292 int keysize, int valid, int startcrc, int endcrc)
294 unsigned int val = 0;
296 val |= ((cfi & 0x1) << 20);
297 val |= ((cbm & 0x1) << 19);
298 val |= ((fcoe & 0x1) << 18);
299 val |= ((cps & 0x1) << 16);
300 val |= (crcpos & 0xffff);
302 nlm_write_ucore_crcpos(val);
305 val |= ((keysize & 0x3f) << 25);
306 val |= ((valid & 0x1) << 24);
307 val |= ((endcrc & 0xffff) << 8);
308 val |= (startcrc & 0xff);
310 nlm_write_ucore_crcinfo(val);
313 /* This function returns a fifo empty vector, where each bit provides
314 * the status of a fifo pool, where if the pool is empty the bit gets
317 static __inline__ int
318 nlm_ucore_get_fifoempty(unsigned int fifoempty)
320 return (fifoempty & 0xfffff);
323 /* This function controls how POE will distribute the packet.
324 * pdm - is the packet distribution mode, where
325 * 0x0 - means packet distribution mode is not used
326 * 0x1 - means forwarding based on destination only (no enqueue)
327 * 0x2 - means forwarding based on FID and distr vector (enqueue)
328 * 0x3 - means forwarding based on dest and FID (enqueue)
329 * 0x4 - means forwarding based on distr vec (no enqueue)
330 * 0x6 - means forward based on FID (enqueue), distr vec and serial mode
331 * 0x7 - means forward based on FID (enqueue), dest and serial mode
332 * mc3 - If 1, then the 3 most significant bits of distribution list are taken
333 * from context->class_table
334 * pdl - poe distribution list
335 * dest - fixed destination setup
336 * hash - if 1, use hash based destination
338 static __inline__ void
339 nlm_ucore_setup_poepktdistr(int pdm, int mc3, int pdl, int dest, int hash)
341 unsigned int val = 0;
343 val |= ((hash & 0x1) << 20);
344 val |= ((dest & 0xfff) << 8);
345 val |= ((pdl & 0xf) << 4);
346 val |= ((mc3 & 0x1) << 3);
349 nlm_write_ucore_pktdistr(val);