2 * Copyright (c) 2003-2009 RMI Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of RMI Corporation, nor the names of its contributors,
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 /* #define MAC_SPLIT_MODE */
36 #define MAC_SPACING 0x400
37 #define XGMAC_SPACING 0x400
39 /* PE-MCXMAC register and bit field definitions */
40 #define R_MAC_CONFIG_1 0x00
41 #define O_MAC_CONFIG_1__srst 31
42 #define O_MAC_CONFIG_1__simr 30
43 #define O_MAC_CONFIG_1__hrrmc 18
44 #define W_MAC_CONFIG_1__hrtmc 2
45 #define O_MAC_CONFIG_1__hrrfn 16
46 #define W_MAC_CONFIG_1__hrtfn 2
47 #define O_MAC_CONFIG_1__intlb 8
48 #define O_MAC_CONFIG_1__rxfc 5
49 #define O_MAC_CONFIG_1__txfc 4
50 #define O_MAC_CONFIG_1__srxen 3
51 #define O_MAC_CONFIG_1__rxen 2
52 #define O_MAC_CONFIG_1__stxen 1
53 #define O_MAC_CONFIG_1__txen 0
54 #define R_MAC_CONFIG_2 0x01
55 #define O_MAC_CONFIG_2__prlen 12
56 #define W_MAC_CONFIG_2__prlen 4
57 #define O_MAC_CONFIG_2__speed 8
58 #define W_MAC_CONFIG_2__speed 2
59 #define O_MAC_CONFIG_2__hugen 5
60 #define O_MAC_CONFIG_2__flchk 4
61 #define O_MAC_CONFIG_2__crce 1
62 #define O_MAC_CONFIG_2__fulld 0
63 #define R_IPG_IFG 0x02
64 #define O_IPG_IFG__ipgr1 24
65 #define W_IPG_IFG__ipgr1 7
66 #define O_IPG_IFG__ipgr2 16
67 #define W_IPG_IFG__ipgr2 7
68 #define O_IPG_IFG__mifg 8
69 #define W_IPG_IFG__mifg 8
70 #define O_IPG_IFG__ipgt 0
71 #define W_IPG_IFG__ipgt 7
72 #define R_HALF_DUPLEX 0x03
73 #define O_HALF_DUPLEX__abebt 24
74 #define W_HALF_DUPLEX__abebt 4
75 #define O_HALF_DUPLEX__abebe 19
76 #define O_HALF_DUPLEX__bpnb 18
77 #define O_HALF_DUPLEX__nobo 17
78 #define O_HALF_DUPLEX__edxsdfr 16
79 #define O_HALF_DUPLEX__retry 12
80 #define W_HALF_DUPLEX__retry 4
81 #define O_HALF_DUPLEX__lcol 0
82 #define W_HALF_DUPLEX__lcol 10
83 #define R_MAXIMUM_FRAME_LENGTH 0x04
84 #define O_MAXIMUM_FRAME_LENGTH__maxf 0
85 #define W_MAXIMUM_FRAME_LENGTH__maxf 16
87 #define O_TEST__mbof 3
88 #define O_TEST__rthdf 2
89 #define O_TEST__tpause 1
90 #define O_TEST__sstct 0
91 #define R_MII_MGMT_CONFIG 0x08
92 #define O_MII_MGMT_CONFIG__scinc 5
93 #define O_MII_MGMT_CONFIG__spre 4
94 #define O_MII_MGMT_CONFIG__clks 3
95 #define W_MII_MGMT_CONFIG__clks 3
96 #define R_MII_MGMT_COMMAND 0x09
97 #define O_MII_MGMT_COMMAND__scan 1
98 #define O_MII_MGMT_COMMAND__rstat 0
99 #define R_MII_MGMT_ADDRESS 0x0A
100 #define O_MII_MGMT_ADDRESS__fiad 8
101 #define W_MII_MGMT_ADDRESS__fiad 5
102 #define O_MII_MGMT_ADDRESS__fgad 5
103 #define W_MII_MGMT_ADDRESS__fgad 0
104 #define R_MII_MGMT_WRITE_DATA 0x0B
105 #define O_MII_MGMT_WRITE_DATA__ctld 0
106 #define W_MII_MGMT_WRITE_DATA__ctld 16
107 #define R_MII_MGMT_STATUS 0x0C
108 #define R_MII_MGMT_INDICATORS 0x0D
109 #define O_MII_MGMT_INDICATORS__nvalid 2
110 #define O_MII_MGMT_INDICATORS__scan 1
111 #define O_MII_MGMT_INDICATORS__busy 0
112 #define R_INTERFACE_CONTROL 0x0E
113 #define O_INTERFACE_CONTROL__hrstint 31
114 #define O_INTERFACE_CONTROL__tbimode 27
115 #define O_INTERFACE_CONTROL__ghdmode 26
116 #define O_INTERFACE_CONTROL__lhdmode 25
117 #define O_INTERFACE_CONTROL__phymod 24
118 #define O_INTERFACE_CONTROL__hrrmi 23
119 #define O_INTERFACE_CONTROL__rspd 16
120 #define O_INTERFACE_CONTROL__hr100 15
121 #define O_INTERFACE_CONTROL__frcq 10
122 #define O_INTERFACE_CONTROL__nocfr 9
123 #define O_INTERFACE_CONTROL__dlfct 8
124 #define O_INTERFACE_CONTROL__enjab 0
125 #define R_INTERFACE_STATUS 0x0F
126 #define O_INTERFACE_STATUS__xsdfr 9
127 #define O_INTERFACE_STATUS__ssrr 8
128 #define W_INTERFACE_STATUS__ssrr 5
129 #define O_INTERFACE_STATUS__miilf 3
130 #define O_INTERFACE_STATUS__locar 2
131 #define O_INTERFACE_STATUS__sqerr 1
132 #define O_INTERFACE_STATUS__jabber 0
133 #define R_STATION_ADDRESS_LS 0x10
134 #define R_STATION_ADDRESS_MS 0x11
136 /* A-XGMAC register and bit field definitions */
137 #define R_XGMAC_CONFIG_0 0x00
138 #define O_XGMAC_CONFIG_0__hstmacrst 31
139 #define O_XGMAC_CONFIG_0__hstrstrctl 23
140 #define O_XGMAC_CONFIG_0__hstrstrfn 22
141 #define O_XGMAC_CONFIG_0__hstrsttctl 18
142 #define O_XGMAC_CONFIG_0__hstrsttfn 17
143 #define O_XGMAC_CONFIG_0__hstrstmiim 16
144 #define O_XGMAC_CONFIG_0__hstloopback 8
145 #define R_XGMAC_CONFIG_1 0x01
146 #define O_XGMAC_CONFIG_1__hsttctlen 31
147 #define O_XGMAC_CONFIG_1__hsttfen 30
148 #define O_XGMAC_CONFIG_1__hstrctlen 29
149 #define O_XGMAC_CONFIG_1__hstrfen 28
150 #define O_XGMAC_CONFIG_1__tfen 26
151 #define O_XGMAC_CONFIG_1__rfen 24
152 #define O_XGMAC_CONFIG_1__hstrctlshrtp 12
153 #define O_XGMAC_CONFIG_1__hstdlyfcstx 10
154 #define W_XGMAC_CONFIG_1__hstdlyfcstx 2
155 #define O_XGMAC_CONFIG_1__hstdlyfcsrx 8
156 #define W_XGMAC_CONFIG_1__hstdlyfcsrx 2
157 #define O_XGMAC_CONFIG_1__hstppen 7
158 #define O_XGMAC_CONFIG_1__hstbytswp 6
159 #define O_XGMAC_CONFIG_1__hstdrplt64 5
160 #define O_XGMAC_CONFIG_1__hstprmscrx 4
161 #define O_XGMAC_CONFIG_1__hstlenchk 3
162 #define O_XGMAC_CONFIG_1__hstgenfcs 2
163 #define O_XGMAC_CONFIG_1__hstpadmode 0
164 #define W_XGMAC_CONFIG_1__hstpadmode 2
165 #define R_XGMAC_CONFIG_2 0x02
166 #define O_XGMAC_CONFIG_2__hsttctlfrcp 31
167 #define O_XGMAC_CONFIG_2__hstmlnkflth 27
168 #define O_XGMAC_CONFIG_2__hstalnkflth 26
169 #define O_XGMAC_CONFIG_2__rflnkflt 24
170 #define W_XGMAC_CONFIG_2__rflnkflt 2
171 #define O_XGMAC_CONFIG_2__hstipgextmod 16
172 #define W_XGMAC_CONFIG_2__hstipgextmod 5
173 #define O_XGMAC_CONFIG_2__hstrctlfrcp 15
174 #define O_XGMAC_CONFIG_2__hstipgexten 5
175 #define O_XGMAC_CONFIG_2__hstmipgext 0
176 #define W_XGMAC_CONFIG_2__hstmipgext 5
177 #define R_XGMAC_CONFIG_3 0x03
178 #define O_XGMAC_CONFIG_3__hstfltrfrm 31
179 #define W_XGMAC_CONFIG_3__hstfltrfrm 16
180 #define O_XGMAC_CONFIG_3__hstfltrfrmdc 15
181 #define W_XGMAC_CONFIG_3__hstfltrfrmdc 16
182 #define R_XGMAC_STATION_ADDRESS_LS 0x04
183 #define O_XGMAC_STATION_ADDRESS_LS__hstmacadr0 0
184 #define W_XGMAC_STATION_ADDRESS_LS__hstmacadr0 32
185 #define R_XGMAC_STATION_ADDRESS_MS 0x05
186 #define R_XGMAC_MAX_FRAME_LEN 0x08
187 #define O_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 16
188 #define W_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 14
189 #define O_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 0
190 #define W_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 16
191 #define R_XGMAC_REV_LEVEL 0x0B
192 #define O_XGMAC_REV_LEVEL__revlvl 0
193 #define W_XGMAC_REV_LEVEL__revlvl 15
194 #define R_XGMAC_MIIM_COMMAND 0x10
195 #define O_XGMAC_MIIM_COMMAND__hstldcmd 3
196 #define O_XGMAC_MIIM_COMMAND__hstmiimcmd 0
197 #define W_XGMAC_MIIM_COMMAND__hstmiimcmd 3
198 #define R_XGMAC_MIIM_FILED 0x11
199 #define O_XGMAC_MIIM_FILED__hststfield 30
200 #define W_XGMAC_MIIM_FILED__hststfield 2
201 #define O_XGMAC_MIIM_FILED__hstopfield 28
202 #define W_XGMAC_MIIM_FILED__hstopfield 2
203 #define O_XGMAC_MIIM_FILED__hstphyadx 23
204 #define W_XGMAC_MIIM_FILED__hstphyadx 5
205 #define O_XGMAC_MIIM_FILED__hstregadx 18
206 #define W_XGMAC_MIIM_FILED__hstregadx 5
207 #define O_XGMAC_MIIM_FILED__hsttafield 16
208 #define W_XGMAC_MIIM_FILED__hsttafield 2
209 #define O_XGMAC_MIIM_FILED__miimrddat 0
210 #define W_XGMAC_MIIM_FILED__miimrddat 16
211 #define R_XGMAC_MIIM_CONFIG 0x12
212 #define O_XGMAC_MIIM_CONFIG__hstnopram 7
213 #define O_XGMAC_MIIM_CONFIG__hstclkdiv 0
214 #define W_XGMAC_MIIM_CONFIG__hstclkdiv 7
215 #define R_XGMAC_MIIM_LINK_FAIL_VECTOR 0x13
216 #define O_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 0
217 #define W_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 32
218 #define R_XGMAC_MIIM_INDICATOR 0x14
219 #define O_XGMAC_MIIM_INDICATOR__miimphylf 4
220 #define O_XGMAC_MIIM_INDICATOR__miimmoncplt 3
221 #define O_XGMAC_MIIM_INDICATOR__miimmonvld 2
222 #define O_XGMAC_MIIM_INDICATOR__miimmon 1
223 #define O_XGMAC_MIIM_INDICATOR__miimbusy 0
225 /* Glue logic register and bit field definitions */
226 #define R_MAC_ADDR0 0x50
227 #define R_MAC_ADDR1 0x52
228 #define R_MAC_ADDR2 0x54
229 #define R_MAC_ADDR3 0x56
230 #define R_MAC_ADDR_MASK2 0x58
231 #define R_MAC_ADDR_MASK3 0x5A
232 #define R_MAC_FILTER_CONFIG 0x5C
233 #define O_MAC_FILTER_CONFIG__BROADCAST_EN 10
234 #define O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN 9
235 #define O_MAC_FILTER_CONFIG__ALL_MCAST_EN 8
236 #define O_MAC_FILTER_CONFIG__ALL_UCAST_EN 7
237 #define O_MAC_FILTER_CONFIG__HASH_MCAST_EN 6
238 #define O_MAC_FILTER_CONFIG__HASH_UCAST_EN 5
239 #define O_MAC_FILTER_CONFIG__ADDR_MATCH_DISC 4
240 #define O_MAC_FILTER_CONFIG__MAC_ADDR3_VALID 3
241 #define O_MAC_FILTER_CONFIG__MAC_ADDR2_VALID 2
242 #define O_MAC_FILTER_CONFIG__MAC_ADDR1_VALID 1
243 #define O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID 0
244 #define R_HASH_TABLE_VECTOR 0x30
245 #define R_TX_CONTROL 0x0A0
246 #define O_TX_CONTROL__Tx15Halt 31
247 #define O_TX_CONTROL__Tx14Halt 30
248 #define O_TX_CONTROL__Tx13Halt 29
249 #define O_TX_CONTROL__Tx12Halt 28
250 #define O_TX_CONTROL__Tx11Halt 27
251 #define O_TX_CONTROL__Tx10Halt 26
252 #define O_TX_CONTROL__Tx9Halt 25
253 #define O_TX_CONTROL__Tx8Halt 24
254 #define O_TX_CONTROL__Tx7Halt 23
255 #define O_TX_CONTROL__Tx6Halt 22
256 #define O_TX_CONTROL__Tx5Halt 21
257 #define O_TX_CONTROL__Tx4Halt 20
258 #define O_TX_CONTROL__Tx3Halt 19
259 #define O_TX_CONTROL__Tx2Halt 18
260 #define O_TX_CONTROL__Tx1Halt 17
261 #define O_TX_CONTROL__Tx0Halt 16
262 #define O_TX_CONTROL__TxIdle 15
263 #define O_TX_CONTROL__TxEnable 14
264 #define O_TX_CONTROL__TxThreshold 0
265 #define W_TX_CONTROL__TxThreshold 14
266 #define R_RX_CONTROL 0x0A1
267 #define O_RX_CONTROL__RGMII 10
268 #define O_RX_CONTROL__RxHalt 1
269 #define O_RX_CONTROL__RxEnable 0
270 #define R_DESC_PACK_CTRL 0x0A2
271 #define O_DESC_PACK_CTRL__ByteOffset 17
272 #define W_DESC_PACK_CTRL__ByteOffset 3
273 #define O_DESC_PACK_CTRL__PrePadEnable 16
274 #define O_DESC_PACK_CTRL__MaxEntry 14
275 #define W_DESC_PACK_CTRL__MaxEntry 2
276 #define O_DESC_PACK_CTRL__RegularSize 0
277 #define W_DESC_PACK_CTRL__RegularSize 14
278 #define R_STATCTRL 0x0A3
279 #define O_STATCTRL__OverFlowEn 4
280 #define O_STATCTRL__GIG 3
281 #define O_STATCTRL__Sten 2
282 #define O_STATCTRL__ClrCnt 1
283 #define O_STATCTRL__AutoZ 0
284 #define R_L2ALLOCCTRL 0x0A4
285 #define O_L2ALLOCCTRL__TxL2Allocate 9
286 #define W_L2ALLOCCTRL__TxL2Allocate 9
287 #define O_L2ALLOCCTRL__RxL2Allocate 0
288 #define W_L2ALLOCCTRL__RxL2Allocate 9
289 #define R_INTMASK 0x0A5
290 #define O_INTMASK__Spi4TxError 28
291 #define O_INTMASK__Spi4RxError 27
292 #define O_INTMASK__RGMIIHalfDupCollision 27
293 #define O_INTMASK__Abort 26
294 #define O_INTMASK__Underrun 25
295 #define O_INTMASK__DiscardPacket 24
296 #define O_INTMASK__AsyncFifoFull 23
297 #define O_INTMASK__TagFull 22
298 #define O_INTMASK__Class3Full 21
299 #define O_INTMASK__C3EarlyFull 20
300 #define O_INTMASK__Class2Full 19
301 #define O_INTMASK__C2EarlyFull 18
302 #define O_INTMASK__Class1Full 17
303 #define O_INTMASK__C1EarlyFull 16
304 #define O_INTMASK__Class0Full 15
305 #define O_INTMASK__C0EarlyFull 14
306 #define O_INTMASK__RxDataFull 13
307 #define O_INTMASK__RxEarlyFull 12
308 #define O_INTMASK__RFreeEmpty 9
309 #define O_INTMASK__RFEarlyEmpty 8
310 #define O_INTMASK__P2PSpillEcc 7
311 #define O_INTMASK__FreeDescFull 5
312 #define O_INTMASK__FreeEarlyFull 4
313 #define O_INTMASK__TxFetchError 3
314 #define O_INTMASK__StatCarry 2
315 #define O_INTMASK__MDInt 1
316 #define O_INTMASK__TxIllegal 0
317 #define R_INTREG 0x0A6
318 #define O_INTREG__Spi4TxError 28
319 #define O_INTREG__Spi4RxError 27
320 #define O_INTREG__RGMIIHalfDupCollision 27
321 #define O_INTREG__Abort 26
322 #define O_INTREG__Underrun 25
323 #define O_INTREG__DiscardPacket 24
324 #define O_INTREG__AsyncFifoFull 23
325 #define O_INTREG__TagFull 22
326 #define O_INTREG__Class3Full 21
327 #define O_INTREG__C3EarlyFull 20
328 #define O_INTREG__Class2Full 19
329 #define O_INTREG__C2EarlyFull 18
330 #define O_INTREG__Class1Full 17
331 #define O_INTREG__C1EarlyFull 16
332 #define O_INTREG__Class0Full 15
333 #define O_INTREG__C0EarlyFull 14
334 #define O_INTREG__RxDataFull 13
335 #define O_INTREG__RxEarlyFull 12
336 #define O_INTREG__RFreeEmpty 9
337 #define O_INTREG__RFEarlyEmpty 8
338 #define O_INTREG__P2PSpillEcc 7
339 #define O_INTREG__FreeDescFull 5
340 #define O_INTREG__FreeEarlyFull 4
341 #define O_INTREG__TxFetchError 3
342 #define O_INTREG__StatCarry 2
343 #define O_INTREG__MDInt 1
344 #define O_INTREG__TxIllegal 0
345 #define R_TXRETRY 0x0A7
346 #define O_TXRETRY__CollisionRetry 6
347 #define O_TXRETRY__BusErrorRetry 5
348 #define O_TXRETRY__UnderRunRetry 4
349 #define O_TXRETRY__Retries 0
350 #define W_TXRETRY__Retries 4
351 #define R_CORECONTROL 0x0A8
352 #define O_CORECONTROL__ErrorThread 4
353 #define W_CORECONTROL__ErrorThread 7
354 #define O_CORECONTROL__Shutdown 2
355 #define O_CORECONTROL__Speed 0
356 #define W_CORECONTROL__Speed 2
357 #define R_BYTEOFFSET0 0x0A9
358 #define R_BYTEOFFSET1 0x0AA
359 #define R_L2TYPE_0 0x0F0
360 #define O_L2TYPE__ExtraHdrProtoSize 26
361 #define W_L2TYPE__ExtraHdrProtoSize 5
362 #define O_L2TYPE__ExtraHdrProtoOffset 20
363 #define W_L2TYPE__ExtraHdrProtoOffset 6
364 #define O_L2TYPE__ExtraHeaderSize 14
365 #define W_L2TYPE__ExtraHeaderSize 6
366 #define O_L2TYPE__ProtoOffset 8
367 #define W_L2TYPE__ProtoOffset 6
368 #define O_L2TYPE__L2HdrOffset 2
369 #define W_L2TYPE__L2HdrOffset 6
370 #define O_L2TYPE__L2Proto 0
371 #define W_L2TYPE__L2Proto 2
372 #define R_L2TYPE_1 0xF0
373 #define R_L2TYPE_2 0xF0
374 #define R_L2TYPE_3 0xF0
375 #define R_PARSERCONFIGREG 0x100
376 #define O_PARSERCONFIGREG__CRCHashPoly 8
377 #define W_PARSERCONFIGREG__CRCHashPoly 7
378 #define O_PARSERCONFIGREG__PrePadOffset 4
379 #define W_PARSERCONFIGREG__PrePadOffset 4
380 #define O_PARSERCONFIGREG__UseCAM 2
381 #define O_PARSERCONFIGREG__UseHASH 1
382 #define O_PARSERCONFIGREG__UseProto 0
383 #define R_L3CTABLE 0x140
384 #define O_L3CTABLE__Offset0 25
385 #define W_L3CTABLE__Offset0 7
386 #define O_L3CTABLE__Len0 21
387 #define W_L3CTABLE__Len0 4
388 #define O_L3CTABLE__Offset1 14
389 #define W_L3CTABLE__Offset1 7
390 #define O_L3CTABLE__Len1 10
391 #define W_L3CTABLE__Len1 4
392 #define O_L3CTABLE__Offset2 4
393 #define W_L3CTABLE__Offset2 6
394 #define O_L3CTABLE__Len2 0
395 #define W_L3CTABLE__Len2 4
396 #define O_L3CTABLE__L3HdrOffset 26
397 #define W_L3CTABLE__L3HdrOffset 6
398 #define O_L3CTABLE__L4ProtoOffset 20
399 #define W_L3CTABLE__L4ProtoOffset 6
400 #define O_L3CTABLE__IPChksumCompute 19
401 #define O_L3CTABLE__L4Classify 18
402 #define O_L3CTABLE__L2Proto 16
403 #define W_L3CTABLE__L2Proto 2
404 #define O_L3CTABLE__L3ProtoKey 0
405 #define W_L3CTABLE__L3ProtoKey 16
406 #define R_L4CTABLE 0x160
407 #define O_L4CTABLE__Offset0 21
408 #define W_L4CTABLE__Offset0 6
409 #define O_L4CTABLE__Len0 17
410 #define W_L4CTABLE__Len0 4
411 #define O_L4CTABLE__Offset1 11
412 #define W_L4CTABLE__Offset1 6
413 #define O_L4CTABLE__Len1 7
414 #define W_L4CTABLE__Len1 4
415 #define O_L4CTABLE__TCPChksumEnable 0
416 #define R_CAM4X128TABLE 0x172
417 #define O_CAM4X128TABLE__ClassId 7
418 #define W_CAM4X128TABLE__ClassId 2
419 #define O_CAM4X128TABLE__BucketId 1
420 #define W_CAM4X128TABLE__BucketId 6
421 #define O_CAM4X128TABLE__UseBucket 0
422 #define R_CAM4X128KEY 0x180
423 #define R_TRANSLATETABLE 0x1A0
424 #define R_DMACR0 0x200
425 #define O_DMACR0__Data0WrMaxCr 27
426 #define W_DMACR0__Data0WrMaxCr 3
427 #define O_DMACR0__Data0RdMaxCr 24
428 #define W_DMACR0__Data0RdMaxCr 3
429 #define O_DMACR0__Data1WrMaxCr 21
430 #define W_DMACR0__Data1WrMaxCr 3
431 #define O_DMACR0__Data1RdMaxCr 18
432 #define W_DMACR0__Data1RdMaxCr 3
433 #define O_DMACR0__Data2WrMaxCr 15
434 #define W_DMACR0__Data2WrMaxCr 3
435 #define O_DMACR0__Data2RdMaxCr 12
436 #define W_DMACR0__Data2RdMaxCr 3
437 #define O_DMACR0__Data3WrMaxCr 9
438 #define W_DMACR0__Data3WrMaxCr 3
439 #define O_DMACR0__Data3RdMaxCr 6
440 #define W_DMACR0__Data3RdMaxCr 3
441 #define O_DMACR0__Data4WrMaxCr 3
442 #define W_DMACR0__Data4WrMaxCr 3
443 #define O_DMACR0__Data4RdMaxCr 0
444 #define W_DMACR0__Data4RdMaxCr 3
445 #define R_DMACR1 0x201
446 #define O_DMACR1__Data5WrMaxCr 27
447 #define W_DMACR1__Data5WrMaxCr 3
448 #define O_DMACR1__Data5RdMaxCr 24
449 #define W_DMACR1__Data5RdMaxCr 3
450 #define O_DMACR1__Data6WrMaxCr 21
451 #define W_DMACR1__Data6WrMaxCr 3
452 #define O_DMACR1__Data6RdMaxCr 18
453 #define W_DMACR1__Data6RdMaxCr 3
454 #define O_DMACR1__Data7WrMaxCr 15
455 #define W_DMACR1__Data7WrMaxCr 3
456 #define O_DMACR1__Data7RdMaxCr 12
457 #define W_DMACR1__Data7RdMaxCr 3
458 #define O_DMACR1__Data8WrMaxCr 9
459 #define W_DMACR1__Data8WrMaxCr 3
460 #define O_DMACR1__Data8RdMaxCr 6
461 #define W_DMACR1__Data8RdMaxCr 3
462 #define O_DMACR1__Data9WrMaxCr 3
463 #define W_DMACR1__Data9WrMaxCr 3
464 #define O_DMACR1__Data9RdMaxCr 0
465 #define W_DMACR1__Data9RdMaxCr 3
466 #define R_DMACR2 0x202
467 #define O_DMACR2__Data10WrMaxCr 27
468 #define W_DMACR2__Data10WrMaxCr 3
469 #define O_DMACR2__Data10RdMaxCr 24
470 #define W_DMACR2__Data10RdMaxCr 3
471 #define O_DMACR2__Data11WrMaxCr 21
472 #define W_DMACR2__Data11WrMaxCr 3
473 #define O_DMACR2__Data11RdMaxCr 18
474 #define W_DMACR2__Data11RdMaxCr 3
475 #define O_DMACR2__Data12WrMaxCr 15
476 #define W_DMACR2__Data12WrMaxCr 3
477 #define O_DMACR2__Data12RdMaxCr 12
478 #define W_DMACR2__Data12RdMaxCr 3
479 #define O_DMACR2__Data13WrMaxCr 9
480 #define W_DMACR2__Data13WrMaxCr 3
481 #define O_DMACR2__Data13RdMaxCr 6
482 #define W_DMACR2__Data13RdMaxCr 3
483 #define O_DMACR2__Data14WrMaxCr 3
484 #define W_DMACR2__Data14WrMaxCr 3
485 #define O_DMACR2__Data14RdMaxCr 0
486 #define W_DMACR2__Data14RdMaxCr 3
487 #define R_DMACR3 0x203
488 #define O_DMACR3__Data15WrMaxCr 27
489 #define W_DMACR3__Data15WrMaxCr 3
490 #define O_DMACR3__Data15RdMaxCr 24
491 #define W_DMACR3__Data15RdMaxCr 3
492 #define O_DMACR3__SpClassWrMaxCr 21
493 #define W_DMACR3__SpClassWrMaxCr 3
494 #define O_DMACR3__SpClassRdMaxCr 18
495 #define W_DMACR3__SpClassRdMaxCr 3
496 #define O_DMACR3__JumFrInWrMaxCr 15
497 #define W_DMACR3__JumFrInWrMaxCr 3
498 #define O_DMACR3__JumFrInRdMaxCr 12
499 #define W_DMACR3__JumFrInRdMaxCr 3
500 #define O_DMACR3__RegFrInWrMaxCr 9
501 #define W_DMACR3__RegFrInWrMaxCr 3
502 #define O_DMACR3__RegFrInRdMaxCr 6
503 #define W_DMACR3__RegFrInRdMaxCr 3
504 #define O_DMACR3__FrOutWrMaxCr 3
505 #define W_DMACR3__FrOutWrMaxCr 3
506 #define O_DMACR3__FrOutRdMaxCr 0
507 #define W_DMACR3__FrOutRdMaxCr 3
508 #define R_REG_FRIN_SPILL_MEM_START_0 0x204
509 #define O_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 0
510 #define W_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 32
511 #define R_REG_FRIN_SPILL_MEM_START_1 0x205
512 #define O_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 0
513 #define W_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 3
514 #define R_REG_FRIN_SPILL_MEM_SIZE 0x206
515 #define O_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 0
516 #define W_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 32
517 #define R_FROUT_SPILL_MEM_START_0 0x207
518 #define O_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 0
519 #define W_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 32
520 #define R_FROUT_SPILL_MEM_START_1 0x208
521 #define O_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 0
522 #define W_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 3
523 #define R_FROUT_SPILL_MEM_SIZE 0x209
524 #define O_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 0
525 #define W_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 32
526 #define R_CLASS0_SPILL_MEM_START_0 0x20A
527 #define O_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 0
528 #define W_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 32
529 #define R_CLASS0_SPILL_MEM_START_1 0x20B
530 #define O_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 0
531 #define W_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 3
532 #define R_CLASS0_SPILL_MEM_SIZE 0x20C
533 #define O_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 0
534 #define W_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 32
535 #define R_JUMFRIN_SPILL_MEM_START_0 0x20D
536 #define O_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 0
537 #define W_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 32
538 #define R_JUMFRIN_SPILL_MEM_START_1 0x20E
539 #define O_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 0
540 #define W_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 3
541 #define R_JUMFRIN_SPILL_MEM_SIZE 0x20F
542 #define O_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 0
543 #define W_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 32
544 #define R_CLASS1_SPILL_MEM_START_0 0x210
545 #define O_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 0
546 #define W_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 32
547 #define R_CLASS1_SPILL_MEM_START_1 0x211
548 #define O_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 0
549 #define W_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 3
550 #define R_CLASS1_SPILL_MEM_SIZE 0x212
551 #define O_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 0
552 #define W_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 32
553 #define R_CLASS2_SPILL_MEM_START_0 0x213
554 #define O_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 0
555 #define W_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 32
556 #define R_CLASS2_SPILL_MEM_START_1 0x214
557 #define O_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 0
558 #define W_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 3
559 #define R_CLASS2_SPILL_MEM_SIZE 0x215
560 #define O_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 0
561 #define W_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 32
562 #define R_CLASS3_SPILL_MEM_START_0 0x216
563 #define O_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 0
564 #define W_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 32
565 #define R_CLASS3_SPILL_MEM_START_1 0x217
566 #define O_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 0
567 #define W_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 3
568 #define R_CLASS3_SPILL_MEM_SIZE 0x218
569 #define O_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 0
570 #define W_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 32
571 #define R_REG_FRIN1_SPILL_MEM_START_0 0x219
572 #define R_REG_FRIN1_SPILL_MEM_START_1 0x21a
573 #define R_REG_FRIN1_SPILL_MEM_SIZE 0x21b
574 #define R_SPIHNGY0 0x219
575 #define O_SPIHNGY0__EG_HNGY_THRESH_0 24
576 #define W_SPIHNGY0__EG_HNGY_THRESH_0 7
577 #define O_SPIHNGY0__EG_HNGY_THRESH_1 16
578 #define W_SPIHNGY0__EG_HNGY_THRESH_1 7
579 #define O_SPIHNGY0__EG_HNGY_THRESH_2 8
580 #define W_SPIHNGY0__EG_HNGY_THRESH_2 7
581 #define O_SPIHNGY0__EG_HNGY_THRESH_3 0
582 #define W_SPIHNGY0__EG_HNGY_THRESH_3 7
583 #define R_SPIHNGY1 0x21A
584 #define O_SPIHNGY1__EG_HNGY_THRESH_4 24
585 #define W_SPIHNGY1__EG_HNGY_THRESH_4 7
586 #define O_SPIHNGY1__EG_HNGY_THRESH_5 16
587 #define W_SPIHNGY1__EG_HNGY_THRESH_5 7
588 #define O_SPIHNGY1__EG_HNGY_THRESH_6 8
589 #define W_SPIHNGY1__EG_HNGY_THRESH_6 7
590 #define O_SPIHNGY1__EG_HNGY_THRESH_7 0
591 #define W_SPIHNGY1__EG_HNGY_THRESH_7 7
592 #define R_SPIHNGY2 0x21B
593 #define O_SPIHNGY2__EG_HNGY_THRESH_8 24
594 #define W_SPIHNGY2__EG_HNGY_THRESH_8 7
595 #define O_SPIHNGY2__EG_HNGY_THRESH_9 16
596 #define W_SPIHNGY2__EG_HNGY_THRESH_9 7
597 #define O_SPIHNGY2__EG_HNGY_THRESH_10 8
598 #define W_SPIHNGY2__EG_HNGY_THRESH_10 7
599 #define O_SPIHNGY2__EG_HNGY_THRESH_11 0
600 #define W_SPIHNGY2__EG_HNGY_THRESH_11 7
601 #define R_SPIHNGY3 0x21C
602 #define O_SPIHNGY3__EG_HNGY_THRESH_12 24
603 #define W_SPIHNGY3__EG_HNGY_THRESH_12 7
604 #define O_SPIHNGY3__EG_HNGY_THRESH_13 16
605 #define W_SPIHNGY3__EG_HNGY_THRESH_13 7
606 #define O_SPIHNGY3__EG_HNGY_THRESH_14 8
607 #define W_SPIHNGY3__EG_HNGY_THRESH_14 7
608 #define O_SPIHNGY3__EG_HNGY_THRESH_15 0
609 #define W_SPIHNGY3__EG_HNGY_THRESH_15 7
610 #define R_SPISTRV0 0x21D
611 #define O_SPISTRV0__EG_STRV_THRESH_0 24
612 #define W_SPISTRV0__EG_STRV_THRESH_0 7
613 #define O_SPISTRV0__EG_STRV_THRESH_1 16
614 #define W_SPISTRV0__EG_STRV_THRESH_1 7
615 #define O_SPISTRV0__EG_STRV_THRESH_2 8
616 #define W_SPISTRV0__EG_STRV_THRESH_2 7
617 #define O_SPISTRV0__EG_STRV_THRESH_3 0
618 #define W_SPISTRV0__EG_STRV_THRESH_3 7
619 #define R_SPISTRV1 0x21E
620 #define O_SPISTRV1__EG_STRV_THRESH_4 24
621 #define W_SPISTRV1__EG_STRV_THRESH_4 7
622 #define O_SPISTRV1__EG_STRV_THRESH_5 16
623 #define W_SPISTRV1__EG_STRV_THRESH_5 7
624 #define O_SPISTRV1__EG_STRV_THRESH_6 8
625 #define W_SPISTRV1__EG_STRV_THRESH_6 7
626 #define O_SPISTRV1__EG_STRV_THRESH_7 0
627 #define W_SPISTRV1__EG_STRV_THRESH_7 7
628 #define R_SPISTRV2 0x21F
629 #define O_SPISTRV2__EG_STRV_THRESH_8 24
630 #define W_SPISTRV2__EG_STRV_THRESH_8 7
631 #define O_SPISTRV2__EG_STRV_THRESH_9 16
632 #define W_SPISTRV2__EG_STRV_THRESH_9 7
633 #define O_SPISTRV2__EG_STRV_THRESH_10 8
634 #define W_SPISTRV2__EG_STRV_THRESH_10 7
635 #define O_SPISTRV2__EG_STRV_THRESH_11 0
636 #define W_SPISTRV2__EG_STRV_THRESH_11 7
637 #define R_SPISTRV3 0x220
638 #define O_SPISTRV3__EG_STRV_THRESH_12 24
639 #define W_SPISTRV3__EG_STRV_THRESH_12 7
640 #define O_SPISTRV3__EG_STRV_THRESH_13 16
641 #define W_SPISTRV3__EG_STRV_THRESH_13 7
642 #define O_SPISTRV3__EG_STRV_THRESH_14 8
643 #define W_SPISTRV3__EG_STRV_THRESH_14 7
644 #define O_SPISTRV3__EG_STRV_THRESH_15 0
645 #define W_SPISTRV3__EG_STRV_THRESH_15 7
646 #define R_TXDATAFIFO0 0x221
647 #define O_TXDATAFIFO0__Tx0DataFifoStart 24
648 #define W_TXDATAFIFO0__Tx0DataFifoStart 7
649 #define O_TXDATAFIFO0__Tx0DataFifoSize 16
650 #define W_TXDATAFIFO0__Tx0DataFifoSize 7
651 #define O_TXDATAFIFO0__Tx1DataFifoStart 8
652 #define W_TXDATAFIFO0__Tx1DataFifoStart 7
653 #define O_TXDATAFIFO0__Tx1DataFifoSize 0
654 #define W_TXDATAFIFO0__Tx1DataFifoSize 7
655 #define R_TXDATAFIFO1 0x222
656 #define O_TXDATAFIFO1__Tx2DataFifoStart 24
657 #define W_TXDATAFIFO1__Tx2DataFifoStart 7
658 #define O_TXDATAFIFO1__Tx2DataFifoSize 16
659 #define W_TXDATAFIFO1__Tx2DataFifoSize 7
660 #define O_TXDATAFIFO1__Tx3DataFifoStart 8
661 #define W_TXDATAFIFO1__Tx3DataFifoStart 7
662 #define O_TXDATAFIFO1__Tx3DataFifoSize 0
663 #define W_TXDATAFIFO1__Tx3DataFifoSize 7
664 #define R_TXDATAFIFO2 0x223
665 #define O_TXDATAFIFO2__Tx4DataFifoStart 24
666 #define W_TXDATAFIFO2__Tx4DataFifoStart 7
667 #define O_TXDATAFIFO2__Tx4DataFifoSize 16
668 #define W_TXDATAFIFO2__Tx4DataFifoSize 7
669 #define O_TXDATAFIFO2__Tx5DataFifoStart 8
670 #define W_TXDATAFIFO2__Tx5DataFifoStart 7
671 #define O_TXDATAFIFO2__Tx5DataFifoSize 0
672 #define W_TXDATAFIFO2__Tx5DataFifoSize 7
673 #define R_TXDATAFIFO3 0x224
674 #define O_TXDATAFIFO3__Tx6DataFifoStart 24
675 #define W_TXDATAFIFO3__Tx6DataFifoStart 7
676 #define O_TXDATAFIFO3__Tx6DataFifoSize 16
677 #define W_TXDATAFIFO3__Tx6DataFifoSize 7
678 #define O_TXDATAFIFO3__Tx7DataFifoStart 8
679 #define W_TXDATAFIFO3__Tx7DataFifoStart 7
680 #define O_TXDATAFIFO3__Tx7DataFifoSize 0
681 #define W_TXDATAFIFO3__Tx7DataFifoSize 7
682 #define R_TXDATAFIFO4 0x225
683 #define O_TXDATAFIFO4__Tx8DataFifoStart 24
684 #define W_TXDATAFIFO4__Tx8DataFifoStart 7
685 #define O_TXDATAFIFO4__Tx8DataFifoSize 16
686 #define W_TXDATAFIFO4__Tx8DataFifoSize 7
687 #define O_TXDATAFIFO4__Tx9DataFifoStart 8
688 #define W_TXDATAFIFO4__Tx9DataFifoStart 7
689 #define O_TXDATAFIFO4__Tx9DataFifoSize 0
690 #define W_TXDATAFIFO4__Tx9DataFifoSize 7
691 #define R_TXDATAFIFO5 0x226
692 #define O_TXDATAFIFO5__Tx10DataFifoStart 24
693 #define W_TXDATAFIFO5__Tx10DataFifoStart 7
694 #define O_TXDATAFIFO5__Tx10DataFifoSize 16
695 #define W_TXDATAFIFO5__Tx10DataFifoSize 7
696 #define O_TXDATAFIFO5__Tx11DataFifoStart 8
697 #define W_TXDATAFIFO5__Tx11DataFifoStart 7
698 #define O_TXDATAFIFO5__Tx11DataFifoSize 0
699 #define W_TXDATAFIFO5__Tx11DataFifoSize 7
700 #define R_TXDATAFIFO6 0x227
701 #define O_TXDATAFIFO6__Tx12DataFifoStart 24
702 #define W_TXDATAFIFO6__Tx12DataFifoStart 7
703 #define O_TXDATAFIFO6__Tx12DataFifoSize 16
704 #define W_TXDATAFIFO6__Tx12DataFifoSize 7
705 #define O_TXDATAFIFO6__Tx13DataFifoStart 8
706 #define W_TXDATAFIFO6__Tx13DataFifoStart 7
707 #define O_TXDATAFIFO6__Tx13DataFifoSize 0
708 #define W_TXDATAFIFO6__Tx13DataFifoSize 7
709 #define R_TXDATAFIFO7 0x228
710 #define O_TXDATAFIFO7__Tx14DataFifoStart 24
711 #define W_TXDATAFIFO7__Tx14DataFifoStart 7
712 #define O_TXDATAFIFO7__Tx14DataFifoSize 16
713 #define W_TXDATAFIFO7__Tx14DataFifoSize 7
714 #define O_TXDATAFIFO7__Tx15DataFifoStart 8
715 #define W_TXDATAFIFO7__Tx15DataFifoStart 7
716 #define O_TXDATAFIFO7__Tx15DataFifoSize 0
717 #define W_TXDATAFIFO7__Tx15DataFifoSize 7
718 #define R_RXDATAFIFO0 0x229
719 #define O_RXDATAFIFO0__Rx0DataFifoStart 24
720 #define W_RXDATAFIFO0__Rx0DataFifoStart 7
721 #define O_RXDATAFIFO0__Rx0DataFifoSize 16
722 #define W_RXDATAFIFO0__Rx0DataFifoSize 7
723 #define O_RXDATAFIFO0__Rx1DataFifoStart 8
724 #define W_RXDATAFIFO0__Rx1DataFifoStart 7
725 #define O_RXDATAFIFO0__Rx1DataFifoSize 0
726 #define W_RXDATAFIFO0__Rx1DataFifoSize 7
727 #define R_RXDATAFIFO1 0x22A
728 #define O_RXDATAFIFO1__Rx2DataFifoStart 24
729 #define W_RXDATAFIFO1__Rx2DataFifoStart 7
730 #define O_RXDATAFIFO1__Rx2DataFifoSize 16
731 #define W_RXDATAFIFO1__Rx2DataFifoSize 7
732 #define O_RXDATAFIFO1__Rx3DataFifoStart 8
733 #define W_RXDATAFIFO1__Rx3DataFifoStart 7
734 #define O_RXDATAFIFO1__Rx3DataFifoSize 0
735 #define W_RXDATAFIFO1__Rx3DataFifoSize 7
736 #define R_RXDATAFIFO2 0x22B
737 #define O_RXDATAFIFO2__Rx4DataFifoStart 24
738 #define W_RXDATAFIFO2__Rx4DataFifoStart 7
739 #define O_RXDATAFIFO2__Rx4DataFifoSize 16
740 #define W_RXDATAFIFO2__Rx4DataFifoSize 7
741 #define O_RXDATAFIFO2__Rx5DataFifoStart 8
742 #define W_RXDATAFIFO2__Rx5DataFifoStart 7
743 #define O_RXDATAFIFO2__Rx5DataFifoSize 0
744 #define W_RXDATAFIFO2__Rx5DataFifoSize 7
745 #define R_RXDATAFIFO3 0x22C
746 #define O_RXDATAFIFO3__Rx6DataFifoStart 24
747 #define W_RXDATAFIFO3__Rx6DataFifoStart 7
748 #define O_RXDATAFIFO3__Rx6DataFifoSize 16
749 #define W_RXDATAFIFO3__Rx6DataFifoSize 7
750 #define O_RXDATAFIFO3__Rx7DataFifoStart 8
751 #define W_RXDATAFIFO3__Rx7DataFifoStart 7
752 #define O_RXDATAFIFO3__Rx7DataFifoSize 0
753 #define W_RXDATAFIFO3__Rx7DataFifoSize 7
754 #define R_RXDATAFIFO4 0x22D
755 #define O_RXDATAFIFO4__Rx8DataFifoStart 24
756 #define W_RXDATAFIFO4__Rx8DataFifoStart 7
757 #define O_RXDATAFIFO4__Rx8DataFifoSize 16
758 #define W_RXDATAFIFO4__Rx8DataFifoSize 7
759 #define O_RXDATAFIFO4__Rx9DataFifoStart 8
760 #define W_RXDATAFIFO4__Rx9DataFifoStart 7
761 #define O_RXDATAFIFO4__Rx9DataFifoSize 0
762 #define W_RXDATAFIFO4__Rx9DataFifoSize 7
763 #define R_RXDATAFIFO5 0x22E
764 #define O_RXDATAFIFO5__Rx10DataFifoStart 24
765 #define W_RXDATAFIFO5__Rx10DataFifoStart 7
766 #define O_RXDATAFIFO5__Rx10DataFifoSize 16
767 #define W_RXDATAFIFO5__Rx10DataFifoSize 7
768 #define O_RXDATAFIFO5__Rx11DataFifoStart 8
769 #define W_RXDATAFIFO5__Rx11DataFifoStart 7
770 #define O_RXDATAFIFO5__Rx11DataFifoSize 0
771 #define W_RXDATAFIFO5__Rx11DataFifoSize 7
772 #define R_RXDATAFIFO6 0x22F
773 #define O_RXDATAFIFO6__Rx12DataFifoStart 24
774 #define W_RXDATAFIFO6__Rx12DataFifoStart 7
775 #define O_RXDATAFIFO6__Rx12DataFifoSize 16
776 #define W_RXDATAFIFO6__Rx12DataFifoSize 7
777 #define O_RXDATAFIFO6__Rx13DataFifoStart 8
778 #define W_RXDATAFIFO6__Rx13DataFifoStart 7
779 #define O_RXDATAFIFO6__Rx13DataFifoSize 0
780 #define W_RXDATAFIFO6__Rx13DataFifoSize 7
781 #define R_RXDATAFIFO7 0x230
782 #define O_RXDATAFIFO7__Rx14DataFifoStart 24
783 #define W_RXDATAFIFO7__Rx14DataFifoStart 7
784 #define O_RXDATAFIFO7__Rx14DataFifoSize 16
785 #define W_RXDATAFIFO7__Rx14DataFifoSize 7
786 #define O_RXDATAFIFO7__Rx15DataFifoStart 8
787 #define W_RXDATAFIFO7__Rx15DataFifoStart 7
788 #define O_RXDATAFIFO7__Rx15DataFifoSize 0
789 #define W_RXDATAFIFO7__Rx15DataFifoSize 7
790 #define R_XGMACPADCALIBRATION 0x231
791 #define R_FREEQCARVE 0x233
792 #define R_SPI4STATICDELAY0 0x240
793 #define O_SPI4STATICDELAY0__DataLine7 28
794 #define W_SPI4STATICDELAY0__DataLine7 4
795 #define O_SPI4STATICDELAY0__DataLine6 24
796 #define W_SPI4STATICDELAY0__DataLine6 4
797 #define O_SPI4STATICDELAY0__DataLine5 20
798 #define W_SPI4STATICDELAY0__DataLine5 4
799 #define O_SPI4STATICDELAY0__DataLine4 16
800 #define W_SPI4STATICDELAY0__DataLine4 4
801 #define O_SPI4STATICDELAY0__DataLine3 12
802 #define W_SPI4STATICDELAY0__DataLine3 4
803 #define O_SPI4STATICDELAY0__DataLine2 8
804 #define W_SPI4STATICDELAY0__DataLine2 4
805 #define O_SPI4STATICDELAY0__DataLine1 4
806 #define W_SPI4STATICDELAY0__DataLine1 4
807 #define O_SPI4STATICDELAY0__DataLine0 0
808 #define W_SPI4STATICDELAY0__DataLine0 4
809 #define R_SPI4STATICDELAY1 0x241
810 #define O_SPI4STATICDELAY1__DataLine15 28
811 #define W_SPI4STATICDELAY1__DataLine15 4
812 #define O_SPI4STATICDELAY1__DataLine14 24
813 #define W_SPI4STATICDELAY1__DataLine14 4
814 #define O_SPI4STATICDELAY1__DataLine13 20
815 #define W_SPI4STATICDELAY1__DataLine13 4
816 #define O_SPI4STATICDELAY1__DataLine12 16
817 #define W_SPI4STATICDELAY1__DataLine12 4
818 #define O_SPI4STATICDELAY1__DataLine11 12
819 #define W_SPI4STATICDELAY1__DataLine11 4
820 #define O_SPI4STATICDELAY1__DataLine10 8
821 #define W_SPI4STATICDELAY1__DataLine10 4
822 #define O_SPI4STATICDELAY1__DataLine9 4
823 #define W_SPI4STATICDELAY1__DataLine9 4
824 #define O_SPI4STATICDELAY1__DataLine8 0
825 #define W_SPI4STATICDELAY1__DataLine8 4
826 #define R_SPI4STATICDELAY2 0x242
827 #define O_SPI4STATICDELAY0__TxStat1 8
828 #define W_SPI4STATICDELAY0__TxStat1 4
829 #define O_SPI4STATICDELAY0__TxStat0 4
830 #define W_SPI4STATICDELAY0__TxStat0 4
831 #define O_SPI4STATICDELAY0__RxControl 0
832 #define W_SPI4STATICDELAY0__RxControl 4
833 #define R_SPI4CONTROL 0x243
834 #define O_SPI4CONTROL__StaticDelay 2
835 #define O_SPI4CONTROL__LVDS_LVTTL 1
836 #define O_SPI4CONTROL__SPI4Enable 0
837 #define R_CLASSWATERMARKS 0x244
838 #define O_CLASSWATERMARKS__Class0Watermark 24
839 #define W_CLASSWATERMARKS__Class0Watermark 5
840 #define O_CLASSWATERMARKS__Class1Watermark 16
841 #define W_CLASSWATERMARKS__Class1Watermark 5
842 #define O_CLASSWATERMARKS__Class3Watermark 0
843 #define W_CLASSWATERMARKS__Class3Watermark 5
844 #define R_RXWATERMARKS1 0x245
845 #define O_RXWATERMARKS__Rx0DataWatermark 24
846 #define W_RXWATERMARKS__Rx0DataWatermark 7
847 #define O_RXWATERMARKS__Rx1DataWatermark 16
848 #define W_RXWATERMARKS__Rx1DataWatermark 7
849 #define O_RXWATERMARKS__Rx3DataWatermark 0
850 #define W_RXWATERMARKS__Rx3DataWatermark 7
851 #define R_RXWATERMARKS2 0x246
852 #define O_RXWATERMARKS__Rx4DataWatermark 24
853 #define W_RXWATERMARKS__Rx4DataWatermark 7
854 #define O_RXWATERMARKS__Rx5DataWatermark 16
855 #define W_RXWATERMARKS__Rx5DataWatermark 7
856 #define O_RXWATERMARKS__Rx6DataWatermark 8
857 #define W_RXWATERMARKS__Rx6DataWatermark 7
858 #define O_RXWATERMARKS__Rx7DataWatermark 0
859 #define W_RXWATERMARKS__Rx7DataWatermark 7
860 #define R_RXWATERMARKS3 0x247
861 #define O_RXWATERMARKS__Rx8DataWatermark 24
862 #define W_RXWATERMARKS__Rx8DataWatermark 7
863 #define O_RXWATERMARKS__Rx9DataWatermark 16
864 #define W_RXWATERMARKS__Rx9DataWatermark 7
865 #define O_RXWATERMARKS__Rx10DataWatermark 8
866 #define W_RXWATERMARKS__Rx10DataWatermark 7
867 #define O_RXWATERMARKS__Rx11DataWatermark 0
868 #define W_RXWATERMARKS__Rx11DataWatermark 7
869 #define R_RXWATERMARKS4 0x248
870 #define O_RXWATERMARKS__Rx12DataWatermark 24
871 #define W_RXWATERMARKS__Rx12DataWatermark 7
872 #define O_RXWATERMARKS__Rx13DataWatermark 16
873 #define W_RXWATERMARKS__Rx13DataWatermark 7
874 #define O_RXWATERMARKS__Rx14DataWatermark 8
875 #define W_RXWATERMARKS__Rx14DataWatermark 7
876 #define O_RXWATERMARKS__Rx15DataWatermark 0
877 #define W_RXWATERMARKS__Rx15DataWatermark 7
878 #define R_FREEWATERMARKS 0x249
879 #define O_FREEWATERMARKS__FreeOutWatermark 16
880 #define W_FREEWATERMARKS__FreeOutWatermark 16
881 #define O_FREEWATERMARKS__JumFrWatermark 8
882 #define W_FREEWATERMARKS__JumFrWatermark 7
883 #define O_FREEWATERMARKS__RegFrWatermark 0
884 #define W_FREEWATERMARKS__RegFrWatermark 7
885 #define R_EGRESSFIFOCARVINGSLOTS 0x24a
889 #define CTRL_REG_FREE 2
890 #define CTRL_JUMBO_FREE 3
896 #define CTRL_B0_NOT_EOP 0
897 #define CTRL_B0_EOP 1
899 #define R_ROUND_ROBIN_TABLE 0
900 #define R_PDE_CLASS_0 0x300
901 #define R_PDE_CLASS_1 0x302
902 #define R_PDE_CLASS_2 0x304
903 #define R_PDE_CLASS_3 0x306
905 #define R_MSG_TX_THRESHOLD 0x308
907 #define R_GMAC_JFR0_BUCKET_SIZE 0x320
908 #define R_GMAC_RFR0_BUCKET_SIZE 0x321
909 #define R_GMAC_TX0_BUCKET_SIZE 0x322
910 #define R_GMAC_TX1_BUCKET_SIZE 0x323
911 #define R_GMAC_TX2_BUCKET_SIZE 0x324
912 #define R_GMAC_TX3_BUCKET_SIZE 0x325
913 #define R_GMAC_JFR1_BUCKET_SIZE 0x326
914 #define R_GMAC_RFR1_BUCKET_SIZE 0x327
916 #define R_XGS_TX0_BUCKET_SIZE 0x320
917 #define R_XGS_TX1_BUCKET_SIZE 0x321
918 #define R_XGS_TX2_BUCKET_SIZE 0x322
919 #define R_XGS_TX3_BUCKET_SIZE 0x323
920 #define R_XGS_TX4_BUCKET_SIZE 0x324
921 #define R_XGS_TX5_BUCKET_SIZE 0x325
922 #define R_XGS_TX6_BUCKET_SIZE 0x326
923 #define R_XGS_TX7_BUCKET_SIZE 0x327
924 #define R_XGS_TX8_BUCKET_SIZE 0x328
925 #define R_XGS_TX9_BUCKET_SIZE 0x329
926 #define R_XGS_TX10_BUCKET_SIZE 0x32A
927 #define R_XGS_TX11_BUCKET_SIZE 0x32B
928 #define R_XGS_TX12_BUCKET_SIZE 0x32C
929 #define R_XGS_TX13_BUCKET_SIZE 0x32D
930 #define R_XGS_TX14_BUCKET_SIZE 0x32E
931 #define R_XGS_TX15_BUCKET_SIZE 0x32F
932 #define R_XGS_JFR_BUCKET_SIZE 0x330
933 #define R_XGS_RFR_BUCKET_SIZE 0x331
935 #define R_CC_CPU0_0 0x380
936 #define R_CC_CPU1_0 0x388
937 #define R_CC_CPU2_0 0x390
938 #define R_CC_CPU3_0 0x398
939 #define R_CC_CPU4_0 0x3a0
940 #define R_CC_CPU5_0 0x3a8
941 #define R_CC_CPU6_0 0x3b0
942 #define R_CC_CPU7_0 0x3b8
945 xlr_mac_speed_10, xlr_mac_speed_100,
946 xlr_mac_speed_1000, xlr_mac_speed_rsvd
950 xlr_mac_duplex_auto, xlr_mac_duplex_half,
960 xlr_mac_fc_auto, xlr_mac_fc_disabled, xlr_mac_fc_frame,
961 xlr_mac_fc_collision, xlr_mac_fc_carrier
964 /* static int mac_frin_to_be_sent_thr[8]; */
971 PORT_START_DEV_STATE,
975 struct rge_softc_stats {
976 unsigned int rx_frames;
977 unsigned int tx_frames;
978 unsigned int rx_packets;
979 unsigned int rx_bytes;
980 unsigned int tx_packets;
981 unsigned int tx_bytes;
987 * Let these be the first fields in this structure the structure is
988 * cacheline aligned when allocated in init_etherdev
990 struct fr_desc *frin_spill;
991 struct fr_desc *frout_spill;
992 union rx_tx_desc *class_0_spill;
993 union rx_tx_desc *class_1_spill;
994 union rx_tx_desc *class_2_spill;
995 union rx_tx_desc *class_3_spill;
996 int spill_configured;
998 struct rge_softc *sc; /* pointer to freebsd device soft-pointer */
999 struct rge_softc_stats stats;
1003 xlr_reg_t *mii_mmio;
1004 xlr_reg_t *pcs_mmio;
1005 xlr_reg_t *serdes_mmio;
1013 int phy_oldlinkstat;
1014 unsigned char phys_addr[2];
1016 xlr_mac_speed_t speed; /* current speed */
1017 xlr_mac_duplex_t duplex;/* current duplex */
1018 xlr_mac_link_t link; /* current link */
1019 xlr_mac_fc_t flow_ctrl; /* current flow control setting */
1027 int frin_to_be_sent[8];
1034 unsigned char dev_addr[6];
1035 unsigned long base_addr;
1036 unsigned long mem_end;
1037 struct ifnet *rge_ifp; /* interface info */
1041 struct driver_data priv;
1043 device_t rge_miibus;
1044 struct mii_data rge_mii;/* MII/media information */
1045 bus_space_handle_t rge_bhandle;
1046 bus_space_tag_t rge_btag;
1048 struct resource rge_irq;
1049 struct resource *rge_res;
1050 struct ifmedia rge_ifmedia; /* TBI media info */
1052 int rge_link; /* link state */
1053 int rge_link_evt; /* pending link event */
1054 struct callout rge_stat_ch;
1055 void (*xmit) (struct ifnet *);
1056 void (*stop) (struct rge_softc *);
1057 int (*ioctl) (struct ifnet *, u_long, caddr_t);
1058 struct rge_softc_stats *(*get_stats) (struct rge_softc *);
1063 struct size_1_desc {
1067 struct size_2_desc {
1072 struct size_3_desc {
1078 struct size_4_desc {
1086 struct size_1_desc d1;
1090 struct size_2_desc d2;
1091 /* struct size_3_desc d3; */
1092 /* struct size_4_desc d4; */
1096 extern unsigned char xlr_base_mac_addr[];