sys/mips/rt305x/rt_swreg.h

   1 /*-
   2  * Copyright (c) 2010 Aleksandr Rybalko.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #ifndef _RT_SWREG_H_
  30 #define _RT_SWREG_H_
  31
  32 /* XXX: must move to config */
  33 #define RT3052F
  34
  35 #define RT_SW_BASE      0x10110000
  36
  37 #define RT_SW_ISR               0x00
  38
  39 #define         WATCHDOG1_TMR_EXPIRED   (1<<29)
  40 #define         WATCHDOG0_TMR_EXPIRED   (1<<28)
  41 #define         HAS_INTRUDER            (1<<27)
  42 #define         PORT_ST_CHG             (1<<26)
  43 #define         BC_STORM                (1<<25)
  44 #define         MUST_DROP_LAN           (1<<24)
  45 #define         GLOBAL_QUE_FULL         (1<<23)
  46 #define         LAN_QUE_FULL6           (1<<20)
  47 #define         LAN_QUE_FULL5           (1<<19)
  48 #define         LAN_QUE_FULL4           (1<<18)
  49 #define         LAN_QUE_FULL3           (1<<17)
  50 #define         LAN_QUE_FULL2           (1<<16)
  51 #define         LAN_QUE_FULL1           (1<<15)
  52 #define         LAN_QUE_FULL0           (1<<14)
  53
  54 #define RT_SW_IMR               0x04
  55
  56 #define RT_SW_FCT0              0x08
  57 #define RT_SW_FCT1              0x0c
  58 #define RT_SW_PFC0              0x10
  59 #define RT_SW_PFC1              0x14
  60 #define RT_SW_PFC2              0x18
  61 #define RT_SW_GQS0              0x1c
  62 #define RT_SW_GQS1              0x20
  63 #define RT_SW_ATS               0x24
  64 #define RT_SW_ATS0              0x28
  65 #define RT_SW_ATS1              0x2c
  66 #define RT_SW_ATS2              0x30
  67 #define RT_SW_WMAD0             0x34
  68 #define RT_SW_WMAD1             0x38
  69 #define RT_SW_WMAD2             0x3c
  70 #define RT_SW_PVIDC0            0x40
  71 #define RT_SW_PVIDC1            0x44
  72 #define RT_SW_PVIDC2            0x48
  73 #define RT_SW_PVIDC3            0x4c
  74 #define RT_SW_VID0              0x50
  75 #define RT_SW_VID1              0x54
  76 #define RT_SW_VID2              0x58
  77 #define RT_SW_VID3              0x5c
  78 #define RT_SW_VID4              0x60
  79 #define RT_SW_VID5              0x64
  80 #define RT_SW_VID6              0x68
  81 #define RT_SW_VID7              0x6c
  82 #define RT_SW_VMSC0             0x70
  83 #define RT_SW_VMSC1             0x74
  84 #define RT_SW_VMSC2             0x78
  85 #define RT_SW_VMSC3             0x7c
  86 #define RT_SW_POA               0x80
  87 #define RT_SW_FPA               0x84
  88 #define RT_SW_PTS               0x88
  89 #define RT_SW_SOCPC             0x8c
  90 #define RT_SW_POC0              0x90
  91 #define RT_SW_POC1              0x94
  92 #define RT_SW_POC2              0x98
  93 #define RT_SW_SGC               0x9c
  94 #define RT_SW_STRT              0xa0
  95 #define RT_SW_LEDP0             0xa4
  96 #define RT_SW_LEDP1             0xa8
  97 #define RT_SW_LEDP2             0xac
  98 #define RT_SW_LEDP3             0xb0
  99 #define RT_SW_LEDP4             0xb4
 100 #define RT_SW_WDTR              0xb8
 101 #define RT_SW_DES               0xbc
 102 #define RT_SW_PCR0              0xc0
 103 #define RT_SW_PCR1              0xc4
 104 #define RT_SW_FPA               0xc8
 105 #define RT_SW_FCT2              0xcc
 106 #define RT_SW_QSS0              0xd0
 107
 108 #define RT_SW_QSS1              0xd4
 109 #define RT_SW_DEC               0xd8
 110 #define         BRIDGE_IPG_SHIFT        24
 111 #define         DEBUG_SW_PORT_SEL_SHIFT 3
 112 #define         DEBUG_SW_PORT_SEL_MASK  0x00000038
 113
 114 #define RT_SW_MTI               0xdc
 115 #define         SKIP_BLOCKS_SHIFT       7
 116 #define         SKIP_BLOCKS_MASK        0x0000ff80
 117 #define         SW_RAM_TEST_DONE        (1<<6)
 118 #define         AT_RAM_TEST_DONE        (1<<5)
 119 #define         AT_RAM_TEST_FAIL        (1<<4)
 120 #define         LK_RAM_TEST_DONE        (1<<3)
 121 #define         LK_RAM_TEST_FAIL        (1<<2)
 122 #define         DT_RAM_TEST_DONE        (1<<1)
 123 #define         DT_RAM_TEST_FAIL        (1<<0)
 124
 125 #define RT_SW_PPC               0xe0
 126 #define         SW2FE_CNT_SHIFT         16
 127 #define         FE2SW_CNT_SHIFT         0
 128
 129 #define RT_SW_SGC2              0xe4
 130 #define         FE2SW_WL_FC_EN  (1<<30)
 131 #define         LAN_PMAP_P0_IS_LAN              (1<<24)
 132 #define         LAN_PMAP_P1_IS_LAN              (1<<25)
 133 #define         LAN_PMAP_P2_IS_LAN              (1<<26)
 134 #define         LAN_PMAP_P3_IS_LAN              (1<<27)
 135 #define         LAN_PMAP_P4_IS_LAN              (1<<28)
 136 #define         LAN_PMAP_P5_IS_LAN              (1<<29)
 137 /* Transmit CPU TPID(810x) port bit map */
 138 #define         TX_CPU_TPID_BIT_MAP_SHIFT       16
 139 #define         TX_CPU_TPID_BIT_MAP_MASK        0x007f0000
 140 #define         ARBITER_LAN_EN                  (1<<11)
 141 #define         CPU_TPID_EN                     (1<<10)
 142 #define         P0_DOUBLE_TAG_EN                (1<<0)
 143 #define         P1_DOUBLE_TAG_EN                (1<<1)
 144 #define         P2_DOUBLE_TAG_EN                (1<<2)
 145 #define         P3_DOUBLE_TAG_EN                (1<<3)
 146 #define         P4_DOUBLE_TAG_EN                (1<<4)
 147 #define         P5_DOUBLE_TAG_EN                (1<<5)
 148
 149 #define RT_SW_P0PC              0xe8
 150 #define RT_SW_P1PC              0xec
 151 #define RT_SW_P2PC              0xf0
 152 #define RT_SW_P3PC              0xf4
 153 #define RT_SW_P4PC              0xf8
 154 #define RT_SW_P5PC              0xfc
 155 #define         BAD_PCOUNT_SHIFT        16
 156 #define         BAD_PCOUNT_MASK         0xffff0000
 157 #define         GOOD_PCOUNT_SHIFT       0
 158 #define         GOOD_PCOUNT_MASK        0x0000ffff
 159
 160 #endif /* _RT_SWREG_H_ */