2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/init.h>
38 #include <linux/mlx4/cmd.h>
39 #include <linux/mlx4/qp.h>
45 * QP to support BF should have bits 6,7 cleared
47 #define MLX4_BF_QP_SKIP_MASK 0xc0
48 #define MLX4_MAX_BF_QP_RANGE 0x40
50 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type)
52 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
55 spin_lock(&qp_table->lock);
57 qp = __mlx4_qp_lookup(dev, qpn);
59 atomic_inc(&qp->refcount);
61 spin_unlock(&qp_table->lock);
64 mlx4_dbg(dev, "Async event for none existent QP %08x\n", qpn);
68 qp->event(qp, event_type);
70 if (atomic_dec_and_test(&qp->refcount))
74 /* used for INIT/CLOSE port logic */
75 static int is_master_qp0(struct mlx4_dev *dev, struct mlx4_qp *qp, int *real_qp0, int *proxy_qp0)
77 /* this procedure is called after we already know we are on the master */
78 /* qp0 is either the proxy qp0, or the real qp0 */
79 u32 pf_proxy_offset = dev->phys_caps.base_proxy_sqpn + 8 * mlx4_master_func_num(dev);
80 *proxy_qp0 = qp->qpn >= pf_proxy_offset && qp->qpn <= pf_proxy_offset + 1;
82 *real_qp0 = qp->qpn >= dev->phys_caps.base_sqpn &&
83 qp->qpn <= dev->phys_caps.base_sqpn + 1;
85 return *real_qp0 || *proxy_qp0;
88 static int __mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
89 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
90 struct mlx4_qp_context *context,
91 enum mlx4_qp_optpar optpar,
92 int sqd_event, struct mlx4_qp *qp, int native)
94 static const u16 op[MLX4_QP_NUM_STATE][MLX4_QP_NUM_STATE] = {
95 [MLX4_QP_STATE_RST] = {
96 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
97 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
98 [MLX4_QP_STATE_INIT] = MLX4_CMD_RST2INIT_QP,
100 [MLX4_QP_STATE_INIT] = {
101 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
102 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
103 [MLX4_QP_STATE_INIT] = MLX4_CMD_INIT2INIT_QP,
104 [MLX4_QP_STATE_RTR] = MLX4_CMD_INIT2RTR_QP,
106 [MLX4_QP_STATE_RTR] = {
107 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
108 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
109 [MLX4_QP_STATE_RTS] = MLX4_CMD_RTR2RTS_QP,
111 [MLX4_QP_STATE_RTS] = {
112 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
113 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
114 [MLX4_QP_STATE_RTS] = MLX4_CMD_RTS2RTS_QP,
115 [MLX4_QP_STATE_SQD] = MLX4_CMD_RTS2SQD_QP,
117 [MLX4_QP_STATE_SQD] = {
118 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
119 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
120 [MLX4_QP_STATE_RTS] = MLX4_CMD_SQD2RTS_QP,
121 [MLX4_QP_STATE_SQD] = MLX4_CMD_SQD2SQD_QP,
123 [MLX4_QP_STATE_SQER] = {
124 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
125 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
126 [MLX4_QP_STATE_RTS] = MLX4_CMD_SQERR2RTS_QP,
128 [MLX4_QP_STATE_ERR] = {
129 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
130 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
134 struct mlx4_priv *priv = mlx4_priv(dev);
135 struct mlx4_cmd_mailbox *mailbox;
141 if (cur_state >= MLX4_QP_NUM_STATE || new_state >= MLX4_QP_NUM_STATE ||
142 !op[cur_state][new_state])
145 if (op[cur_state][new_state] == MLX4_CMD_2RST_QP) {
146 ret = mlx4_cmd(dev, 0, qp->qpn, 2,
147 MLX4_CMD_2RST_QP, MLX4_CMD_TIME_CLASS_A, native);
148 if (mlx4_is_master(dev) && cur_state != MLX4_QP_STATE_ERR &&
149 cur_state != MLX4_QP_STATE_RST &&
150 is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) {
151 port = (qp->qpn & 1) + 1;
153 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0;
155 priv->mfunc.master.qp0_state[port].qp0_active = 0;
160 mailbox = mlx4_alloc_cmd_mailbox(dev);
162 return PTR_ERR(mailbox);
164 if (cur_state == MLX4_QP_STATE_RST && new_state == MLX4_QP_STATE_INIT) {
165 u64 mtt_addr = mlx4_mtt_addr(dev, mtt);
166 context->mtt_base_addr_h = mtt_addr >> 32;
167 context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
168 context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
171 *(__be32 *) mailbox->buf = cpu_to_be32(optpar);
172 memcpy(mailbox->buf + 8, context, sizeof *context);
174 ((struct mlx4_qp_context *) (mailbox->buf + 8))->local_qpn =
175 cpu_to_be32(qp->qpn);
177 ret = mlx4_cmd(dev, mailbox->dma,
178 qp->qpn | (!!sqd_event << 31),
179 new_state == MLX4_QP_STATE_RST ? 2 : 0,
180 op[cur_state][new_state], MLX4_CMD_TIME_CLASS_C, native);
182 if (mlx4_is_master(dev) && is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) {
183 port = (qp->qpn & 1) + 1;
184 if (cur_state != MLX4_QP_STATE_ERR &&
185 cur_state != MLX4_QP_STATE_RST &&
186 new_state == MLX4_QP_STATE_ERR) {
188 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0;
190 priv->mfunc.master.qp0_state[port].qp0_active = 0;
191 } else if (new_state == MLX4_QP_STATE_RTR) {
193 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 1;
195 priv->mfunc.master.qp0_state[port].qp0_active = 1;
199 mlx4_free_cmd_mailbox(dev, mailbox);
203 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
204 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
205 struct mlx4_qp_context *context,
206 enum mlx4_qp_optpar optpar,
207 int sqd_event, struct mlx4_qp *qp)
209 return __mlx4_qp_modify(dev, mtt, cur_state, new_state, context,
210 optpar, sqd_event, qp, 0);
212 EXPORT_SYMBOL_GPL(mlx4_qp_modify);
214 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
217 struct mlx4_priv *priv = mlx4_priv(dev);
218 struct mlx4_qp_table *qp_table = &priv->qp_table;
220 if (cnt > MLX4_MAX_BF_QP_RANGE && bf_qp)
223 *base = mlx4_bitmap_alloc_range(&qp_table->bitmap, cnt, align,
224 bf_qp ? MLX4_BF_QP_SKIP_MASK : 0);
231 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
238 if (mlx4_is_mfunc(dev)) {
239 set_param_l(&in_param, (((!!bf_qp) << 31) | (u32)cnt));
240 set_param_h(&in_param, align);
241 err = mlx4_cmd_imm(dev, in_param, &out_param,
242 RES_QP, RES_OP_RESERVE,
244 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
248 *base = get_param_l(&out_param);
251 return __mlx4_qp_reserve_range(dev, cnt, align, base, bf_qp);
253 EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range);
255 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
257 struct mlx4_priv *priv = mlx4_priv(dev);
258 struct mlx4_qp_table *qp_table = &priv->qp_table;
260 if (mlx4_is_qp_reserved(dev, (u32) base_qpn))
262 mlx4_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt);
265 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
270 if (mlx4_is_mfunc(dev)) {
271 set_param_l(&in_param, base_qpn);
272 set_param_h(&in_param, cnt);
273 err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE,
275 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
277 mlx4_warn(dev, "Failed to release qp range"
278 " base:%d cnt:%d\n", base_qpn, cnt);
281 __mlx4_qp_release_range(dev, base_qpn, cnt);
283 EXPORT_SYMBOL_GPL(mlx4_qp_release_range);
285 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn)
287 struct mlx4_priv *priv = mlx4_priv(dev);
288 struct mlx4_qp_table *qp_table = &priv->qp_table;
291 err = mlx4_table_get(dev, &qp_table->qp_table, qpn);
295 err = mlx4_table_get(dev, &qp_table->auxc_table, qpn);
299 err = mlx4_table_get(dev, &qp_table->altc_table, qpn);
303 err = mlx4_table_get(dev, &qp_table->rdmarc_table, qpn);
307 err = mlx4_table_get(dev, &qp_table->cmpt_table, qpn);
314 mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
317 mlx4_table_put(dev, &qp_table->altc_table, qpn);
320 mlx4_table_put(dev, &qp_table->auxc_table, qpn);
323 mlx4_table_put(dev, &qp_table->qp_table, qpn);
329 static int mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn)
333 if (mlx4_is_mfunc(dev)) {
334 set_param_l(¶m, qpn);
335 return mlx4_cmd_imm(dev, param, ¶m, RES_QP, RES_OP_MAP_ICM,
336 MLX4_CMD_ALLOC_RES, MLX4_CMD_TIME_CLASS_A,
339 return __mlx4_qp_alloc_icm(dev, qpn);
342 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
344 struct mlx4_priv *priv = mlx4_priv(dev);
345 struct mlx4_qp_table *qp_table = &priv->qp_table;
347 mlx4_table_put(dev, &qp_table->cmpt_table, qpn);
348 mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
349 mlx4_table_put(dev, &qp_table->altc_table, qpn);
350 mlx4_table_put(dev, &qp_table->auxc_table, qpn);
351 mlx4_table_put(dev, &qp_table->qp_table, qpn);
354 static void mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
358 if (mlx4_is_mfunc(dev)) {
359 set_param_l(&in_param, qpn);
360 if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM,
361 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
363 mlx4_warn(dev, "Failed to free icm of qp:%d\n", qpn);
365 __mlx4_qp_free_icm(dev, qpn);
368 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp)
370 struct mlx4_priv *priv = mlx4_priv(dev);
371 struct mlx4_qp_table *qp_table = &priv->qp_table;
379 err = mlx4_qp_alloc_icm(dev, qpn);
383 spin_lock_irq(&qp_table->lock);
384 err = radix_tree_insert(&dev->qp_table_tree, qp->qpn &
385 (dev->caps.num_qps - 1), qp);
386 spin_unlock_irq(&qp_table->lock);
390 atomic_set(&qp->refcount, 1);
391 init_completion(&qp->free);
396 mlx4_qp_free_icm(dev, qpn);
400 EXPORT_SYMBOL_GPL(mlx4_qp_alloc);
402 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp)
404 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
407 spin_lock_irqsave(&qp_table->lock, flags);
408 radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1));
409 spin_unlock_irqrestore(&qp_table->lock, flags);
411 EXPORT_SYMBOL_GPL(mlx4_qp_remove);
413 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp)
415 if (atomic_dec_and_test(&qp->refcount))
417 wait_for_completion(&qp->free);
419 mlx4_qp_free_icm(dev, qp->qpn);
421 EXPORT_SYMBOL_GPL(mlx4_qp_free);
423 static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn)
425 return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP,
426 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
429 int mlx4_init_qp_table(struct mlx4_dev *dev)
431 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
433 int reserved_from_top = 0;
434 int reserved_from_bot;
437 spin_lock_init(&qp_table->lock);
438 INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC);
439 if (mlx4_is_slave(dev))
443 * We reserve 2 extra QPs per port for the special QPs. The
444 * block of special QPs must be aligned to a multiple of 8, so
447 * We also reserve the MSB of the 24-bit QP number to indicate
448 * that a QP is an XRC QP.
450 dev->phys_caps.base_sqpn =
451 ALIGN(dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 8);
454 int sort[MLX4_NUM_QP_REGION];
456 int last_base = dev->caps.num_qps;
458 for (i = 1; i < MLX4_NUM_QP_REGION; ++i)
461 for (i = MLX4_NUM_QP_REGION; i > 0; --i) {
462 for (j = 2; j < i; ++j) {
463 if (dev->caps.reserved_qps_cnt[sort[j]] >
464 dev->caps.reserved_qps_cnt[sort[j - 1]]) {
466 sort[j] = sort[j - 1];
472 for (i = 1; i < MLX4_NUM_QP_REGION; ++i) {
473 last_base -= dev->caps.reserved_qps_cnt[sort[i]];
474 dev->caps.reserved_qps_base[sort[i]] = last_base;
476 dev->caps.reserved_qps_cnt[sort[i]];
481 /* Reserve 8 real SQPs in both native and SRIOV modes.
482 * In addition, in SRIOV mode, reserve 8 proxy SQPs per function
483 * (for all PFs and VFs), and 8 corresponding tunnel QPs.
484 * Each proxy SQP works opposite its own tunnel QP.
486 * The QPs are arranged as follows:
488 * b. All the proxy SQPs (8 per function)
489 * c. All the tunnel QPs (8 per function)
491 reserved_from_bot = mlx4_num_reserved_sqps(dev);
492 if (reserved_from_bot + reserved_from_top > dev->caps.num_qps) {
493 mlx4_err(dev, "Number of reserved QPs is higher than number "
494 "of QPs, increase the value of log_num_qp\n");
498 err = mlx4_bitmap_init(&qp_table->bitmap, dev->caps.num_qps,
499 (1 << 23) - 1, reserved_from_bot,
504 if (mlx4_is_mfunc(dev)) {
506 dev->phys_caps.base_proxy_sqpn = dev->phys_caps.base_sqpn + 8;
507 dev->phys_caps.base_tunnel_sqpn = dev->phys_caps.base_sqpn + 8 + 8 * MLX4_MFUNC_MAX;
509 /* In mfunc, calculate proxy and tunnel qp offsets for the PF here,
510 * since the PF does not call mlx4_slave_caps */
511 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
512 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
513 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
514 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
516 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
517 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
522 for (k = 0; k < dev->caps.num_ports; k++) {
523 dev->caps.qp0_proxy[k] = dev->phys_caps.base_proxy_sqpn +
524 8 * mlx4_master_func_num(dev) + k;
525 dev->caps.qp0_tunnel[k] = dev->caps.qp0_proxy[k] + 8 * MLX4_MFUNC_MAX;
526 dev->caps.qp1_proxy[k] = dev->phys_caps.base_proxy_sqpn +
527 8 * mlx4_master_func_num(dev) + MLX4_MAX_PORTS + k;
528 dev->caps.qp1_tunnel[k] = dev->caps.qp1_proxy[k] + 8 * MLX4_MFUNC_MAX;
533 err = mlx4_CONF_SPECIAL_QP(dev, dev->phys_caps.base_sqpn);
539 kfree(dev->caps.qp0_tunnel);
540 kfree(dev->caps.qp0_proxy);
541 kfree(dev->caps.qp1_tunnel);
542 kfree(dev->caps.qp1_proxy);
543 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
544 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
548 void mlx4_cleanup_qp_table(struct mlx4_dev *dev)
550 if (mlx4_is_slave(dev))
553 mlx4_CONF_SPECIAL_QP(dev, 0);
554 mlx4_bitmap_cleanup(&mlx4_priv(dev)->qp_table.bitmap);
557 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
558 struct mlx4_qp_context *context)
560 struct mlx4_cmd_mailbox *mailbox;
563 mailbox = mlx4_alloc_cmd_mailbox(dev);
565 return PTR_ERR(mailbox);
567 err = mlx4_cmd_box(dev, 0, mailbox->dma, qp->qpn, 0,
568 MLX4_CMD_QUERY_QP, MLX4_CMD_TIME_CLASS_A,
571 memcpy(context, mailbox->buf + 8, sizeof *context);
573 mlx4_free_cmd_mailbox(dev, mailbox);
576 EXPORT_SYMBOL_GPL(mlx4_qp_query);
578 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
579 struct mlx4_qp_context *context,
580 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state)
584 enum mlx4_qp_state states[] = {
591 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
592 context->flags &= cpu_to_be32(~(0xf << 28));
593 context->flags |= cpu_to_be32(states[i + 1] << 28);
594 err = mlx4_qp_modify(dev, mtt, states[i], states[i + 1],
597 mlx4_err(dev, "Failed to bring QP to state: "
598 "%d with error: %d\n",
603 *qp_state = states[i + 1];
608 EXPORT_SYMBOL_GPL(mlx4_qp_to_ready);