2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * Some hw specific parts of this pmap were derived or influenced
27 * by NetBSD's ibm4xx pmap module. More generic code is shared with
28 * a few other pmap modules from the FreeBSD tree.
34 * Kernel and user threads run within one common virtual address space
37 * Virtual address space layout:
38 * -----------------------------
39 * 0x0000_0000 - 0xafff_ffff : user process
40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
43 * 0xc100_0000 - 0xfeef_ffff : KVA
44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region
51 #include <sys/cdefs.h>
52 __FBSDID("$FreeBSD$");
54 #include <sys/param.h>
55 #include <sys/malloc.h>
59 #include <sys/queue.h>
60 #include <sys/systm.h>
61 #include <sys/kernel.h>
62 #include <sys/linker.h>
63 #include <sys/msgbuf.h>
65 #include <sys/mutex.h>
66 #include <sys/rwlock.h>
67 #include <sys/sched.h>
69 #include <sys/vmmeter.h>
72 #include <vm/vm_page.h>
73 #include <vm/vm_kern.h>
74 #include <vm/vm_pageout.h>
75 #include <vm/vm_extern.h>
76 #include <vm/vm_object.h>
77 #include <vm/vm_param.h>
78 #include <vm/vm_map.h>
79 #include <vm/vm_pager.h>
82 #include <machine/cpu.h>
83 #include <machine/pcb.h>
84 #include <machine/platform.h>
86 #include <machine/tlb.h>
87 #include <machine/spr.h>
88 #include <machine/md_var.h>
89 #include <machine/mmuvar.h>
90 #include <machine/pmap.h>
91 #include <machine/pte.h>
96 #define debugf(fmt, args...) printf(fmt, ##args)
98 #define debugf(fmt, args...)
101 #define TODO panic("%s: not implemented", __func__);
103 extern struct mtx sched_lock;
105 extern int dumpsys_minidump;
107 extern unsigned char _etext[];
108 extern unsigned char _end[];
110 extern uint32_t *bootinfo;
113 extern uint32_t bp_ntlb1s;
116 vm_paddr_t ccsrbar_pa;
118 vm_offset_t kernstart;
121 /* Message buffer and tables. */
122 static vm_offset_t data_start;
123 static vm_size_t data_end;
125 /* Phys/avail memory regions. */
126 static struct mem_region *availmem_regions;
127 static int availmem_regions_sz;
128 static struct mem_region *physmem_regions;
129 static int physmem_regions_sz;
131 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
132 static vm_offset_t zero_page_va;
133 static struct mtx zero_page_mutex;
135 static struct mtx tlbivax_mutex;
138 * Reserved KVA space for mmu_booke_zero_page_idle. This is used
139 * by idle thred only, no lock required.
141 static vm_offset_t zero_page_idle_va;
143 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
144 static vm_offset_t copy_page_src_va;
145 static vm_offset_t copy_page_dst_va;
146 static struct mtx copy_page_mutex;
148 /**************************************************************************/
150 /**************************************************************************/
152 static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t,
153 vm_prot_t, boolean_t);
155 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
156 unsigned int kernel_ptbls; /* Number of KVA ptbls. */
159 * If user pmap is processed with mmu_booke_remove and the resident count
160 * drops to 0, there are no more pages to remove, so we need not continue.
162 #define PMAP_REMOVE_DONE(pmap) \
163 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
165 extern void tid_flush(tlbtid_t);
167 /**************************************************************************/
168 /* TLB and TID handling */
169 /**************************************************************************/
171 /* Translation ID busy table */
172 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
175 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
176 * core revisions and should be read from h/w registers during early config.
178 uint32_t tlb0_entries;
180 uint32_t tlb0_entries_per_way;
182 #define TLB0_ENTRIES (tlb0_entries)
183 #define TLB0_WAYS (tlb0_ways)
184 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
186 #define TLB1_ENTRIES 16
188 /* In-ram copy of the TLB1 */
189 static tlb_entry_t tlb1[TLB1_ENTRIES];
191 /* Next free entry in the TLB1 */
192 static unsigned int tlb1_idx;
194 static tlbtid_t tid_alloc(struct pmap *);
196 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
198 static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t);
199 static void tlb1_write_entry(unsigned int);
200 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
201 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t);
203 static vm_size_t tsize2size(unsigned int);
204 static unsigned int size2tsize(vm_size_t);
205 static unsigned int ilog2(unsigned int);
207 static void set_mas4_defaults(void);
209 static inline void tlb0_flush_entry(vm_offset_t);
210 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
212 /**************************************************************************/
213 /* Page table management */
214 /**************************************************************************/
216 static struct rwlock_padalign pvh_global_lock;
218 /* Data for the pv entry allocation mechanism */
219 static uma_zone_t pvzone;
220 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
222 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
224 #ifndef PMAP_SHPGPERPROC
225 #define PMAP_SHPGPERPROC 200
228 static void ptbl_init(void);
229 static struct ptbl_buf *ptbl_buf_alloc(void);
230 static void ptbl_buf_free(struct ptbl_buf *);
231 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *);
233 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int);
234 static void ptbl_free(mmu_t, pmap_t, unsigned int);
235 static void ptbl_hold(mmu_t, pmap_t, unsigned int);
236 static int ptbl_unhold(mmu_t, pmap_t, unsigned int);
238 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t);
239 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t);
240 static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t);
241 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t);
243 static pv_entry_t pv_alloc(void);
244 static void pv_free(pv_entry_t);
245 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
246 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
248 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */
249 #define PTBL_BUFS (128 * 16)
252 TAILQ_ENTRY(ptbl_buf) link; /* list link */
253 vm_offset_t kva; /* va of mapping */
256 /* ptbl free list and a lock used for access synchronization. */
257 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist;
258 static struct mtx ptbl_buf_freelist_lock;
260 /* Base address of kva space allocated fot ptbl bufs. */
261 static vm_offset_t ptbl_buf_pool_vabase;
263 /* Pointer to ptbl_buf structures. */
264 static struct ptbl_buf *ptbl_bufs;
266 void pmap_bootstrap_ap(volatile uint32_t *);
269 * Kernel MMU interface
271 static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
272 static void mmu_booke_clear_modify(mmu_t, vm_page_t);
273 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t,
274 vm_size_t, vm_offset_t);
275 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t);
276 static void mmu_booke_copy_pages(mmu_t, vm_page_t *,
277 vm_offset_t, vm_page_t *, vm_offset_t, int);
278 static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t,
279 vm_prot_t, boolean_t);
280 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
281 vm_page_t, vm_prot_t);
282 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t,
284 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t);
285 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t,
287 static void mmu_booke_init(mmu_t);
288 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t);
289 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
290 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t);
291 static int mmu_booke_ts_referenced(mmu_t, vm_page_t);
292 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t,
294 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t,
296 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t,
297 vm_object_t, vm_pindex_t, vm_size_t);
298 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t);
299 static void mmu_booke_page_init(mmu_t, vm_page_t);
300 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t);
301 static void mmu_booke_pinit(mmu_t, pmap_t);
302 static void mmu_booke_pinit0(mmu_t, pmap_t);
303 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
305 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
306 static void mmu_booke_qremove(mmu_t, vm_offset_t, int);
307 static void mmu_booke_release(mmu_t, pmap_t);
308 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
309 static void mmu_booke_remove_all(mmu_t, vm_page_t);
310 static void mmu_booke_remove_write(mmu_t, vm_page_t);
311 static void mmu_booke_zero_page(mmu_t, vm_page_t);
312 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int);
313 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t);
314 static void mmu_booke_activate(mmu_t, struct thread *);
315 static void mmu_booke_deactivate(mmu_t, struct thread *);
316 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
317 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t);
318 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t);
319 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t);
320 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t);
321 static void mmu_booke_kremove(mmu_t, vm_offset_t);
322 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
323 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t,
325 static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *,
326 vm_size_t, vm_size_t *);
327 static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *,
328 vm_size_t, vm_offset_t);
329 static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *);
331 static mmu_method_t mmu_booke_methods[] = {
332 /* pmap dispatcher interface */
333 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring),
334 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify),
335 MMUMETHOD(mmu_copy, mmu_booke_copy),
336 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page),
337 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages),
338 MMUMETHOD(mmu_enter, mmu_booke_enter),
339 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object),
340 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick),
341 MMUMETHOD(mmu_extract, mmu_booke_extract),
342 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold),
343 MMUMETHOD(mmu_init, mmu_booke_init),
344 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified),
345 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable),
346 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced),
347 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced),
348 MMUMETHOD(mmu_map, mmu_booke_map),
349 MMUMETHOD(mmu_mincore, mmu_booke_mincore),
350 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt),
351 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick),
352 MMUMETHOD(mmu_page_init, mmu_booke_page_init),
353 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings),
354 MMUMETHOD(mmu_pinit, mmu_booke_pinit),
355 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0),
356 MMUMETHOD(mmu_protect, mmu_booke_protect),
357 MMUMETHOD(mmu_qenter, mmu_booke_qenter),
358 MMUMETHOD(mmu_qremove, mmu_booke_qremove),
359 MMUMETHOD(mmu_release, mmu_booke_release),
360 MMUMETHOD(mmu_remove, mmu_booke_remove),
361 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all),
362 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write),
363 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache),
364 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page),
365 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area),
366 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle),
367 MMUMETHOD(mmu_activate, mmu_booke_activate),
368 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate),
370 /* Internal interfaces */
371 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap),
372 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped),
373 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev),
374 MMUMETHOD(mmu_kenter, mmu_booke_kenter),
375 MMUMETHOD(mmu_kextract, mmu_booke_kextract),
376 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */
377 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev),
379 /* dumpsys() support */
380 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map),
381 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap),
382 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md),
387 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0);
398 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
401 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
402 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock);
404 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
405 ("tlb_miss_lock: tried to lock self"));
407 tlb_lock(pc->pc_booke_tlb_lock);
409 CTR1(KTR_PMAP, "%s: locked", __func__);
416 tlb_miss_unlock(void)
424 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
426 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
427 __func__, pc->pc_cpuid);
429 tlb_unlock(pc->pc_booke_tlb_lock);
431 CTR1(KTR_PMAP, "%s: unlocked", __func__);
437 /* Return number of entries in TLB0. */
439 tlb0_get_tlbconf(void)
443 tlb0_cfg = mfspr(SPR_TLB0CFG);
444 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
445 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
446 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
449 /* Initialize pool of kva ptbl buffers. */
455 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
456 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
457 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
458 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
460 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
461 TAILQ_INIT(&ptbl_buf_freelist);
463 for (i = 0; i < PTBL_BUFS; i++) {
464 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
465 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
469 /* Get a ptbl_buf from the freelist. */
470 static struct ptbl_buf *
473 struct ptbl_buf *buf;
475 mtx_lock(&ptbl_buf_freelist_lock);
476 buf = TAILQ_FIRST(&ptbl_buf_freelist);
478 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
479 mtx_unlock(&ptbl_buf_freelist_lock);
481 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
486 /* Return ptbl buff to free pool. */
488 ptbl_buf_free(struct ptbl_buf *buf)
491 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
493 mtx_lock(&ptbl_buf_freelist_lock);
494 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
495 mtx_unlock(&ptbl_buf_freelist_lock);
499 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
502 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
504 struct ptbl_buf *pbuf;
506 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
508 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
510 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
511 if (pbuf->kva == (vm_offset_t)ptbl) {
512 /* Remove from pmap ptbl buf list. */
513 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
515 /* Free corresponding ptbl buf. */
521 /* Allocate page table. */
523 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
525 vm_page_t mtbl[PTBL_PAGES];
527 struct ptbl_buf *pbuf;
532 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
533 (pmap == kernel_pmap), pdir_idx);
535 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
536 ("ptbl_alloc: invalid pdir_idx"));
537 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
538 ("pte_alloc: valid ptbl entry exists!"));
540 pbuf = ptbl_buf_alloc();
542 panic("pte_alloc: couldn't alloc kernel virtual memory");
544 ptbl = (pte_t *)pbuf->kva;
546 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
548 /* Allocate ptbl pages, this will sleep! */
549 for (i = 0; i < PTBL_PAGES; i++) {
550 pidx = (PTBL_PAGES * pdir_idx) + i;
551 while ((m = vm_page_alloc(NULL, pidx,
552 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
555 rw_wunlock(&pvh_global_lock);
557 rw_wlock(&pvh_global_lock);
563 /* Map allocated pages into kernel_pmap. */
564 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES);
566 /* Zero whole ptbl. */
567 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE);
569 /* Add pbuf to the pmap ptbl bufs list. */
570 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
575 /* Free ptbl pages and invalidate pdir entry. */
577 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
585 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
586 (pmap == kernel_pmap), pdir_idx);
588 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
589 ("ptbl_free: invalid pdir_idx"));
591 ptbl = pmap->pm_pdir[pdir_idx];
593 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
595 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
598 * Invalidate the pdir entry as soon as possible, so that other CPUs
599 * don't attempt to look up the page tables we are releasing.
601 mtx_lock_spin(&tlbivax_mutex);
604 pmap->pm_pdir[pdir_idx] = NULL;
607 mtx_unlock_spin(&tlbivax_mutex);
609 for (i = 0; i < PTBL_PAGES; i++) {
610 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
611 pa = pte_vatopa(mmu, kernel_pmap, va);
612 m = PHYS_TO_VM_PAGE(pa);
613 vm_page_free_zero(m);
614 atomic_subtract_int(&cnt.v_wire_count, 1);
615 mmu_booke_kremove(mmu, va);
618 ptbl_free_pmap_ptbl(pmap, ptbl);
622 * Decrement ptbl pages hold count and attempt to free ptbl pages.
623 * Called when removing pte entry from ptbl.
625 * Return 1 if ptbl pages were freed.
628 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
635 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
636 (pmap == kernel_pmap), pdir_idx);
638 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
639 ("ptbl_unhold: invalid pdir_idx"));
640 KASSERT((pmap != kernel_pmap),
641 ("ptbl_unhold: unholding kernel ptbl!"));
643 ptbl = pmap->pm_pdir[pdir_idx];
645 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
646 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
647 ("ptbl_unhold: non kva ptbl"));
649 /* decrement hold count */
650 for (i = 0; i < PTBL_PAGES; i++) {
651 pa = pte_vatopa(mmu, kernel_pmap,
652 (vm_offset_t)ptbl + (i * PAGE_SIZE));
653 m = PHYS_TO_VM_PAGE(pa);
658 * Free ptbl pages if there are no pte etries in this ptbl.
659 * wire_count has the same value for all ptbl pages, so check the last
662 if (m->wire_count == 0) {
663 ptbl_free(mmu, pmap, pdir_idx);
665 //debugf("ptbl_unhold: e (freed ptbl)\n");
673 * Increment hold count for ptbl pages. This routine is used when a new pte
674 * entry is being inserted into the ptbl.
677 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
684 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
687 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
688 ("ptbl_hold: invalid pdir_idx"));
689 KASSERT((pmap != kernel_pmap),
690 ("ptbl_hold: holding kernel ptbl!"));
692 ptbl = pmap->pm_pdir[pdir_idx];
694 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
696 for (i = 0; i < PTBL_PAGES; i++) {
697 pa = pte_vatopa(mmu, kernel_pmap,
698 (vm_offset_t)ptbl + (i * PAGE_SIZE));
699 m = PHYS_TO_VM_PAGE(pa);
704 /* Allocate pv_entry structure. */
711 if (pv_entry_count > pv_entry_high_water)
713 pv = uma_zalloc(pvzone, M_NOWAIT);
718 /* Free pv_entry structure. */
720 pv_free(pv_entry_t pve)
724 uma_zfree(pvzone, pve);
728 /* Allocate and initialize pv_entry structure. */
730 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
734 //int su = (pmap == kernel_pmap);
735 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
736 // (u_int32_t)pmap, va, (u_int32_t)m);
740 panic("pv_insert: no pv entries!");
746 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
747 rw_assert(&pvh_global_lock, RA_WLOCKED);
749 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
751 //debugf("pv_insert: e\n");
754 /* Destroy pv entry. */
756 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
760 //int su = (pmap == kernel_pmap);
761 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
763 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
764 rw_assert(&pvh_global_lock, RA_WLOCKED);
767 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
768 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
769 /* remove from pv_list */
770 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
771 if (TAILQ_EMPTY(&m->md.pv_list))
772 vm_page_aflag_clear(m, PGA_WRITEABLE);
774 /* free pv entry struct */
780 //debugf("pv_remove: e\n");
784 * Clean pte entry, try to free page table page if requested.
786 * Return 1 if ptbl pages were freed, otherwise return 0.
789 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags)
791 unsigned int pdir_idx = PDIR_IDX(va);
792 unsigned int ptbl_idx = PTBL_IDX(va);
797 //int su = (pmap == kernel_pmap);
798 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
799 // su, (u_int32_t)pmap, va, flags);
801 ptbl = pmap->pm_pdir[pdir_idx];
802 KASSERT(ptbl, ("pte_remove: null ptbl"));
804 pte = &ptbl[ptbl_idx];
806 if (pte == NULL || !PTE_ISVALID(pte))
809 if (PTE_ISWIRED(pte))
810 pmap->pm_stats.wired_count--;
812 /* Handle managed entry. */
813 if (PTE_ISMANAGED(pte)) {
814 /* Get vm_page_t for mapped pte. */
815 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
817 if (PTE_ISMODIFIED(pte))
820 if (PTE_ISREFERENCED(pte))
821 vm_page_aflag_set(m, PGA_REFERENCED);
823 pv_remove(pmap, va, m);
826 mtx_lock_spin(&tlbivax_mutex);
829 tlb0_flush_entry(va);
834 mtx_unlock_spin(&tlbivax_mutex);
836 pmap->pm_stats.resident_count--;
838 if (flags & PTBL_UNHOLD) {
839 //debugf("pte_remove: e (unhold)\n");
840 return (ptbl_unhold(mmu, pmap, pdir_idx));
843 //debugf("pte_remove: e\n");
848 * Insert PTE for a given page and virtual address.
851 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags)
853 unsigned int pdir_idx = PDIR_IDX(va);
854 unsigned int ptbl_idx = PTBL_IDX(va);
857 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
858 pmap == kernel_pmap, pmap, va);
860 /* Get the page table pointer. */
861 ptbl = pmap->pm_pdir[pdir_idx];
864 /* Allocate page table pages. */
865 ptbl = ptbl_alloc(mmu, pmap, pdir_idx);
868 * Check if there is valid mapping for requested
869 * va, if there is, remove it.
871 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
872 if (PTE_ISVALID(pte)) {
873 pte_remove(mmu, pmap, va, PTBL_HOLD);
876 * pte is not used, increment hold count
879 if (pmap != kernel_pmap)
880 ptbl_hold(mmu, pmap, pdir_idx);
885 * Insert pv_entry into pv_list for mapped page if part of managed
888 if ((m->oflags & VPO_UNMANAGED) == 0) {
889 flags |= PTE_MANAGED;
891 /* Create and insert pv entry. */
892 pv_insert(pmap, va, m);
895 pmap->pm_stats.resident_count++;
897 mtx_lock_spin(&tlbivax_mutex);
900 tlb0_flush_entry(va);
901 if (pmap->pm_pdir[pdir_idx] == NULL) {
903 * If we just allocated a new page table, hook it in
906 pmap->pm_pdir[pdir_idx] = ptbl;
908 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]);
909 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK;
910 pte->flags |= (PTE_VALID | flags);
913 mtx_unlock_spin(&tlbivax_mutex);
916 /* Return the pa for the given pmap/va. */
918 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
923 pte = pte_find(mmu, pmap, va);
924 if ((pte != NULL) && PTE_ISVALID(pte))
925 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
929 /* Get a pointer to a PTE in a page table. */
931 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
933 unsigned int pdir_idx = PDIR_IDX(va);
934 unsigned int ptbl_idx = PTBL_IDX(va);
936 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
938 if (pmap->pm_pdir[pdir_idx])
939 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
944 /**************************************************************************/
946 /**************************************************************************/
949 * This is called during booke_init, before the system is really initialized.
952 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
954 vm_offset_t phys_kernelend;
955 struct mem_region *mp, *mp1;
958 u_int phys_avail_count;
959 vm_size_t physsz, hwphyssz, kstack0_sz;
960 vm_offset_t kernel_pdir, kstack0, va;
961 vm_paddr_t kstack0_phys;
965 debugf("mmu_booke_bootstrap: entered\n");
967 /* Initialize invalidation mutex */
968 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
970 /* Read TLB0 size and associativity. */
974 * Align kernel start and end address (kernel image).
975 * Note that kernel end does not necessarily relate to kernsize.
976 * kernsize is the size of the kernel that is actually mapped.
977 * Also note that "start - 1" is deliberate. With SMP, the
978 * entry point is exactly a page from the actual load address.
979 * As such, trunc_page() has no effect and we're off by a page.
980 * Since we always have the ELF header between the load address
981 * and the entry point, we can safely subtract 1 to compensate.
983 kernstart = trunc_page(start - 1);
984 data_start = round_page(kernelend);
985 data_end = data_start;
988 * Addresses of preloaded modules (like file systems) use
989 * physical addresses. Make sure we relocate those into
992 preload_addr_relocate = kernstart - kernload;
994 /* Allocate the dynamic per-cpu area. */
995 dpcpu = (void *)data_end;
996 data_end += DPCPU_SIZE;
998 /* Allocate space for the message buffer. */
999 msgbufp = (struct msgbuf *)data_end;
1000 data_end += msgbufsize;
1001 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp,
1004 data_end = round_page(data_end);
1006 /* Allocate space for ptbl_bufs. */
1007 ptbl_bufs = (struct ptbl_buf *)data_end;
1008 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
1009 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs,
1012 data_end = round_page(data_end);
1014 /* Allocate PTE tables for kernel KVA. */
1015 kernel_pdir = data_end;
1016 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS +
1017 PDIR_SIZE - 1) / PDIR_SIZE;
1018 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
1019 debugf(" kernel ptbls: %d\n", kernel_ptbls);
1020 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end);
1022 debugf(" data_end: 0x%08x\n", data_end);
1023 if (data_end - kernstart > kernsize) {
1024 kernsize += tlb1_mapin_region(kernstart + kernsize,
1025 kernload + kernsize, (data_end - kernstart) - kernsize);
1027 data_end = kernstart + kernsize;
1028 debugf(" updated data_end: 0x%08x\n", data_end);
1031 * Clear the structures - note we can only do it safely after the
1032 * possible additional TLB1 translations are in place (above) so that
1033 * all range up to the currently calculated 'data_end' is covered.
1035 dpcpu_init(dpcpu, 0);
1036 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE);
1037 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1039 /*******************************************************/
1040 /* Set the start and end of kva. */
1041 /*******************************************************/
1042 virtual_avail = round_page(data_end);
1043 virtual_end = VM_MAX_KERNEL_ADDRESS;
1045 /* Allocate KVA space for page zero/copy operations. */
1046 zero_page_va = virtual_avail;
1047 virtual_avail += PAGE_SIZE;
1048 zero_page_idle_va = virtual_avail;
1049 virtual_avail += PAGE_SIZE;
1050 copy_page_src_va = virtual_avail;
1051 virtual_avail += PAGE_SIZE;
1052 copy_page_dst_va = virtual_avail;
1053 virtual_avail += PAGE_SIZE;
1054 debugf("zero_page_va = 0x%08x\n", zero_page_va);
1055 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va);
1056 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va);
1057 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va);
1059 /* Initialize page zero/copy mutexes. */
1060 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
1061 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
1063 /* Allocate KVA space for ptbl bufs. */
1064 ptbl_buf_pool_vabase = virtual_avail;
1065 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
1066 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n",
1067 ptbl_buf_pool_vabase, virtual_avail);
1069 /* Calculate corresponding physical addresses for the kernel region. */
1070 phys_kernelend = kernload + kernsize;
1071 debugf("kernel image and allocated data:\n");
1072 debugf(" kernload = 0x%08x\n", kernload);
1073 debugf(" kernstart = 0x%08x\n", kernstart);
1074 debugf(" kernsize = 0x%08x\n", kernsize);
1076 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz)
1077 panic("mmu_booke_bootstrap: phys_avail too small");
1080 * Remove kernel physical address range from avail regions list. Page
1081 * align all regions. Non-page aligned memory isn't very interesting
1082 * to us. Also, sort the entries for ascending addresses.
1085 /* Retrieve phys/avail mem regions */
1086 mem_regions(&physmem_regions, &physmem_regions_sz,
1087 &availmem_regions, &availmem_regions_sz);
1089 cnt = availmem_regions_sz;
1090 debugf("processing avail regions:\n");
1091 for (mp = availmem_regions; mp->mr_size; mp++) {
1093 e = mp->mr_start + mp->mr_size;
1094 debugf(" %08x-%08x -> ", s, e);
1095 /* Check whether this region holds all of the kernel. */
1096 if (s < kernload && e > phys_kernelend) {
1097 availmem_regions[cnt].mr_start = phys_kernelend;
1098 availmem_regions[cnt++].mr_size = e - phys_kernelend;
1101 /* Look whether this regions starts within the kernel. */
1102 if (s >= kernload && s < phys_kernelend) {
1103 if (e <= phys_kernelend)
1107 /* Now look whether this region ends within the kernel. */
1108 if (e > kernload && e <= phys_kernelend) {
1113 /* Now page align the start and size of the region. */
1119 debugf("%08x-%08x = %x\n", s, e, sz);
1121 /* Check whether some memory is left here. */
1125 (cnt - (mp - availmem_regions)) * sizeof(*mp));
1131 /* Do an insertion sort. */
1132 for (mp1 = availmem_regions; mp1 < mp; mp1++)
1133 if (s < mp1->mr_start)
1136 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
1144 availmem_regions_sz = cnt;
1146 /*******************************************************/
1147 /* Steal physical memory for kernel stack from the end */
1148 /* of the first avail region */
1149 /*******************************************************/
1150 kstack0_sz = KSTACK_PAGES * PAGE_SIZE;
1151 kstack0_phys = availmem_regions[0].mr_start +
1152 availmem_regions[0].mr_size;
1153 kstack0_phys -= kstack0_sz;
1154 availmem_regions[0].mr_size -= kstack0_sz;
1156 /*******************************************************/
1157 /* Fill in phys_avail table, based on availmem_regions */
1158 /*******************************************************/
1159 phys_avail_count = 0;
1162 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
1164 debugf("fill in phys_avail:\n");
1165 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
1167 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n",
1168 availmem_regions[i].mr_start,
1169 availmem_regions[i].mr_start +
1170 availmem_regions[i].mr_size,
1171 availmem_regions[i].mr_size);
1173 if (hwphyssz != 0 &&
1174 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
1175 debugf(" hw.physmem adjust\n");
1176 if (physsz < hwphyssz) {
1177 phys_avail[j] = availmem_regions[i].mr_start;
1179 availmem_regions[i].mr_start +
1187 phys_avail[j] = availmem_regions[i].mr_start;
1188 phys_avail[j + 1] = availmem_regions[i].mr_start +
1189 availmem_regions[i].mr_size;
1191 physsz += availmem_regions[i].mr_size;
1193 physmem = btoc(physsz);
1195 /* Calculate the last available physical address. */
1196 for (i = 0; phys_avail[i + 2] != 0; i += 2)
1198 Maxmem = powerpc_btop(phys_avail[i + 1]);
1200 debugf("Maxmem = 0x%08lx\n", Maxmem);
1201 debugf("phys_avail_count = %d\n", phys_avail_count);
1202 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem,
1205 /*******************************************************/
1206 /* Initialize (statically allocated) kernel pmap. */
1207 /*******************************************************/
1208 PMAP_LOCK_INIT(kernel_pmap);
1209 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
1211 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap);
1212 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls);
1213 debugf("kernel pdir range: 0x%08x - 0x%08x\n",
1214 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1);
1216 /* Initialize kernel pdir */
1217 for (i = 0; i < kernel_ptbls; i++)
1218 kernel_pmap->pm_pdir[kptbl_min + i] =
1219 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES));
1221 for (i = 0; i < MAXCPU; i++) {
1222 kernel_pmap->pm_tid[i] = TID_KERNEL;
1224 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
1225 tidbusy[i][0] = kernel_pmap;
1229 * Fill in PTEs covering kernel code and data. They are not required
1230 * for address translation, as this area is covered by static TLB1
1231 * entries, but for pte_vatopa() to work correctly with kernel area
1234 for (va = kernstart; va < data_end; va += PAGE_SIZE) {
1235 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
1236 pte->rpn = kernload + (va - kernstart);
1237 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1240 /* Mark kernel_pmap active on all CPUs */
1241 CPU_FILL(&kernel_pmap->pm_active);
1244 * Initialize the global pv list lock.
1246 rw_init(&pvh_global_lock, "pmap pv global");
1248 /*******************************************************/
1250 /*******************************************************/
1252 /* Enter kstack0 into kernel map, provide guard page */
1253 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1254 thread0.td_kstack = kstack0;
1255 thread0.td_kstack_pages = KSTACK_PAGES;
1257 debugf("kstack_sz = 0x%08x\n", kstack0_sz);
1258 debugf("kstack0_phys at 0x%08x - 0x%08x\n",
1259 kstack0_phys, kstack0_phys + kstack0_sz);
1260 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz);
1262 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
1263 for (i = 0; i < KSTACK_PAGES; i++) {
1264 mmu_booke_kenter(mmu, kstack0, kstack0_phys);
1265 kstack0 += PAGE_SIZE;
1266 kstack0_phys += PAGE_SIZE;
1269 debugf("virtual_avail = %08x\n", virtual_avail);
1270 debugf("virtual_end = %08x\n", virtual_end);
1272 debugf("mmu_booke_bootstrap: exit\n");
1276 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
1281 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
1282 * have the snapshot of its contents in the s/w tlb1[] table, so use
1283 * these values directly to (re)program AP's TLB1 hardware.
1285 for (i = bp_ntlb1s; i < tlb1_idx; i++) {
1286 /* Skip invalid entries */
1287 if (!(tlb1[i].mas1 & MAS1_VALID))
1290 tlb1_write_entry(i);
1293 set_mas4_defaults();
1297 * Get the physical page address for the given pmap/virtual address.
1300 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1305 pa = pte_vatopa(mmu, pmap, va);
1312 * Extract the physical page address associated with the given
1313 * kernel virtual address.
1316 mmu_booke_kextract(mmu_t mmu, vm_offset_t va)
1319 return (pte_vatopa(mmu, kernel_pmap, va));
1323 * Initialize the pmap module.
1324 * Called by vm_init, to initialize any structures that the pmap
1325 * system needs to map virtual memory.
1328 mmu_booke_init(mmu_t mmu)
1330 int shpgperproc = PMAP_SHPGPERPROC;
1333 * Initialize the address space (zone) for the pv entries. Set a
1334 * high water mark so that the system can recover from excessive
1335 * numbers of pv entries.
1337 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1338 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1340 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1341 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1343 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1344 pv_entry_high_water = 9 * (pv_entry_max / 10);
1346 uma_zone_reserve_kva(pvzone, pv_entry_max);
1348 /* Pre-fill pvzone with initial number of pv entries. */
1349 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1351 /* Initialize ptbl allocation. */
1356 * Map a list of wired pages into kernel virtual address space. This is
1357 * intended for temporary mappings which do not need page modification or
1358 * references recorded. Existing mappings in the region are overwritten.
1361 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1366 while (count-- > 0) {
1367 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1374 * Remove page mappings from kernel virtual address space. Intended for
1375 * temporary mappings entered by mmu_booke_qenter.
1378 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count)
1383 while (count-- > 0) {
1384 mmu_booke_kremove(mmu, va);
1390 * Map a wired page into kernel virtual address space.
1393 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1395 unsigned int pdir_idx = PDIR_IDX(va);
1396 unsigned int ptbl_idx = PTBL_IDX(va);
1400 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1401 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1403 flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
1405 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1407 mtx_lock_spin(&tlbivax_mutex);
1410 if (PTE_ISVALID(pte)) {
1412 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1414 /* Flush entry from TLB0 */
1415 tlb0_flush_entry(va);
1418 pte->rpn = pa & ~PTE_PA_MASK;
1421 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1422 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1423 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1425 /* Flush the real memory from the instruction cache. */
1426 if ((flags & (PTE_I | PTE_G)) == 0) {
1427 __syncicache((void *)va, PAGE_SIZE);
1431 mtx_unlock_spin(&tlbivax_mutex);
1435 * Remove a page from kernel page table.
1438 mmu_booke_kremove(mmu_t mmu, vm_offset_t va)
1440 unsigned int pdir_idx = PDIR_IDX(va);
1441 unsigned int ptbl_idx = PTBL_IDX(va);
1444 // CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va));
1446 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1447 (va <= VM_MAX_KERNEL_ADDRESS)),
1448 ("mmu_booke_kremove: invalid va"));
1450 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1452 if (!PTE_ISVALID(pte)) {
1454 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1459 mtx_lock_spin(&tlbivax_mutex);
1462 /* Invalidate entry in TLB0, update PTE. */
1463 tlb0_flush_entry(va);
1468 mtx_unlock_spin(&tlbivax_mutex);
1472 * Initialize pmap associated with process 0.
1475 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap)
1478 PMAP_LOCK_INIT(pmap);
1479 mmu_booke_pinit(mmu, pmap);
1480 PCPU_SET(curpmap, pmap);
1484 * Initialize a preallocated and zeroed pmap structure,
1485 * such as one in a vmspace structure.
1488 mmu_booke_pinit(mmu_t mmu, pmap_t pmap)
1492 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
1493 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
1495 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
1497 for (i = 0; i < MAXCPU; i++)
1498 pmap->pm_tid[i] = TID_NONE;
1499 CPU_ZERO(&kernel_pmap->pm_active);
1500 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1501 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
1502 TAILQ_INIT(&pmap->pm_ptbl_list);
1506 * Release any resources held by the given physical map.
1507 * Called when a pmap initialized by mmu_booke_pinit is being released.
1508 * Should only be called if the map contains no valid mappings.
1511 mmu_booke_release(mmu_t mmu, pmap_t pmap)
1514 KASSERT(pmap->pm_stats.resident_count == 0,
1515 ("pmap_release: pmap resident count %ld != 0",
1516 pmap->pm_stats.resident_count));
1520 * Insert the given physical page at the specified virtual address in the
1521 * target physical map with the protection requested. If specified the page
1522 * will be wired down.
1525 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1526 vm_prot_t prot, boolean_t wired)
1529 rw_wlock(&pvh_global_lock);
1531 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired);
1532 rw_wunlock(&pvh_global_lock);
1537 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1538 vm_prot_t prot, boolean_t wired)
1545 pa = VM_PAGE_TO_PHYS(m);
1546 su = (pmap == kernel_pmap);
1549 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1550 // "pa=0x%08x prot=0x%08x wired=%d)\n",
1551 // (u_int32_t)pmap, su, pmap->pm_tid,
1552 // (u_int32_t)m, va, pa, prot, wired);
1555 KASSERT(((va >= virtual_avail) &&
1556 (va <= VM_MAX_KERNEL_ADDRESS)),
1557 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1559 KASSERT((va <= VM_MAXUSER_ADDRESS),
1560 ("mmu_booke_enter_locked: user pmap, non user va"));
1562 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1563 VM_OBJECT_ASSERT_LOCKED(m->object);
1565 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1568 * If there is an existing mapping, and the physical address has not
1569 * changed, must be protection or wiring change.
1571 if (((pte = pte_find(mmu, pmap, va)) != NULL) &&
1572 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1575 * Before actually updating pte->flags we calculate and
1576 * prepare its new value in a helper var.
1579 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1581 /* Wiring change, just update stats. */
1583 if (!PTE_ISWIRED(pte)) {
1585 pmap->pm_stats.wired_count++;
1588 if (PTE_ISWIRED(pte)) {
1589 flags &= ~PTE_WIRED;
1590 pmap->pm_stats.wired_count--;
1594 if (prot & VM_PROT_WRITE) {
1595 /* Add write permissions. */
1600 if ((flags & PTE_MANAGED) != 0)
1601 vm_page_aflag_set(m, PGA_WRITEABLE);
1603 /* Handle modified pages, sense modify status. */
1606 * The PTE_MODIFIED flag could be set by underlying
1607 * TLB misses since we last read it (above), possibly
1608 * other CPUs could update it so we check in the PTE
1609 * directly rather than rely on that saved local flags
1612 if (PTE_ISMODIFIED(pte))
1616 if (prot & VM_PROT_EXECUTE) {
1622 * Check existing flags for execute permissions: if we
1623 * are turning execute permissions on, icache should
1626 if ((pte->flags & (PTE_UX | PTE_SX)) == 0)
1630 flags &= ~PTE_REFERENCED;
1633 * The new flags value is all calculated -- only now actually
1636 mtx_lock_spin(&tlbivax_mutex);
1639 tlb0_flush_entry(va);
1643 mtx_unlock_spin(&tlbivax_mutex);
1647 * If there is an existing mapping, but it's for a different
1648 * physical address, pte_enter() will delete the old mapping.
1650 //if ((pte != NULL) && PTE_ISVALID(pte))
1651 // debugf("mmu_booke_enter_locked: replace\n");
1653 // debugf("mmu_booke_enter_locked: new\n");
1655 /* Now set up the flags and install the new mapping. */
1656 flags = (PTE_SR | PTE_VALID);
1662 if (prot & VM_PROT_WRITE) {
1667 if ((m->oflags & VPO_UNMANAGED) == 0)
1668 vm_page_aflag_set(m, PGA_WRITEABLE);
1671 if (prot & VM_PROT_EXECUTE) {
1677 /* If its wired update stats. */
1679 pmap->pm_stats.wired_count++;
1683 pte_enter(mmu, pmap, m, va, flags);
1685 /* Flush the real memory from the instruction cache. */
1686 if (prot & VM_PROT_EXECUTE)
1690 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1691 __syncicache((void *)va, PAGE_SIZE);
1697 * Maps a sequence of resident pages belonging to the same object.
1698 * The sequence begins with the given page m_start. This page is
1699 * mapped at the given virtual address start. Each subsequent page is
1700 * mapped at a virtual address that is offset from start by the same
1701 * amount as the page is offset from m_start within the object. The
1702 * last page in the sequence is the page with the largest offset from
1703 * m_start that can be mapped at a virtual address less than the given
1704 * virtual address end. Not every virtual page between start and end
1705 * is mapped; only those for which a resident page exists with the
1706 * corresponding offset from m_start are mapped.
1709 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start,
1710 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1713 vm_pindex_t diff, psize;
1715 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1717 psize = atop(end - start);
1719 rw_wlock(&pvh_global_lock);
1721 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1722 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m,
1723 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1724 m = TAILQ_NEXT(m, listq);
1726 rw_wunlock(&pvh_global_lock);
1731 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1735 rw_wlock(&pvh_global_lock);
1737 mmu_booke_enter_locked(mmu, pmap, va, m,
1738 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1739 rw_wunlock(&pvh_global_lock);
1744 * Remove the given range of addresses from the specified map.
1746 * It is assumed that the start and end are properly rounded to the page size.
1749 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1754 int su = (pmap == kernel_pmap);
1756 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1757 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1760 KASSERT(((va >= virtual_avail) &&
1761 (va <= VM_MAX_KERNEL_ADDRESS)),
1762 ("mmu_booke_remove: kernel pmap, non kernel va"));
1764 KASSERT((va <= VM_MAXUSER_ADDRESS),
1765 ("mmu_booke_remove: user pmap, non user va"));
1768 if (PMAP_REMOVE_DONE(pmap)) {
1769 //debugf("mmu_booke_remove: e (empty)\n");
1773 hold_flag = PTBL_HOLD_FLAG(pmap);
1774 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1776 rw_wlock(&pvh_global_lock);
1778 for (; va < endva; va += PAGE_SIZE) {
1779 pte = pte_find(mmu, pmap, va);
1780 if ((pte != NULL) && PTE_ISVALID(pte))
1781 pte_remove(mmu, pmap, va, hold_flag);
1784 rw_wunlock(&pvh_global_lock);
1786 //debugf("mmu_booke_remove: e\n");
1790 * Remove physical page from all pmaps in which it resides.
1793 mmu_booke_remove_all(mmu_t mmu, vm_page_t m)
1798 rw_wlock(&pvh_global_lock);
1799 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) {
1800 pvn = TAILQ_NEXT(pv, pv_link);
1802 PMAP_LOCK(pv->pv_pmap);
1803 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1804 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag);
1805 PMAP_UNLOCK(pv->pv_pmap);
1807 vm_page_aflag_clear(m, PGA_WRITEABLE);
1808 rw_wunlock(&pvh_global_lock);
1812 * Map a range of physical addresses into kernel virtual address space.
1815 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1816 vm_paddr_t pa_end, int prot)
1818 vm_offset_t sva = *virt;
1819 vm_offset_t va = sva;
1821 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n",
1822 // sva, pa_start, pa_end);
1824 while (pa_start < pa_end) {
1825 mmu_booke_kenter(mmu, va, pa_start);
1827 pa_start += PAGE_SIZE;
1831 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va);
1836 * The pmap must be activated before it's address space can be accessed in any
1840 mmu_booke_activate(mmu_t mmu, struct thread *td)
1845 pmap = &td->td_proc->p_vmspace->vm_pmap;
1847 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)",
1848 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1850 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1852 mtx_lock_spin(&sched_lock);
1854 cpuid = PCPU_GET(cpuid);
1855 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1856 PCPU_SET(curpmap, pmap);
1858 if (pmap->pm_tid[cpuid] == TID_NONE)
1861 /* Load PID0 register with pmap tid value. */
1862 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1863 __asm __volatile("isync");
1865 mtx_unlock_spin(&sched_lock);
1867 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1868 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1872 * Deactivate the specified process's address space.
1875 mmu_booke_deactivate(mmu_t mmu, struct thread *td)
1879 pmap = &td->td_proc->p_vmspace->vm_pmap;
1881 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x",
1882 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1884 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1885 PCPU_SET(curpmap, NULL);
1889 * Copy the range specified by src_addr/len
1890 * from the source map to the range dst_addr/len
1891 * in the destination map.
1893 * This routine is only advisory and need not do anything.
1896 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap,
1897 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1903 * Set the physical protection on the specified range of this map as requested.
1906 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1913 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1914 mmu_booke_remove(mmu, pmap, sva, eva);
1918 if (prot & VM_PROT_WRITE)
1922 for (va = sva; va < eva; va += PAGE_SIZE) {
1923 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
1924 if (PTE_ISVALID(pte)) {
1925 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1927 mtx_lock_spin(&tlbivax_mutex);
1930 /* Handle modified pages. */
1931 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
1934 tlb0_flush_entry(va);
1935 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1938 mtx_unlock_spin(&tlbivax_mutex);
1946 * Clear the write and modified bits in each of the given page's mappings.
1949 mmu_booke_remove_write(mmu_t mmu, vm_page_t m)
1954 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1955 ("mmu_booke_remove_write: page %p is not managed", m));
1958 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1959 * set by another thread while the object is locked. Thus,
1960 * if PGA_WRITEABLE is clear, no page table entries need updating.
1962 VM_OBJECT_ASSERT_WLOCKED(m->object);
1963 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1965 rw_wlock(&pvh_global_lock);
1966 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1967 PMAP_LOCK(pv->pv_pmap);
1968 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) {
1969 if (PTE_ISVALID(pte)) {
1970 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1972 mtx_lock_spin(&tlbivax_mutex);
1975 /* Handle modified pages. */
1976 if (PTE_ISMODIFIED(pte))
1979 /* Flush mapping from TLB0. */
1980 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1983 mtx_unlock_spin(&tlbivax_mutex);
1986 PMAP_UNLOCK(pv->pv_pmap);
1988 vm_page_aflag_clear(m, PGA_WRITEABLE);
1989 rw_wunlock(&pvh_global_lock);
1993 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2002 va = trunc_page(va);
2003 sz = round_page(sz);
2005 rw_wlock(&pvh_global_lock);
2006 pmap = PCPU_GET(curpmap);
2007 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
2010 pte = pte_find(mmu, pm, va);
2011 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
2017 /* Create a mapping in the active pmap. */
2019 m = PHYS_TO_VM_PAGE(pa);
2021 pte_enter(mmu, pmap, m, addr,
2022 PTE_SR | PTE_VALID | PTE_UR);
2023 __syncicache((void *)addr, PAGE_SIZE);
2024 pte_remove(mmu, pmap, addr, PTBL_UNHOLD);
2027 __syncicache((void *)va, PAGE_SIZE);
2032 rw_wunlock(&pvh_global_lock);
2036 * Atomically extract and hold the physical page with the given
2037 * pmap and virtual address pair if that mapping permits the given
2041 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va,
2053 pte = pte_find(mmu, pmap, va);
2054 if ((pte != NULL) && PTE_ISVALID(pte)) {
2055 if (pmap == kernel_pmap)
2060 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) {
2061 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa))
2063 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2074 * Initialize a vm_page's machine-dependent fields.
2077 mmu_booke_page_init(mmu_t mmu, vm_page_t m)
2080 TAILQ_INIT(&m->md.pv_list);
2084 * mmu_booke_zero_page_area zeros the specified hardware page by
2085 * mapping it into virtual memory and using bzero to clear
2088 * off and size must reside within a single page.
2091 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
2095 /* XXX KASSERT off and size are within a single page? */
2097 mtx_lock(&zero_page_mutex);
2100 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2101 bzero((caddr_t)va + off, size);
2102 mmu_booke_kremove(mmu, va);
2104 mtx_unlock(&zero_page_mutex);
2108 * mmu_booke_zero_page zeros the specified hardware page.
2111 mmu_booke_zero_page(mmu_t mmu, vm_page_t m)
2114 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE);
2118 * mmu_booke_copy_page copies the specified (machine independent) page by
2119 * mapping the page into virtual memory and using memcopy to copy the page,
2120 * one machine dependent page at a time.
2123 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm)
2125 vm_offset_t sva, dva;
2127 sva = copy_page_src_va;
2128 dva = copy_page_dst_va;
2130 mtx_lock(©_page_mutex);
2131 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm));
2132 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm));
2133 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2134 mmu_booke_kremove(mmu, dva);
2135 mmu_booke_kremove(mmu, sva);
2136 mtx_unlock(©_page_mutex);
2140 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
2141 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
2144 vm_offset_t a_pg_offset, b_pg_offset;
2147 mtx_lock(©_page_mutex);
2148 while (xfersize > 0) {
2149 a_pg_offset = a_offset & PAGE_MASK;
2150 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2151 mmu_booke_kenter(mmu, copy_page_src_va,
2152 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
2153 a_cp = (char *)copy_page_src_va + a_pg_offset;
2154 b_pg_offset = b_offset & PAGE_MASK;
2155 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2156 mmu_booke_kenter(mmu, copy_page_dst_va,
2157 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
2158 b_cp = (char *)copy_page_dst_va + b_pg_offset;
2159 bcopy(a_cp, b_cp, cnt);
2160 mmu_booke_kremove(mmu, copy_page_dst_va);
2161 mmu_booke_kremove(mmu, copy_page_src_va);
2166 mtx_unlock(©_page_mutex);
2170 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it
2171 * into virtual memory and using bzero to clear its contents. This is intended
2172 * to be called from the vm_pagezero process only and outside of Giant. No
2176 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m)
2180 va = zero_page_idle_va;
2181 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2182 bzero((caddr_t)va, PAGE_SIZE);
2183 mmu_booke_kremove(mmu, va);
2187 * Return whether or not the specified physical page was modified
2188 * in any of physical maps.
2191 mmu_booke_is_modified(mmu_t mmu, vm_page_t m)
2197 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2198 ("mmu_booke_is_modified: page %p is not managed", m));
2202 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2203 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
2204 * is clear, no PTEs can be modified.
2206 VM_OBJECT_ASSERT_WLOCKED(m->object);
2207 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2209 rw_wlock(&pvh_global_lock);
2210 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2211 PMAP_LOCK(pv->pv_pmap);
2212 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2214 if (PTE_ISMODIFIED(pte))
2217 PMAP_UNLOCK(pv->pv_pmap);
2221 rw_wunlock(&pvh_global_lock);
2226 * Return whether or not the specified virtual address is eligible
2230 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr)
2237 * Return whether or not the specified physical page was referenced
2238 * in any physical maps.
2241 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m)
2247 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2248 ("mmu_booke_is_referenced: page %p is not managed", m));
2250 rw_wlock(&pvh_global_lock);
2251 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2252 PMAP_LOCK(pv->pv_pmap);
2253 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2255 if (PTE_ISREFERENCED(pte))
2258 PMAP_UNLOCK(pv->pv_pmap);
2262 rw_wunlock(&pvh_global_lock);
2267 * Clear the modify bits on the specified physical page.
2270 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m)
2275 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2276 ("mmu_booke_clear_modify: page %p is not managed", m));
2277 VM_OBJECT_ASSERT_WLOCKED(m->object);
2278 KASSERT(!vm_page_xbusied(m),
2279 ("mmu_booke_clear_modify: page %p is exclusive busied", m));
2282 * If the page is not PG_AWRITEABLE, then no PTEs can be modified.
2283 * If the object containing the page is locked and the page is not
2284 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set.
2286 if ((m->aflags & PGA_WRITEABLE) == 0)
2288 rw_wlock(&pvh_global_lock);
2289 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2290 PMAP_LOCK(pv->pv_pmap);
2291 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2293 mtx_lock_spin(&tlbivax_mutex);
2296 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
2297 tlb0_flush_entry(pv->pv_va);
2298 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
2303 mtx_unlock_spin(&tlbivax_mutex);
2305 PMAP_UNLOCK(pv->pv_pmap);
2307 rw_wunlock(&pvh_global_lock);
2311 * Return a count of reference bits for a page, clearing those bits.
2312 * It is not necessary for every reference bit to be cleared, but it
2313 * is necessary that 0 only be returned when there are truly no
2314 * reference bits set.
2316 * XXX: The exact number of bits to check and clear is a matter that
2317 * should be tested and standardized at some point in the future for
2318 * optimal aging of shared pages.
2321 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m)
2327 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2328 ("mmu_booke_ts_referenced: page %p is not managed", m));
2330 rw_wlock(&pvh_global_lock);
2331 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2332 PMAP_LOCK(pv->pv_pmap);
2333 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2335 if (PTE_ISREFERENCED(pte)) {
2336 mtx_lock_spin(&tlbivax_mutex);
2339 tlb0_flush_entry(pv->pv_va);
2340 pte->flags &= ~PTE_REFERENCED;
2343 mtx_unlock_spin(&tlbivax_mutex);
2346 PMAP_UNLOCK(pv->pv_pmap);
2351 PMAP_UNLOCK(pv->pv_pmap);
2353 rw_wunlock(&pvh_global_lock);
2358 * Change wiring attribute for a map/virtual-address pair.
2361 mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired)
2366 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
2368 if (!PTE_ISWIRED(pte)) {
2369 pte->flags |= PTE_WIRED;
2370 pmap->pm_stats.wired_count++;
2373 if (PTE_ISWIRED(pte)) {
2374 pte->flags &= ~PTE_WIRED;
2375 pmap->pm_stats.wired_count--;
2383 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
2384 * page. This count may be changed upwards or downwards in the future; it is
2385 * only necessary that true be returned for a small subset of pmaps for proper
2389 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
2395 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2396 ("mmu_booke_page_exists_quick: page %p is not managed", m));
2399 rw_wlock(&pvh_global_lock);
2400 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2401 if (pv->pv_pmap == pmap) {
2408 rw_wunlock(&pvh_global_lock);
2413 * Return the number of managed mappings to the given physical page that are
2417 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m)
2423 if ((m->oflags & VPO_UNMANAGED) != 0)
2425 rw_wlock(&pvh_global_lock);
2426 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2427 PMAP_LOCK(pv->pv_pmap);
2428 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL)
2429 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2431 PMAP_UNLOCK(pv->pv_pmap);
2433 rw_wunlock(&pvh_global_lock);
2438 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2444 * This currently does not work for entries that
2445 * overlap TLB1 entries.
2447 for (i = 0; i < tlb1_idx; i ++) {
2448 if (tlb1_iomapped(i, pa, size, &va) == 0)
2456 mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2463 /* Raw physical memory dumps don't have a virtual address. */
2464 if (md->md_vaddr == ~0UL) {
2465 /* We always map a 256MB page at 256M. */
2466 gran = 256 * 1024 * 1024;
2467 pa = md->md_paddr + ofs;
2468 ppa = pa & ~(gran - 1);
2471 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO);
2472 if (*sz > (gran - ofs))
2477 /* Minidumps are based on virtual memory addresses. */
2478 va = md->md_vaddr + ofs;
2479 if (va >= kernstart + kernsize) {
2480 gran = PAGE_SIZE - (va & PAGE_MASK);
2488 mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2492 /* Raw physical memory dumps don't have a virtual address. */
2493 if (md->md_vaddr == ~0UL) {
2495 tlb1[tlb1_idx].mas1 = 0;
2496 tlb1[tlb1_idx].mas2 = 0;
2497 tlb1[tlb1_idx].mas3 = 0;
2498 tlb1_write_entry(tlb1_idx);
2502 /* Minidumps are based on virtual memory addresses. */
2503 /* Nothing to do... */
2507 mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev)
2509 static struct pmap_md md;
2513 if (dumpsys_minidump) {
2514 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2516 /* 1st: kernel .data and .bss. */
2518 md.md_vaddr = trunc_page((uintptr_t)_etext);
2519 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2522 switch (prev->md_index) {
2524 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2526 md.md_vaddr = data_start;
2527 md.md_size = data_end - data_start;
2530 /* 3rd: kernel VM. */
2531 va = prev->md_vaddr + prev->md_size;
2532 /* Find start of next chunk (from va). */
2533 while (va < virtual_end) {
2534 /* Don't dump the buffer cache. */
2535 if (va >= kmi.buffer_sva &&
2536 va < kmi.buffer_eva) {
2537 va = kmi.buffer_eva;
2540 pte = pte_find(mmu, kernel_pmap, va);
2541 if (pte != NULL && PTE_ISVALID(pte))
2545 if (va < virtual_end) {
2548 /* Find last page in chunk. */
2549 while (va < virtual_end) {
2550 /* Don't run into the buffer cache. */
2551 if (va == kmi.buffer_sva)
2553 pte = pte_find(mmu, kernel_pmap, va);
2554 if (pte == NULL || !PTE_ISVALID(pte))
2558 md.md_size = va - md.md_vaddr;
2566 } else { /* minidumps */
2567 mem_regions(&physmem_regions, &physmem_regions_sz,
2568 &availmem_regions, &availmem_regions_sz);
2571 /* first physical chunk. */
2572 md.md_paddr = physmem_regions[0].mr_start;
2573 md.md_size = physmem_regions[0].mr_size;
2576 } else if (md.md_index < physmem_regions_sz) {
2577 md.md_paddr = physmem_regions[md.md_index].mr_start;
2578 md.md_size = physmem_regions[md.md_index].mr_size;
2582 /* There's no next physical chunk. */
2591 * Map a set of physical memory pages into the kernel virtual address space.
2592 * Return a pointer to where it is mapped. This routine is intended to be used
2593 * for mapping device memory, NOT real memory.
2596 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2603 * CCSR is premapped. Note that (pa + size - 1) is there to make sure
2604 * we don't wrap around. Devices on the local bus typically extend all
2605 * the way up to and including 0xffffffff. In that case (pa + size)
2606 * would be 0. This creates a false positive (i.e. we think it's
2607 * within the CCSR) and not create a mapping.
2609 if (pa >= ccsrbar_pa && (pa + size - 1) < (ccsrbar_pa + CCSRBAR_SIZE)) {
2610 va = CCSRBAR_VA + (pa - ccsrbar_pa);
2611 return ((void *)va);
2614 va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa);
2618 sz = 1 << (ilog2(size) & ~1);
2620 printf("Wiring VA=%x to PA=%x (size=%x), "
2621 "using TLB1[%d]\n", va, pa, sz, tlb1_idx);
2622 tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO);
2632 * 'Unmap' a range mapped by mmu_booke_mapdev().
2635 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2637 vm_offset_t base, offset;
2640 * Unmap only if this is inside kernel virtual space.
2642 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2643 base = trunc_page(va);
2644 offset = va & PAGE_MASK;
2645 size = roundup(offset + size, PAGE_SIZE);
2646 kva_free(base, size);
2651 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2652 * specified pmap. This eliminates the blast of soft faults on process startup
2653 * and immediately after an mmap.
2656 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2657 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2660 VM_OBJECT_ASSERT_WLOCKED(object);
2661 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2662 ("mmu_booke_object_init_pt: non-device object"));
2666 * Perform the pmap work for mincore.
2669 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2670 vm_paddr_t *locked_pa)
2677 /**************************************************************************/
2679 /**************************************************************************/
2682 * Allocate a TID. If necessary, steal one from someone else.
2683 * The new TID is flushed from the TLB before returning.
2686 tid_alloc(pmap_t pmap)
2691 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2693 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2695 thiscpu = PCPU_GET(cpuid);
2697 tid = PCPU_GET(tid_next);
2700 PCPU_SET(tid_next, tid + 1);
2702 /* If we are stealing TID then clear the relevant pmap's field */
2703 if (tidbusy[thiscpu][tid] != NULL) {
2705 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2707 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2709 /* Flush all entries from TLB0 matching this TID. */
2713 tidbusy[thiscpu][tid] = pmap;
2714 pmap->pm_tid[thiscpu] = tid;
2715 __asm __volatile("msync; isync");
2717 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2718 PCPU_GET(tid_next));
2723 /**************************************************************************/
2725 /**************************************************************************/
2728 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
2738 if (mas1 & MAS1_VALID)
2743 if (mas1 & MAS1_IPROT)
2748 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
2749 tid = MAS1_GETTID(mas1);
2751 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2754 size = tsize2size(tsize);
2756 debugf("%3d: (%s) [AS=%d] "
2757 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x "
2758 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n",
2759 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7);
2762 /* Convert TLB0 va and way number to tlb0[] table index. */
2763 static inline unsigned int
2764 tlb0_tableidx(vm_offset_t va, unsigned int way)
2768 idx = (way * TLB0_ENTRIES_PER_WAY);
2769 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2774 * Invalidate TLB0 entry.
2777 tlb0_flush_entry(vm_offset_t va)
2780 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2782 mtx_assert(&tlbivax_mutex, MA_OWNED);
2784 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2785 __asm __volatile("isync; msync");
2786 __asm __volatile("tlbsync; msync");
2788 CTR1(KTR_PMAP, "%s: e", __func__);
2791 /* Print out contents of the MAS registers for each TLB0 entry */
2793 tlb0_print_tlbentries(void)
2795 uint32_t mas0, mas1, mas2, mas3, mas7;
2796 int entryidx, way, idx;
2798 debugf("TLB0 entries:\n");
2799 for (way = 0; way < TLB0_WAYS; way ++)
2800 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
2802 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
2803 mtspr(SPR_MAS0, mas0);
2804 __asm __volatile("isync");
2806 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
2807 mtspr(SPR_MAS2, mas2);
2809 __asm __volatile("isync; tlbre");
2811 mas1 = mfspr(SPR_MAS1);
2812 mas2 = mfspr(SPR_MAS2);
2813 mas3 = mfspr(SPR_MAS3);
2814 mas7 = mfspr(SPR_MAS7);
2816 idx = tlb0_tableidx(mas2, way);
2817 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
2821 /**************************************************************************/
2823 /**************************************************************************/
2826 * TLB1 mapping notes:
2829 * TLB1[1] Kernel text and data.
2830 * TLB1[2-15] Additional kernel text and data mappings (if required), PCI
2831 * windows, other devices mappings.
2835 * Write given entry to TLB1 hardware.
2836 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7).
2839 tlb1_write_entry(unsigned int idx)
2841 uint32_t mas0, mas7;
2843 //debugf("tlb1_write_entry: s\n");
2845 /* Clear high order RPN bits */
2849 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2850 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0);
2852 mtspr(SPR_MAS0, mas0);
2853 __asm __volatile("isync");
2854 mtspr(SPR_MAS1, tlb1[idx].mas1);
2855 __asm __volatile("isync");
2856 mtspr(SPR_MAS2, tlb1[idx].mas2);
2857 __asm __volatile("isync");
2858 mtspr(SPR_MAS3, tlb1[idx].mas3);
2859 __asm __volatile("isync");
2860 mtspr(SPR_MAS7, mas7);
2861 __asm __volatile("isync; tlbwe; isync; msync");
2863 //debugf("tlb1_write_entry: e\n");
2867 * Return the largest uint value log such that 2^log <= num.
2870 ilog2(unsigned int num)
2874 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num));
2879 * Convert TLB TSIZE value to mapped region size.
2882 tsize2size(unsigned int tsize)
2887 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2890 return ((1 << (2 * tsize)) * 1024);
2894 * Convert region size (must be power of 4) to TLB TSIZE value.
2897 size2tsize(vm_size_t size)
2900 return (ilog2(size) / 2 - 5);
2904 * Register permanent kernel mapping in TLB1.
2906 * Entries are created starting from index 0 (current free entry is
2907 * kept in tlb1_idx) and are not supposed to be invalidated.
2910 tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size,
2916 if (tlb1_idx >= TLB1_ENTRIES) {
2917 printf("tlb1_set_entry: TLB1 full!\n");
2921 /* Convert size to TSIZE */
2922 tsize = size2tsize(size);
2924 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
2925 /* XXX TS is hard coded to 0 for now as we only use single address space */
2926 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
2928 /* XXX LOCK tlb1[] */
2930 tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
2931 tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
2932 tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags;
2934 /* Set supervisor RWX permission bits */
2935 tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
2937 tlb1_write_entry(tlb1_idx++);
2939 /* XXX UNLOCK tlb1[] */
2942 * XXX in general TLB1 updates should be propagated between CPUs,
2943 * since current design assumes to have the same TLB1 set-up on all
2950 * Map in contiguous RAM region into the TLB1 using maximum of
2951 * KERNEL_REGION_MAX_TLB_ENTRIES entries.
2953 * If necessary round up last entry size and return total size
2954 * used by all allocated entries.
2957 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
2959 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES];
2960 vm_size_t mapped, pgsz, base, mask;
2963 /* Round up to the next 1M */
2964 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1);
2969 pgsz = 64*1024*1024;
2970 while (mapped < size) {
2971 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) {
2972 while (pgsz > (size - mapped))
2978 /* We under-map. Correct for this. */
2979 if (mapped < size) {
2980 while (pgs[idx - 1] == pgsz) {
2984 /* XXX We may increase beyond out starting point. */
2993 /* Align address to the boundary */
2995 va = (va + mask) & ~mask;
2996 pa = (pa + mask) & ~mask;
2999 for (idx = 0; idx < nents; idx++) {
3001 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz);
3002 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM);
3007 mapped = (va - base);
3008 debugf("mapped size 0x%08x (wasted space 0x%08x)\n",
3009 mapped, mapped - size);
3014 * TLB1 initialization routine, to be called after the very first
3015 * assembler level setup done in locore.S.
3018 tlb1_init(vm_offset_t ccsrbar)
3020 uint32_t mas0, mas1, mas3;
3024 ccsrbar_pa = ccsrbar;
3026 if (bootinfo != NULL && bootinfo[0] != 1) {
3027 tlb1_idx = *((uint16_t *)(bootinfo + 8));
3031 /* The first entry/entries are used to map the kernel. */
3032 for (i = 0; i < tlb1_idx; i++) {
3033 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3034 mtspr(SPR_MAS0, mas0);
3035 __asm __volatile("isync; tlbre");
3037 mas1 = mfspr(SPR_MAS1);
3038 if ((mas1 & MAS1_VALID) == 0)
3041 mas3 = mfspr(SPR_MAS3);
3043 tlb1[i].mas1 = mas1;
3044 tlb1[i].mas2 = mfspr(SPR_MAS2);
3045 tlb1[i].mas3 = mas3;
3048 kernload = mas3 & MAS3_RPN;
3050 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3051 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
3054 /* Map in CCSRBAR. */
3055 tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO);
3058 bp_ntlb1s = tlb1_idx;
3061 /* Purge the remaining entries */
3062 for (i = tlb1_idx; i < TLB1_ENTRIES; i++)
3063 tlb1_write_entry(i);
3065 /* Setup TLB miss defaults */
3066 set_mas4_defaults();
3070 * Setup MAS4 defaults.
3071 * These values are loaded to MAS0-2 on a TLB miss.
3074 set_mas4_defaults(void)
3078 /* Defaults: TLB0, PID0, TSIZED=4K */
3079 mas4 = MAS4_TLBSELD0;
3080 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
3084 mtspr(SPR_MAS4, mas4);
3085 __asm __volatile("isync");
3089 * Print out contents of the MAS registers for each TLB1 entry
3092 tlb1_print_tlbentries(void)
3094 uint32_t mas0, mas1, mas2, mas3, mas7;
3097 debugf("TLB1 entries:\n");
3098 for (i = 0; i < TLB1_ENTRIES; i++) {
3100 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3101 mtspr(SPR_MAS0, mas0);
3103 __asm __volatile("isync; tlbre");
3105 mas1 = mfspr(SPR_MAS1);
3106 mas2 = mfspr(SPR_MAS2);
3107 mas3 = mfspr(SPR_MAS3);
3108 mas7 = mfspr(SPR_MAS7);
3110 tlb_print_entry(i, mas1, mas2, mas3, mas7);
3115 * Print out contents of the in-ram tlb1 table.
3118 tlb1_print_entries(void)
3122 debugf("tlb1[] table entries:\n");
3123 for (i = 0; i < TLB1_ENTRIES; i++)
3124 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0);
3128 * Return 0 if the physical IO range is encompassed by one of the
3129 * the TLB1 entries, otherwise return related error code.
3132 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
3135 vm_paddr_t pa_start;
3137 unsigned int entry_tsize;
3138 vm_size_t entry_size;
3140 *va = (vm_offset_t)NULL;
3142 /* Skip invalid entries */
3143 if (!(tlb1[i].mas1 & MAS1_VALID))
3147 * The entry must be cache-inhibited, guarded, and r/w
3148 * so it can function as an i/o page
3150 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G);
3151 if (prot != (MAS2_I | MAS2_G))
3154 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW);
3155 if (prot != (MAS3_SR | MAS3_SW))
3158 /* The address should be within the entry range. */
3159 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3160 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3162 entry_size = tsize2size(entry_tsize);
3163 pa_start = tlb1[i].mas3 & MAS3_RPN;
3164 pa_end = pa_start + entry_size - 1;
3166 if ((pa < pa_start) || ((pa + size) > pa_end))
3169 /* Return virtual address of this mapping. */
3170 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start);