2 * Copyright (C) 2002 Benno Rice.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/module.h>
34 #include <sys/kernel.h>
36 #include <dev/ofw/openfirm.h>
37 #include <dev/ofw/ofw_pci.h>
38 #include <dev/ofw/ofw_bus.h>
39 #include <dev/ofw/ofw_bus_subr.h>
41 #include <dev/pci/pcivar.h>
42 #include <dev/pci/pcireg.h>
44 #include <machine/bus.h>
45 #include <machine/intr_machdep.h>
46 #include <machine/md_var.h>
47 #include <machine/pio.h>
48 #include <machine/resource.h>
52 #include <powerpc/ofw/ofw_pci.h>
53 #include <powerpc/powermac/uninorthvar.h>
60 #define UNINORTH_DEBUG 0
65 static int uninorth_probe(device_t);
66 static int uninorth_attach(device_t);
71 static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int,
73 static void uninorth_write_config(device_t, u_int, u_int, u_int,
74 u_int, u_int32_t, int);
79 static int uninorth_enable_config(struct uninorth_softc *, u_int,
85 static device_method_t uninorth_methods[] = {
86 /* Device interface */
87 DEVMETHOD(device_probe, uninorth_probe),
88 DEVMETHOD(device_attach, uninorth_attach),
91 DEVMETHOD(pcib_read_config, uninorth_read_config),
92 DEVMETHOD(pcib_write_config, uninorth_write_config),
97 static devclass_t uninorth_devclass;
99 DEFINE_CLASS_1(pcib, uninorth_driver, uninorth_methods,
100 sizeof(struct uninorth_softc), ofw_pci_driver);
101 DRIVER_MODULE(uninorth, nexus, uninorth_driver, uninorth_devclass, 0, 0);
104 uninorth_probe(device_t dev)
106 const char *type, *compatible;
108 type = ofw_bus_get_type(dev);
109 compatible = ofw_bus_get_compat(dev);
111 if (type == NULL || compatible == NULL)
114 if (strcmp(type, "pci") != 0)
117 if (strcmp(compatible, "uni-north") == 0) {
118 device_set_desc(dev, "Apple UniNorth Host-PCI bridge");
120 } else if (strcmp(compatible, "u3-agp") == 0) {
121 device_set_desc(dev, "Apple U3 Host-AGP bridge");
123 } else if (strcmp(compatible, "u4-pcie") == 0) {
124 device_set_desc(dev, "IBM CPC945 PCI Express Root");
132 uninorth_attach(device_t dev)
134 struct uninorth_softc *sc;
135 const char *compatible;
139 node = ofw_bus_get_node(dev);
140 sc = device_get_softc(dev);
142 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
146 compatible = ofw_bus_get_compat(dev);
147 if (strcmp(compatible, "u3-agp") == 0)
149 if (strcmp(compatible, "u4-pcie") == 0)
152 if (sc->sc_ver >= 3) {
153 sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[1] + 0x800000, PAGE_SIZE);
154 sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1] + 0xc00000, PAGE_SIZE);
156 sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[0] + 0x800000, PAGE_SIZE);
157 sc->sc_data = (vm_offset_t)pmap_mapdev(reg[0] + 0xc00000, PAGE_SIZE);
160 return (ofw_pci_attach(dev));
164 uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
167 struct uninorth_softc *sc;
170 sc = device_get_softc(dev);
171 caoff = sc->sc_data + (reg & 0x07);
173 if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) {
176 return (in8rb(caoff));
179 return (in16rb(caoff));
182 return (in32rb(caoff));
191 uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func,
192 u_int reg, u_int32_t val, int width)
194 struct uninorth_softc *sc;
197 sc = device_get_softc(dev);
198 caoff = sc->sc_data + (reg & 0x07);
200 if (uninorth_enable_config(sc, bus, slot, func, reg)) {
216 uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot,
217 u_int func, u_int reg)
222 if (resource_int_value(device_get_name(sc->pci_sc.sc_dev),
223 device_get_unit(sc->pci_sc.sc_dev), "skipslot", &pass) == 0) {
229 * Issue type 0 configuration space accesses for the root bus.
231 * NOTE: On U4, issue only type 1 accesses. There is a secret
232 * PCI Express <-> PCI Express bridge not present in the device tree,
233 * and we need to route all of our configuration space through it.
235 if (sc->pci_sc.sc_bus == bus && sc->sc_ver < 4) {
237 * No slots less than 11 on the primary bus on U3 and lower
242 cfgval = (1 << slot) | (func << 8) | (reg & 0xfc);
244 cfgval = (bus << 16) | (slot << 11) | (func << 8) |
248 /* Set extended register bits on U4 */
250 cfgval |= (reg >> 8) << 28;
253 out32rb(sc->sc_addr, cfgval);
254 } while (in32rb(sc->sc_addr) != cfgval);