2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_auto_eoi.h"
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/interrupt.h>
44 #include <sys/kernel.h>
46 #include <sys/module.h>
48 #include <machine/cpufunc.h>
49 #include <machine/frame.h>
50 #include <machine/intr_machdep.h>
51 #include <machine/md_var.h>
52 #include <machine/resource.h>
53 #include <machine/segments.h>
55 #include <dev/ic/i8259.h>
56 #include <x86/isa/icu.h>
58 #include <pc98/cbus/cbus.h>
60 #include <x86/isa/isa.h>
62 #include <isa/isavar.h>
65 #define SDT_ATPIC SDT_SYSIGT
68 #define SDT_ATPIC SDT_SYS386IGT
69 #define GSEL_ATPIC GSEL(GCODE_SEL, SEL_KPL)
75 #define NUM_ISA_IRQS 16
77 static void atpic_init(void *dummy);
79 unsigned int imen; /* XXX */
82 IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
83 IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
84 IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
85 IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
86 IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
89 #define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
91 #define ATPIC(io, base, eoi, imenptr) \
92 { { atpic_enable_source, atpic_disable_source, (eoi), \
93 atpic_enable_intr, atpic_disable_intr, atpic_vector, \
94 atpic_source_pending, NULL, atpic_resume, atpic_config_intr,\
95 atpic_assign_cpu }, (io), (base), IDT_IO_INTS + (base), \
99 { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
110 struct atpic_intsrc {
111 struct intsrc at_intsrc;
113 int at_irq; /* Relative to PIC base. */
114 enum intr_trigger at_trigger;
116 u_long at_straycount;
119 static void atpic_enable_source(struct intsrc *isrc);
120 static void atpic_disable_source(struct intsrc *isrc, int eoi);
121 static void atpic_eoi_master(struct intsrc *isrc);
122 static void atpic_eoi_slave(struct intsrc *isrc);
123 static void atpic_enable_intr(struct intsrc *isrc);
124 static void atpic_disable_intr(struct intsrc *isrc);
125 static int atpic_vector(struct intsrc *isrc);
126 static void atpic_resume(struct pic *pic, bool suspend_cancelled);
127 static int atpic_source_pending(struct intsrc *isrc);
128 static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
129 enum intr_polarity pol);
130 static int atpic_assign_cpu(struct intsrc *isrc, u_int apic_id);
131 static void i8259_init(struct atpic *pic, int slave);
133 static struct atpic atpics[] = {
134 ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen),
135 ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1)
138 static struct atpic_intsrc atintrs[] = {
157 CTASSERT(sizeof(atintrs) / sizeof(atintrs[0]) == NUM_ISA_IRQS);
160 _atpic_eoi_master(struct intsrc *isrc)
163 KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
164 ("%s: mismatched pic", __func__));
166 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
171 * The data sheet says no auto-EOI on slave, but it sometimes works.
172 * So, if AUTO_EOI_2 is enabled, we use it.
175 _atpic_eoi_slave(struct intsrc *isrc)
178 KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
179 ("%s: mismatched pic", __func__));
181 outb(atpics[SLAVE].at_ioaddr, OCW2_EOI);
183 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
189 atpic_enable_source(struct intsrc *isrc)
191 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
192 struct atpic *ap = (struct atpic *)isrc->is_pic;
195 if (*ap->at_imen & IMEN_MASK(ai)) {
196 *ap->at_imen &= ~IMEN_MASK(ai);
197 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
203 atpic_disable_source(struct intsrc *isrc, int eoi)
205 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
206 struct atpic *ap = (struct atpic *)isrc->is_pic;
209 if (ai->at_trigger != INTR_TRIGGER_EDGE) {
210 *ap->at_imen |= IMEN_MASK(ai);
211 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
215 * Take care to call these functions directly instead of through
216 * a function pointer. All of the referenced variables should
217 * still be hot in the cache.
219 if (eoi == PIC_EOI) {
220 if (isrc->is_pic == &atpics[MASTER].at_pic)
221 _atpic_eoi_master(isrc);
223 _atpic_eoi_slave(isrc);
230 atpic_eoi_master(struct intsrc *isrc)
234 _atpic_eoi_master(isrc);
240 atpic_eoi_slave(struct intsrc *isrc)
244 _atpic_eoi_slave(isrc);
250 atpic_enable_intr(struct intsrc *isrc)
255 atpic_disable_intr(struct intsrc *isrc)
261 atpic_vector(struct intsrc *isrc)
263 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
264 struct atpic *ap = (struct atpic *)isrc->is_pic;
266 return (IRQ(ap, ai));
270 atpic_source_pending(struct intsrc *isrc)
272 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
273 struct atpic *ap = (struct atpic *)isrc->is_pic;
275 return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
279 atpic_resume(struct pic *pic, bool suspend_cancelled)
281 struct atpic *ap = (struct atpic *)pic;
283 i8259_init(ap, ap == &atpics[SLAVE]);
285 if (ap == &atpics[SLAVE] && elcr_found)
291 atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
292 enum intr_polarity pol)
294 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
297 /* Map conforming values to edge/hi and sanity check the values. */
298 if (trig == INTR_TRIGGER_CONFORM)
299 trig = INTR_TRIGGER_EDGE;
300 if (pol == INTR_POLARITY_CONFORM)
301 pol = INTR_POLARITY_HIGH;
302 vector = atpic_vector(isrc);
303 if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) ||
304 (trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) {
306 "atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n",
307 vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level",
308 pol == INTR_POLARITY_HIGH ? "high" : "low");
312 /* If there is no change, just return. */
313 if (ai->at_trigger == trig)
317 if ((vector == 0 || vector == 1 || vector == 7 || vector == 8) &&
318 trig == INTR_TRIGGER_LEVEL) {
321 "atpic: Ignoring invalid level/low configuration for IRQ%u\n",
328 * Certain IRQs can never be level/lo, so don't try to set them
329 * that way if asked. At least some ELCR registers ignore setting
330 * these bits as well.
332 if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) &&
333 trig == INTR_TRIGGER_LEVEL) {
336 "atpic: Ignoring invalid level/low configuration for IRQ%u\n",
342 printf("atpic: No ELCR to configure IRQ%u as %s\n",
343 vector, trig == INTR_TRIGGER_EDGE ? "edge/high" :
348 printf("atpic: Programming IRQ%u as %s\n", vector,
349 trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low");
351 elcr_write_trigger(atpic_vector(isrc), trig);
352 ai->at_trigger = trig;
359 atpic_assign_cpu(struct intsrc *isrc, u_int apic_id)
363 * 8259A's are only used in UP in which case all interrupts always
364 * go to the sole CPU and this function shouldn't even be called.
366 panic("%s: bad cookie", __func__);
370 i8259_init(struct atpic *pic, int slave)
374 /* Reset the PIC and program with next four bytes. */
377 /* MCA uses level triggered interrupts. */
379 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4 | ICW1_LTIM);
382 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4);
383 imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
386 outb(imr_addr, pic->at_intbase);
389 * Setup slave links. For the master pic, indicate what line
390 * the slave is configured on. For the slave indicate
391 * which line on the master we are connected to.
394 outb(imr_addr, ICU_SLAVEID);
396 outb(imr_addr, IRQ_MASK(ICU_SLAVEID));
400 outb(imr_addr, SLAVE_MODE);
402 outb(imr_addr, MASTER_MODE);
404 /* Set interrupt enable mask. */
405 outb(imr_addr, *pic->at_imen);
407 /* Reset is finished, default to IRR on read. */
408 outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR);
411 /* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */
413 outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1);
421 struct atpic_intsrc *ai;
424 /* Start off with all interrupts disabled. */
426 i8259_init(&atpics[MASTER], 0);
427 i8259_init(&atpics[SLAVE], 1);
428 atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
430 /* Install low-level interrupt handlers for all of our IRQs. */
431 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
432 if (i == ICU_SLAVEID)
434 ai->at_intsrc.is_count = &ai->at_count;
435 ai->at_intsrc.is_straycount = &ai->at_straycount;
436 setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
437 ai->at_irq, ai->at_intr, SDT_ATPIC, SEL_KPL, GSEL_ATPIC);
441 /* For MCA systems, all interrupts are level triggered. */
443 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
444 ai->at_trigger = INTR_TRIGGER_LEVEL;
449 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
455 ai->at_trigger = INTR_TRIGGER_EDGE;
458 ai->at_trigger = INTR_TRIGGER_LEVEL;
463 * Look for an ELCR. If we find one, update the trigger modes.
464 * If we don't find one, assume that IRQs 0, 1, 2, and 13 are
465 * edge triggered and that everything else is level triggered.
466 * We only use the trigger information to reprogram the ELCR if
467 * we have one and as an optimization to avoid masking edge
468 * triggered interrupts. For the case that we don't have an ELCR,
469 * it doesn't hurt to mask an edge triggered interrupt, so we
470 * assume level trigger for any interrupt that we aren't sure is
474 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
475 ai->at_trigger = elcr_read_trigger(i);
477 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
484 ai->at_trigger = INTR_TRIGGER_EDGE;
487 ai->at_trigger = INTR_TRIGGER_LEVEL;
495 atpic_init(void *dummy __unused)
497 struct atpic_intsrc *ai;
501 * Register our PICs, even if we aren't going to use any of their
502 * pins so that they are suspended and resumed.
504 if (intr_register_pic(&atpics[0].at_pic) != 0 ||
505 intr_register_pic(&atpics[1].at_pic) != 0)
506 panic("Unable to register ATPICs");
509 * If any of the ISA IRQs have an interrupt source already, then
510 * assume that the APICs are being used and don't register any
511 * of our interrupt sources. This makes sure we don't accidentally
512 * use mixed mode. The "accidental" use could otherwise occur on
513 * machines that route the ACPI SCI interrupt to a different ISA
514 * IRQ (at least one machines routes it to IRQ 13) thus disabling
515 * that APIC ISA routing and allowing the ATPIC source for that IRQ
516 * to leak through. We used to depend on this feature for routing
517 * IRQ0 via mixed mode, but now we don't use mixed mode at all.
519 for (i = 0; i < NUM_ISA_IRQS; i++)
520 if (intr_lookup_source(i) != NULL)
523 /* Loop through all interrupt sources and add them. */
524 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
525 if (i == ICU_SLAVEID)
527 intr_register_source(&ai->at_intsrc);
530 SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_SECOND + 1, atpic_init, NULL);
533 atpic_handle_intr(u_int vector, struct trapframe *frame)
537 KASSERT(vector < NUM_ISA_IRQS, ("unknown int %u\n", vector));
538 isrc = &atintrs[vector].at_intsrc;
541 * If we don't have an event, see if this is a spurious
544 if (isrc->is_event == NULL && (vector == 7 || vector == 15)) {
548 * Read the ISR register to see if IRQ 7/15 is really
549 * pending. Reset read register back to IRR when done.
551 port = ((struct atpic *)isrc->is_pic)->at_ioaddr;
553 outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS);
555 outb(port, OCW3_SEL | OCW3_RR);
557 if ((isr & IRQ_MASK(7)) == 0)
560 intr_execute_handlers(isrc, frame);
565 * Bus attachment for the ISA PIC.
567 static struct isa_pnp_id atpic_ids[] = {
568 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
573 atpic_probe(device_t dev)
577 result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
584 * We might be granted IRQ 2, as this is typically consumed by chaining
585 * between the two PIC components. If we're using the APIC, however,
586 * this may not be the case, and as such we should free the resource.
589 * The generic ISA attachment code will handle allocating any other resources
590 * that we don't explicitly claim here.
593 atpic_attach(device_t dev)
595 struct resource *res;
598 /* Try to allocate our IRQ and then free it. */
600 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
602 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
606 static device_method_t atpic_methods[] = {
607 /* Device interface */
608 DEVMETHOD(device_probe, atpic_probe),
609 DEVMETHOD(device_attach, atpic_attach),
610 DEVMETHOD(device_detach, bus_generic_detach),
611 DEVMETHOD(device_shutdown, bus_generic_shutdown),
612 DEVMETHOD(device_suspend, bus_generic_suspend),
613 DEVMETHOD(device_resume, bus_generic_resume),
617 static driver_t atpic_driver = {
623 static devclass_t atpic_devclass;
625 DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
627 DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
631 * Return a bitmap of the current interrupt requests. This is 8259-specific
632 * and is only suitable for use at probe time.
635 isa_irq_pending(void)
642 return ((irr2 << 8) | irr1);