2 * Structure definitions for HVM state that is held by Xen and must
3 * be saved along with the domain's memory and device-model state.
5 * Copyright (c) 2007 XenSource Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to
9 * deal in the Software without restriction, including without limitation the
10 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
11 * sell copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 #ifndef __XEN_PUBLIC_HVM_SAVE_X86_H__
27 #define __XEN_PUBLIC_HVM_SAVE_X86_H__
30 * Save/restore header: general info about the save file.
33 #define HVM_FILE_MAGIC 0x54381286
34 #define HVM_FILE_VERSION 0x00000001
36 struct hvm_save_header {
37 uint32_t magic; /* Must be HVM_FILE_MAGIC */
38 uint32_t version; /* File format version */
39 uint64_t changeset; /* Version of Xen that saved this file */
40 uint32_t cpuid; /* CPUID[0x01][%eax] on the saving machine */
41 uint32_t gtsc_khz; /* Guest's TSC frequency in kHz */
44 DECLARE_HVM_SAVE_TYPE(HEADER, 1, struct hvm_save_header);
50 * Compat: Pre-3.4 didn't have msr_tsc_aux
54 uint8_t fpu_regs[512];
126 uint32_t ldtr_arbytes;
128 uint64_t sysenter_cs;
129 uint64_t sysenter_esp;
130 uint64_t sysenter_eip;
135 /* msr content saved/restored. */
140 uint64_t msr_syscall_mask;
142 uint64_t msr_tsc_aux;
144 /* guest's idea of what rdtsc() would return */
147 /* pending event, if any */
149 uint32_t pending_event;
151 uint8_t pending_vector:8;
152 uint8_t pending_type:3;
153 uint8_t pending_error_valid:1;
154 uint32_t pending_reserved:19;
155 uint8_t pending_valid:1;
158 /* error code for pending event */
162 struct hvm_hw_cpu_compat {
163 uint8_t fpu_regs[512];
235 uint32_t ldtr_arbytes;
237 uint64_t sysenter_cs;
238 uint64_t sysenter_esp;
239 uint64_t sysenter_eip;
244 /* msr content saved/restored. */
249 uint64_t msr_syscall_mask;
251 /*uint64_t msr_tsc_aux; COMPAT */
253 /* guest's idea of what rdtsc() would return */
256 /* pending event, if any */
258 uint32_t pending_event;
260 uint8_t pending_vector:8;
261 uint8_t pending_type:3;
262 uint8_t pending_error_valid:1;
263 uint32_t pending_reserved:19;
264 uint8_t pending_valid:1;
267 /* error code for pending event */
271 static inline int _hvm_hw_fix_cpu(void *h) {
272 struct hvm_hw_cpu *new=h;
273 struct hvm_hw_cpu_compat *old=h;
275 /* If we copy from the end backwards, we should
276 * be able to do the modification in-place */
277 new->error_code=old->error_code;
278 new->pending_event=old->pending_event;
285 DECLARE_HVM_SAVE_TYPE_COMPAT(CPU, 2, struct hvm_hw_cpu, \
286 struct hvm_hw_cpu_compat, _hvm_hw_fix_cpu);
293 /* IR line bitmasks. */
298 /* Line IRx maps to IRQ irq_base+x */
302 * Where are we in ICW2-4 initialisation (0 means no init in progress)?
303 * Bits 0-1 (=x): Next write at A=1 sets ICW(x+1).
304 * Bit 2: ICW1.IC4 (1 == ICW4 included in init sequence)
305 * Bit 3: ICW1.SNGL (0 == ICW3 included in init sequence)
307 uint8_t init_state:4;
309 /* IR line with highest priority. */
310 uint8_t priority_add:4;
312 /* Reads from A=0 obtain ISR or IRR? */
313 uint8_t readsel_isr:1;
315 /* Reads perform a polling read? */
318 /* Automatically clear IRQs from the ISR during INTA? */
321 /* Automatically rotate IRQ priorities during AEOI? */
322 uint8_t rotate_on_auto_eoi:1;
324 /* Exclude slave inputs when considering in-service IRQs? */
325 uint8_t special_fully_nested_mode:1;
327 /* Special mask mode excludes masked IRs from AEOI and priority checks. */
328 uint8_t special_mask_mode:1;
330 /* Is this a master PIC or slave PIC? (NB. This is not programmable.) */
333 /* Edge/trigger selection. */
336 /* Virtual INT output. */
340 DECLARE_HVM_SAVE_TYPE(PIC, 3, struct hvm_hw_vpic);
347 #define VIOAPIC_NUM_PINS 48 /* 16 ISA IRQs, 32 non-legacy PCI IRQS. */
349 struct hvm_hw_vioapic {
350 uint64_t base_address;
353 union vioapic_redir_entry
358 uint8_t delivery_mode:3;
360 uint8_t delivery_status:1;
362 uint8_t remote_irr:1;
369 } redirtbl[VIOAPIC_NUM_PINS];
372 DECLARE_HVM_SAVE_TYPE(IOAPIC, 4, struct hvm_hw_vioapic);
379 struct hvm_hw_lapic {
380 uint64_t apic_base_msr;
381 uint32_t disabled; /* VLAPIC_xx_DISABLED */
382 uint32_t timer_divisor;
386 DECLARE_HVM_SAVE_TYPE(LAPIC, 5, struct hvm_hw_lapic);
388 struct hvm_hw_lapic_regs {
392 DECLARE_HVM_SAVE_TYPE(LAPIC_REGS, 6, struct hvm_hw_lapic_regs);
399 struct hvm_hw_pci_irqs {
401 * Virtual interrupt wires for a single PCI bus.
402 * Indexed by: device*4 + INTx#.
405 unsigned long i[16 / sizeof (unsigned long)]; /* DECLARE_BITMAP(i, 32*4); */
410 DECLARE_HVM_SAVE_TYPE(PCI_IRQ, 7, struct hvm_hw_pci_irqs);
412 struct hvm_hw_isa_irqs {
414 * Virtual interrupt wires for ISA devices.
415 * Indexed by ISA IRQ (assumes no ISA-device IRQ sharing).
418 unsigned long i[1]; /* DECLARE_BITMAP(i, 16); */
423 DECLARE_HVM_SAVE_TYPE(ISA_IRQ, 8, struct hvm_hw_isa_irqs);
425 struct hvm_hw_pci_link {
427 * PCI-ISA interrupt router.
428 * Each PCI <device:INTx#> is 'wire-ORed' into one of four links using
429 * the traditional 'barber's pole' mapping ((device + INTx#) & 3).
430 * The router provides a programmable mapping from each link to a GSI.
436 DECLARE_HVM_SAVE_TYPE(PCI_LINK, 9, struct hvm_hw_pci_link);
443 struct hvm_hw_pit_channel {
444 uint32_t count; /* can be 65536 */
445 uint16_t latched_count;
446 uint8_t count_latched;
447 uint8_t status_latched;
454 uint8_t bcd; /* not supported */
455 uint8_t gate; /* timer start */
456 } channels[3]; /* 3 x 16 bytes */
457 uint32_t speaker_data_on;
461 DECLARE_HVM_SAVE_TYPE(PIT, 10, struct hvm_hw_pit);
468 #define RTC_CMOS_SIZE 14
471 uint8_t cmos_data[RTC_CMOS_SIZE];
472 /* Index register for 2-part operations */
477 DECLARE_HVM_SAVE_TYPE(RTC, 11, struct hvm_hw_rtc);
484 #define HPET_TIMER_NUM 3 /* 3 timers supported now */
486 /* Memory-mapped, software visible registers */
487 uint64_t capability; /* capabilities */
488 uint64_t res0; /* reserved */
489 uint64_t config; /* configuration */
490 uint64_t res1; /* reserved */
491 uint64_t isr; /* interrupt status reg */
492 uint64_t res2[25]; /* reserved */
493 uint64_t mc64; /* main counter */
494 uint64_t res3; /* reserved */
495 struct { /* timers */
496 uint64_t config; /* configuration/cap */
497 uint64_t cmp; /* comparator */
498 uint64_t fsb; /* FSB route, not supported now */
499 uint64_t res4; /* reserved */
500 } timers[HPET_TIMER_NUM];
501 uint64_t res5[4*(24-HPET_TIMER_NUM)]; /* reserved, up to 0x3ff */
503 /* Hidden register state */
504 uint64_t period[HPET_TIMER_NUM]; /* Last value written to comparator */
507 DECLARE_HVM_SAVE_TYPE(HPET, 12, struct hvm_hw_hpet);
514 struct hvm_hw_pmtimer {
515 uint32_t tmr_val; /* PM_TMR_BLK.TMR_VAL: 32bit free-running counter */
516 uint16_t pm1a_sts; /* PM1a_EVT_BLK.PM1a_STS: status register */
517 uint16_t pm1a_en; /* PM1a_EVT_BLK.PM1a_EN: enable register */
520 DECLARE_HVM_SAVE_TYPE(PMTIMER, 13, struct hvm_hw_pmtimer);
528 #define NUM_FIXED_MSR 11
530 /* mtrr physbase & physmask msr pair*/
531 uint64_t msr_mtrr_var[MTRR_VCNT*2];
532 uint64_t msr_mtrr_fixed[NUM_FIXED_MSR];
533 uint64_t msr_mtrr_cap;
534 uint64_t msr_mtrr_def_type;
537 DECLARE_HVM_SAVE_TYPE(MTRR, 14, struct hvm_hw_mtrr);
540 * The save area of XSAVE/XRSTOR.
543 struct hvm_hw_cpu_xsave {
544 uint64_t xfeature_mask;
545 uint64_t xcr0; /* Updated by XSETBV */
546 uint64_t xcr0_accum; /* Updated by XSETBV */
548 struct { char x[512]; } fpu_sse;
551 uint64_t xstate_bv; /* Updated by XRSTOR */
552 uint64_t reserved[7];
553 } xsave_hdr; /* The 64-byte header */
555 struct { char x[0]; } ymm; /* YMM */
559 #define CPU_XSAVE_CODE 16
562 * Viridian hypervisor context.
565 struct hvm_viridian_domain_context {
566 uint64_t hypercall_gpa;
567 uint64_t guest_os_id;
570 DECLARE_HVM_SAVE_TYPE(VIRIDIAN_DOMAIN, 15, struct hvm_viridian_domain_context);
572 struct hvm_viridian_vcpu_context {
573 uint64_t apic_assist;
576 DECLARE_HVM_SAVE_TYPE(VIRIDIAN_VCPU, 17, struct hvm_viridian_vcpu_context);
578 struct hvm_vmce_vcpu {
582 DECLARE_HVM_SAVE_TYPE(VMCE_VCPU, 18, struct hvm_vmce_vcpu);
585 * Largest type-code in use
587 #define HVM_SAVE_CODE_MAX 18
589 #endif /* __XEN_PUBLIC_HVM_SAVE_X86_H__ */