tools/tools/ath/common/dumpregs_5211.c

   1 /*-
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  13  *    redistribution must be conditioned upon including a substantially
  14  *    similar Disclaimer requirement for further binary redistribution.
  15  *
  16  * NO WARRANTY
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  27  * THE POSSIBILITY OF SUCH DAMAGES.
  28  *
  29  * $FreeBSD$
  30  */
  31 #include "diag.h"
  32
  33 #include "ah.h"
  34 #include "ah_internal.h"
  35 #include "ar5211/ar5211reg.h"
  36 #include "ar5211/ar5211phy.h"
  37
  38 #include "dumpregs.h"
  39
  40 #define N(a)    (sizeof(a) / sizeof(a[0]))
  41
  42 static struct dumpreg ar5211regs[] = {
  43     DEFBASICfmt(AR_CR,          "CR",           AR_CR_BITS),
  44     DEFBASIC(AR_RXDP,           "RXDP"),
  45     DEFBASICfmt(AR_CFG,         "CFG",          AR_CFG_BITS),
  46     DEFBASICfmt(AR_IER,         "IER",          AR_IER_BITS),
  47     DEFBASIC(AR_RTSD0,          "RTSD0"),
  48     DEFBASIC(AR_RTSD1,          "RTSD1"),
  49     DEFBASICfmt(AR_TXCFG,       "TXCFG",        AR_TXCFG_BITS),
  50     DEFBASIC(AR_RXCFG,          "RXCFG"),
  51     DEFBASIC(AR5211_JUMBO_LAST, "JLAST"),
  52     DEFBASIC(AR_MIBC,           "MIBC"),
  53     DEFBASIC(AR_TOPS,           "TOPS"),
  54     DEFBASIC(AR_RXNPTO,         "RXNPTO"),
  55     DEFBASIC(AR_TXNPTO,         "TXNPTO"),
  56     DEFBASIC(AR_RFGTO,          "RFGTO"),
  57     DEFBASIC(AR_RFCNT,          "RFCNT"),
  58     DEFBASIC(AR_MACMISC,        "MISC"),
  59     DEFVOID(AR5311_QDCLKGATE,   "AR5311_QDCLKGATE"),
  60
  61     DEFINT(AR_ISR,              "ISR"),
  62     DEFINT(AR_ISR_S0,           "ISR_S0"),
  63     DEFINT(AR_ISR_S1,           "ISR_S1"),
  64     DEFINT(AR_ISR_S2,           "ISR_S2"),
  65     DEFINT(AR_ISR_S3,           "ISR_S3"),
  66     DEFINT(AR_ISR_S4,           "ISR_S4"),
  67     DEFINT(AR_IMR,              "IMR"),
  68     DEFINT(AR_IMR_S0,           "IMR_S0"),
  69     DEFINT(AR_IMR_S1,           "IMR_S1"),
  70     DEFINT(AR_IMR_S2,           "IMR_S2"),
  71     DEFINT(AR_IMR_S3,           "IMR_S3"),
  72     DEFINT(AR_IMR_S4,           "IMR_S4"),
  73     /* NB: don't read the RAC so we don't affect operation */
  74     DEFVOID(AR_ISR_RAC,         "ISR_RAC"),
  75     DEFINT(AR_ISR_S0_S,         "ISR_S0_S"),
  76     DEFINT(AR_ISR_S1_S,         "ISR_S1_S"),
  77     DEFINT(AR_ISR_S2_S,         "ISR_S2_S"),
  78     DEFINT(AR_ISR_S3_S,         "ISR_S3_S"),
  79     DEFINT(AR_ISR_S4_S,         "ISR_S4_S"),
  80
  81     DEFQCU(AR_Q0_TXDP,          "Q0_TXDP"),
  82     DEFQCU(AR_Q1_TXDP,          "Q1_TXDP"),
  83     DEFQCU(AR_Q2_TXDP,          "Q2_TXDP"),
  84     DEFQCU(AR_Q3_TXDP,          "Q3_TXDP"),
  85     DEFQCU(AR_Q4_TXDP,          "Q4_TXDP"),
  86     DEFQCU(AR_Q5_TXDP,          "Q5_TXDP"),
  87     DEFQCU(AR_Q6_TXDP,          "Q6_TXDP"),
  88     DEFQCU(AR_Q7_TXDP,          "Q7_TXDP"),
  89     DEFQCU(AR_Q8_TXDP,          "Q8_TXDP"),
  90     DEFQCU(AR_Q9_TXDP,          "Q9_TXDP"),
  91
  92     DEFQCU(AR_Q_TXE,            "Q_TXE"),
  93     DEFQCU(AR_Q_TXD,            "Q_TXD"),
  94
  95     DEFQCU(AR_Q0_CBRCFG,        "Q0_CBR"),
  96     DEFQCU(AR_Q1_CBRCFG,        "Q1_CBR"),
  97     DEFQCU(AR_Q2_CBRCFG,        "Q2_CBR"),
  98     DEFQCU(AR_Q3_CBRCFG,        "Q3_CBR"),
  99     DEFQCU(AR_Q4_CBRCFG,        "Q4_CBR"),
 100     DEFQCU(AR_Q5_CBRCFG,        "Q5_CBR"),
 101     DEFQCU(AR_Q6_CBRCFG,        "Q6_CBR"),
 102     DEFQCU(AR_Q7_CBRCFG,        "Q7_CBR"),
 103     DEFQCU(AR_Q8_CBRCFG,        "Q8_CBR"),
 104     DEFQCU(AR_Q9_CBRCFG,        "Q9_CBR"),
 105
 106     DEFQCU(AR_Q0_RDYTIMECFG,    "Q0_RDYT"),
 107     DEFQCU(AR_Q1_RDYTIMECFG,    "Q1_RDYT"),
 108     DEFQCU(AR_Q2_RDYTIMECFG,    "Q2_RDYT"),
 109     DEFQCU(AR_Q3_RDYTIMECFG,    "Q3_RDYT"),
 110     DEFQCU(AR_Q4_RDYTIMECFG,    "Q4_RDYT"),
 111     DEFQCU(AR_Q5_RDYTIMECFG,    "Q5_RDYT"),
 112     DEFQCU(AR_Q6_RDYTIMECFG,    "Q6_RDYT"),
 113     DEFQCU(AR_Q7_RDYTIMECFG,    "Q7_RDYT"),
 114     DEFQCU(AR_Q8_RDYTIMECFG,    "Q8_RDYT"),
 115     DEFQCU(AR_Q9_RDYTIMECFG,    "Q9_RDYT"),
 116
 117     DEFQCU(AR_Q_ONESHOTARM_SC,  "Q_ONESHOTARM_SC"),
 118     DEFQCU(AR_Q_ONESHOTARM_CC,  "Q_ONESHOTARM_CC"),
 119
 120     DEFQCU(AR_Q0_MISC,          "Q0_MISC"),
 121     DEFQCU(AR_Q1_MISC,          "Q1_MISC"),
 122     DEFQCU(AR_Q2_MISC,          "Q2_MISC"),
 123     DEFQCU(AR_Q3_MISC,          "Q3_MISC"),
 124     DEFQCU(AR_Q4_MISC,          "Q4_MISC"),
 125     DEFQCU(AR_Q5_MISC,          "Q5_MISC"),
 126     DEFQCU(AR_Q6_MISC,          "Q6_MISC"),
 127     DEFQCU(AR_Q7_MISC,          "Q7_MISC"),
 128     DEFQCU(AR_Q8_MISC,          "Q8_MISC"),
 129     DEFQCU(AR_Q9_MISC,          "Q9_MISC"),
 130
 131     DEFQCU(AR_Q0_STS,           "Q0_STS"),
 132     DEFQCU(AR_Q1_STS,           "Q1_STS"),
 133     DEFQCU(AR_Q2_STS,           "Q2_STS"),
 134     DEFQCU(AR_Q3_STS,           "Q3_STS"),
 135     DEFQCU(AR_Q4_STS,           "Q4_STS"),
 136     DEFQCU(AR_Q5_STS,           "Q5_STS"),
 137     DEFQCU(AR_Q6_STS,           "Q6_STS"),
 138     DEFQCU(AR_Q7_STS,           "Q7_STS"),
 139     DEFQCU(AR_Q8_STS,           "Q8_STS"),
 140     DEFQCU(AR_Q9_STS,           "Q9_STS"),
 141
 142     DEFQCU(AR_Q_RDYTIMESHDN,    "Q_RDYTIMSHD"),
 143
 144     DEFQCU(AR_D0_QCUMASK,       "D0_MASK"),
 145     DEFQCU(AR_D1_QCUMASK,       "D1_MASK"),
 146     DEFQCU(AR_D2_QCUMASK,       "D2_MASK"),
 147     DEFQCU(AR_D3_QCUMASK,       "D3_MASK"),
 148     DEFQCU(AR_D4_QCUMASK,       "D4_MASK"),
 149     DEFQCU(AR_D5_QCUMASK,       "D5_MASK"),
 150     DEFQCU(AR_D6_QCUMASK,       "D6_MASK"),
 151     DEFQCU(AR_D7_QCUMASK,       "D7_MASK"),
 152     DEFQCU(AR_D8_QCUMASK,       "D8_MASK"),
 153     DEFQCU(AR_D9_QCUMASK,       "D9_MASK"),
 154
 155     DEFDCU(AR_D0_LCL_IFS,       "D0_IFS"),
 156     DEFDCU(AR_D1_LCL_IFS,       "D1_IFS"),
 157     DEFDCU(AR_D2_LCL_IFS,       "D2_IFS"),
 158     DEFDCU(AR_D3_LCL_IFS,       "D3_IFS"),
 159     DEFDCU(AR_D4_LCL_IFS,       "D4_IFS"),
 160     DEFDCU(AR_D5_LCL_IFS,       "D5_IFS"),
 161     DEFDCU(AR_D6_LCL_IFS,       "D6_IFS"),
 162     DEFDCU(AR_D7_LCL_IFS,       "D7_IFS"),
 163     DEFDCU(AR_D8_LCL_IFS,       "D8_IFS"),
 164     DEFDCU(AR_D9_LCL_IFS,       "D9_IFS"),
 165
 166     DEFDCU(AR_D0_RETRY_LIMIT,   "D0_RTRY"),
 167     DEFDCU(AR_D1_RETRY_LIMIT,   "D1_RTRY"),
 168     DEFDCU(AR_D2_RETRY_LIMIT,   "D2_RTRY"),
 169     DEFDCU(AR_D3_RETRY_LIMIT,   "D3_RTRY"),
 170     DEFDCU(AR_D4_RETRY_LIMIT,   "D4_RTRY"),
 171     DEFDCU(AR_D5_RETRY_LIMIT,   "D5_RTRY"),
 172     DEFDCU(AR_D6_RETRY_LIMIT,   "D6_RTRY"),
 173     DEFDCU(AR_D7_RETRY_LIMIT,   "D7_RTRY"),
 174     DEFDCU(AR_D8_RETRY_LIMIT,   "D8_RTRY"),
 175     DEFDCU(AR_D9_RETRY_LIMIT,   "D9_RTRY"),
 176
 177     DEFDCU(AR_D0_CHNTIME,       "D0_CHNT"),
 178     DEFDCU(AR_D1_CHNTIME,       "D1_CHNT"),
 179     DEFDCU(AR_D2_CHNTIME,       "D2_CHNT"),
 180     DEFDCU(AR_D3_CHNTIME,       "D3_CHNT"),
 181     DEFDCU(AR_D4_CHNTIME,       "D4_CHNT"),
 182     DEFDCU(AR_D5_CHNTIME,       "D5_CHNT"),
 183     DEFDCU(AR_D6_CHNTIME,       "D6_CHNT"),
 184     DEFDCU(AR_D7_CHNTIME,       "D7_CHNT"),
 185     DEFDCU(AR_D8_CHNTIME,       "D8_CHNT"),
 186     DEFDCU(AR_D9_CHNTIME,       "D9_CHNT"),
 187
 188     DEFDCU(AR_D0_MISC,          "D0_MISC"),
 189     DEFDCU(AR_D1_MISC,          "D1_MISC"),
 190     DEFDCU(AR_D2_MISC,          "D2_MISC"),
 191     DEFDCU(AR_D3_MISC,          "D3_MISC"),
 192     DEFDCU(AR_D4_MISC,          "D4_MISC"),
 193     DEFDCU(AR_D5_MISC,          "D5_MISC"),
 194     DEFDCU(AR_D6_MISC,          "D6_MISC"),
 195     DEFDCU(AR_D7_MISC,          "D7_MISC"),
 196     DEFDCU(AR_D8_MISC,          "D8_MISC"),
 197     DEFDCU(AR_D9_MISC,          "D9_MISC"),
 198
 199     DEFDCU(AR_D0_SEQNUM,        "D0_SEQ"),
 200     DEFDCU(AR_D1_SEQNUM,        "D1_SEQ"),
 201     DEFDCU(AR_D2_SEQNUM,        "D2_SEQ"),
 202     DEFDCU(AR_D3_SEQNUM,        "D3_SEQ"),
 203     DEFDCU(AR_D4_SEQNUM,        "D4_SEQ"),
 204     DEFDCU(AR_D5_SEQNUM,        "D5_SEQ"),
 205     DEFDCU(AR_D6_SEQNUM,        "D6_SEQ"),
 206     DEFDCU(AR_D7_SEQNUM,        "D7_SEQ"),
 207     DEFDCU(AR_D8_SEQNUM,        "D8_SEQ"),
 208     DEFDCU(AR_D9_SEQNUM,        "D9_SEQ"),
 209
 210     DEFBASIC(AR_D_GBL_IFS_SIFS, "D_SIFS"),
 211     DEFBASIC(AR_D_GBL_IFS_SLOT, "D_SLOT"),
 212     DEFBASIC(AR_D_GBL_IFS_EIFS, "D_EIFS"),
 213     DEFBASIC(AR_D_GBL_IFS_MISC, "D_MISC"),
 214     DEFBASIC(AR_D_FPCTL,        "D_FPCTL"),
 215     DEFBASIC(AR_D_TXPSE,        "D_TXPSE"),
 216     DEFVOID(AR_D_TXBLK_CMD,     "D_CMD"),
 217 #if 0
 218     DEFVOID(AR_D_TXBLK_DATA,    "D_DATA"),
 219 #endif
 220     DEFVOID(AR_D_TXBLK_CLR,     "D_CLR"),
 221     DEFVOID(AR_D_TXBLK_SET,     "D_SET"),
 222     DEFBASICfmt(AR_RC,          "RC",           AR_RC_BITS),
 223     DEFBASICfmt(AR_SCR,         "SCR",          AR_SCR_BITS),
 224     DEFBASICfmt(AR_INTPEND,     "INTPEND",      AR_INTPEND_BITS),
 225     DEFBASIC(AR_SFR,            "SFR"),
 226     DEFBASICfmt(AR_PCICFG,      "PCICFG",       AR_PCICFG_BITS),
 227     DEFBASIC(AR_GPIOCR,         "GPIOCR"),
 228     DEFBASIC(AR_GPIODO,         "GPIODO"),
 229     DEFBASIC(AR_GPIODI,         "GPIODI"),
 230     DEFBASIC(AR_SREV,           "SREV"),
 231     DEFVOID(AR_EEPROM_ADDR,     "EEADDR"),
 232     DEFVOID(AR_EEPROM_DATA,     "EEDATA"),
 233     DEFVOID(AR_EEPROM_CMD,      "EECMD"),
 234     DEFVOID(AR_EEPROM_STS,      "EESTS"),
 235     DEFVOID(AR_EEPROM_CFG,      "EECFG"),
 236     DEFBASIC(AR_STA_ID0,        "STA_ID0"),
 237     DEFBASICfmt(AR_STA_ID1,     "STA_ID1",      AR_STA_ID1_BITS),
 238     DEFBASIC(AR_BSS_ID0,        "BSS_ID0"),
 239     DEFBASIC(AR_BSS_ID1,        "BSS_ID1"),
 240     DEFBASIC(AR_SLOT_TIME,      "SLOTTIME"),
 241     DEFBASIC(AR_TIME_OUT,       "TIME_OUT"),
 242     DEFBASIC(AR_RSSI_THR,       "RSSI_THR"),
 243     DEFBASIC(AR_USEC,           "USEC"),
 244     DEFBASICfmt(AR_BEACON,      "BEACON",       AR_BEACON_BITS),
 245     DEFBASIC(AR_CFP_PERIOD,     "CFP_PER"),
 246     DEFBASIC(AR_TIMER0,         "TIMER0"),
 247     DEFBASIC(AR_TIMER1,         "TIMER1"),
 248     DEFBASIC(AR_TIMER2,         "TIMER2"),
 249     DEFBASIC(AR_TIMER3,         "TIMER3"),
 250     DEFBASIC(AR_CFP_DUR,        "CFP_DUR"),
 251     DEFBASICfmt(AR_RX_FILTER,   "RXFILTER",     AR_RX_FILTER_BITS),
 252     DEFBASIC(AR_MCAST_FIL0,     "MCAST_0"),
 253     DEFBASIC(AR_MCAST_FIL1,     "MCAST_1"),
 254     DEFBASICfmt(AR_DIAG_SW,     "DIAG_SW",      AR_DIAG_SW_BITS),
 255     DEFBASIC(AR_TSF_L32,        "TSF_L32"),
 256     DEFBASIC(AR_TSF_U32,        "TSF_U32"),
 257     DEFBASIC(AR_TST_ADDAC,      "TST_ADAC"),
 258     DEFBASIC(AR_DEF_ANTENNA,    "DEF_ANT"),
 259
 260     DEFBASIC(AR_LAST_TSTP,      "LAST_TST"),
 261     DEFBASIC(AR_NAV,            "NAV"),
 262     DEFBASIC(AR_RTS_OK,         "RTS_OK"),
 263     DEFBASIC(AR_RTS_FAIL,       "RTS_FAIL"),
 264     DEFBASIC(AR_ACK_FAIL,       "ACK_FAIL"),
 265     DEFBASIC(AR_FCS_FAIL,       "FCS_FAIL"),
 266     DEFBASIC(AR_BEACON_CNT,     "BEAC_CNT"),
 267
 268     DEFVOID(AR_PHY_TURBO,       "PHY_TURBO"),
 269     DEFVOID(AR_PHY_CHIP_ID,     "PHY_CHIP_ID"),
 270     DEFVOID(AR_PHY_ACTIVE,      "PHY_ACTIVE"),
 271     DEFVOID(AR_PHY_AGC_CONTROL, "PHY_AGC_CONTROL"),
 272     DEFVOID(AR_PHY_PLL_CTL,     "PHY_PLL_CTL"),
 273     DEFVOID(AR_PHY_RX_DELAY,    "PHY_RX_DELAY"),
 274     DEFVOID(AR_PHY_TIMING_CTRL4,"PHY_TIMING_CTRL4"),
 275     DEFVOID(AR_PHY_RADAR_0,     "PHY_RADAR_0"),
 276     DEFVOID(AR_PHY_IQCAL_RES_PWR_MEAS_I,"PHY_IQCAL_RES_PWR_MEAS_I"),
 277     DEFVOID(AR_PHY_IQCAL_RES_PWR_MEAS_Q,"PHY_IQCAL_RES_PWR_MEAS_Q"),
 278     DEFVOID(AR_PHY_IQCAL_RES_IQ_CORR_MEAS,"PHY_IQCAL_RES_IQ_CORR_MEAS"),
 279     DEFVOID(AR_PHY_CURRENT_RSSI,"PHY_CURRENT_RSSI"),
 280     DEFVOID(AR5211_PHY_MODE,    "PHY_MODE"),
 281 };
 282
 283 static __constructor void
 284 ar5211_ctor(void)
 285 {
 286 #define MAC5211 SREV(2,0), SREV(4,5)
 287         register_regs(ar5211regs, N(ar5211regs), MAC5211, PHYANY);
 288         register_keycache(128, MAC5211, PHYANY);
 289
 290         register_range(0x9800, 0x987c, DUMP_BASEBAND, MAC5211, PHYANY);
 291         register_range(0x9900, 0x995c, DUMP_BASEBAND, MAC5211, PHYANY);
 292         register_range(0x9c00, 0x9c1c, DUMP_BASEBAND, MAC5211, PHYANY);
 293 }