tools/tools/ath/common/dumpregs_5416.c

   1 /*-
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  13  *    redistribution must be conditioned upon including a substantially
  14  *    similar Disclaimer requirement for further binary redistribution.
  15  *
  16  * NO WARRANTY
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  27  * THE POSSIBILITY OF SUCH DAMAGES.
  28  *
  29  * $FreeBSD$
  30  */
  31 #include "diag.h"
  32
  33 #include "ah.h"
  34 #include "ah_internal.h"
  35 #include "ar5416/ar5416reg.h"
  36 #include "ar5416/ar5416phy.h"
  37
  38 #include "dumpregs.h"
  39
  40 #define N(a)    (sizeof(a) / sizeof(a[0]))
  41
  42 #define MAC5416 SREV(13,8), SREV(0xffff,0xffff) /* XXX */
  43
  44 static struct dumpreg ar5416regs[] = {
  45     DEFBASIC(AR_CR,             "CR"),
  46     DEFBASIC(AR_RXDP,           "RXDP"),
  47     DEFBASIC(AR_CFG,            "CFG"),
  48     DEFBASIC(AR_MIRT,           "MIRT"),
  49     DEFBASIC(AR_TIMT,           "TIMT"),
  50     DEFBASIC(AR_CST,            "CST"),
  51     DEFBASIC(AR_IER,            "IER"),
  52     DEFBASIC(AR_TXCFG,          "TXCFG"),
  53     DEFBASICfmt(AR_RXCFG,       "RXCFG",
  54         "\20\6JUMBO_ENA\7JUMBO_WRAP\10SLEEP_DEBUG"),
  55     DEFBASIC(AR_MIBC,           "MIBC"),
  56     DEFBASIC(AR_TOPS,           "TOPS"),
  57     DEFBASIC(AR_RXNPTO,         "RXNPTO"),
  58     DEFBASIC(AR_TXNPTO,         "TXNPTO"),
  59     DEFBASIC(AR_RPGTO,          "RPGTO"),
  60     DEFBASIC(AR_RPCNT,          "RPCNT"),
  61     DEFBASIC(AR_MACMISC,        "MACMISC"),
  62     DEFBASIC(AR_SPC_0,          "SPC_0"),
  63     DEFBASIC(AR_SPC_1,          "SPC_1"),
  64     DEFBASIC(AR_GTXTO,          "GTXTO"),
  65     DEFBASIC(AR_GTTM,           "GTTM"),
  66
  67     DEFINTfmt(AR_ISR,           "ISR",
  68           "\20\1RXOK\2RXDESC\3RXERR\4RXNOPKT\5RXEOL\6RXORN\7TXOK\10TXDESC"
  69           "\11TXERR\12TXNOPKT\13TXEOL\14TXURN\15MIB\16SWI\17RXPHY\20RXKCM"
  70           "\21SWBA\22BRSSI\23BMISS\24HIUERR\25BNR\26RXCHIRP\27RXDOPPL\30BCNMISS"
  71           "\31TIM\32GPIO\33QCBROVF\34QCBRURN\35QTRIG"),
  72     DEFINT(AR_ISR_S0,           "ISR_S0"),
  73     DEFINT(AR_ISR_S1,           "ISR_S1"),
  74     DEFINTfmt(AR_ISR_S2,        "ISR_S2",
  75           "\20\21MCABT\22SSERR\23DPERR\24TIM\25CABEND\26DTIMSYNC\27BCNTO"
  76           "\30CABTO\31DTIM"),
  77     DEFINT(AR_ISR_S3,           "ISR_S3"),
  78     DEFINT(AR_ISR_S4,           "ISR_S4"),
  79     DEFINT(AR_ISR_S5,           "ISR_S5"),
  80     DEFINTfmt(AR_IMR,           "IMR",
  81           "\20\1RXOK\2RXDESC\3RXERR\4RXNOPKT\5RXEOL\6RXORN\7TXOK\10TXDESC"
  82           "\11TXERR\12TXNOPKT\13TXEOL\14TXURN\15MIB\16SWI\17RXPHY\20RXKCM"
  83           "\21SWBA\22BRSSI\23BMISS\24HIUERR\25BNR\26RXCHIRP\27RXDOPPL\30BCNMISS"
  84           "\31TIM\32GPIO\33QCBROVF\34QCBRURN\35QTRIG"),
  85     DEFINT(AR_IMR_S0,           "IMR_S0"),
  86     DEFINT(AR_IMR_S1,           "IMR_S1"),
  87     DEFINTfmt(AR_IMR_S2,        "IMR_S2",
  88           "\20\21MCABT\22SSERR\23DPERR\24TIM\25CABEND\26DTIMSYNC\27BCNTO"
  89           "\30CABTO\31DTIM"),
  90     DEFINT(AR_IMR_S3,           "IMR_S3"),
  91     DEFINT(AR_IMR_S4,           "IMR_S4"),
  92     /* NB: don't read the RAC so we don't affect operation */
  93     DEFVOID(AR_ISR_RAC,         "ISR_RAC"),
  94     DEFINT(AR_ISR_S0_S,         "ISR_S0_S"),
  95     DEFINT(AR_ISR_S1_S,         "ISR_S1_S"),
  96     DEFINT(AR_ISR_S2_S,         "ISR_S2_S"),
  97     DEFINT(AR_ISR_S3_S,         "ISR_S3_S"),
  98     DEFINT(AR_ISR_S4_S,         "ISR_S4_S"),
  99     DEFINT(AR_ISR_S5_S,         "ISR_S5_S"),
 100
 101     DEFBASIC(AR_DMADBG_0,       "DMADBG0"),
 102     DEFBASIC(AR_DMADBG_1,       "DMADBG1"),
 103     DEFBASIC(AR_DMADBG_2,       "DMADBG2"),
 104     DEFBASIC(AR_DMADBG_3,       "DMADBG3"),
 105     DEFBASIC(AR_DMADBG_4,       "DMADBG4"),
 106     DEFBASIC(AR_DMADBG_5,       "DMADBG5"),
 107     DEFBASIC(AR_DMADBG_6,       "DMADBG6"),
 108     DEFBASIC(AR_DMADBG_7,       "DMADBG7"),
 109
 110     DEFBASIC(AR_DCM_A,          "DCM_A"),
 111     DEFBASIC(AR_DCM_D,          "DCM_D"),
 112     DEFBASIC(AR_DCCFG,          "DCCFG"),
 113     DEFBASIC(AR_CCFG,           "CCFG"),
 114     DEFBASIC(AR_CCUCFG,         "CCUCFG"),
 115     DEFBASIC(AR_CPC_0,          "CPC0"),
 116     DEFBASIC(AR_CPC_1,          "CPC1"),
 117     DEFBASIC(AR_CPC_2,          "CPC2"),
 118     DEFBASIC(AR_CPC_3,          "CPC3"),
 119     DEFBASIC(AR_CPCOVF,         "CPCOVF"),
 120
 121     DEFQCU(AR_Q0_TXDP,          "Q0_TXDP"),
 122     DEFQCU(AR_Q1_TXDP,          "Q1_TXDP"),
 123     DEFQCU(AR_Q2_TXDP,          "Q2_TXDP"),
 124     DEFQCU(AR_Q3_TXDP,          "Q3_TXDP"),
 125     DEFQCU(AR_Q4_TXDP,          "Q4_TXDP"),
 126     DEFQCU(AR_Q5_TXDP,          "Q5_TXDP"),
 127     DEFQCU(AR_Q6_TXDP,          "Q6_TXDP"),
 128     DEFQCU(AR_Q7_TXDP,          "Q7_TXDP"),
 129     DEFQCU(AR_Q8_TXDP,          "Q8_TXDP"),
 130     DEFQCU(AR_Q9_TXDP,          "Q9_TXDP"),
 131
 132     DEFQCU(AR_Q_TXE,            "Q_TXE"),
 133     DEFQCU(AR_Q_TXD,            "Q_TXD"),
 134
 135     DEFQCU(AR_Q0_CBRCFG,        "Q0_CBR"),
 136     DEFQCU(AR_Q1_CBRCFG,        "Q1_CBR"),
 137     DEFQCU(AR_Q2_CBRCFG,        "Q2_CBR"),
 138     DEFQCU(AR_Q3_CBRCFG,        "Q3_CBR"),
 139     DEFQCU(AR_Q4_CBRCFG,        "Q4_CBR"),
 140     DEFQCU(AR_Q5_CBRCFG,        "Q5_CBR"),
 141     DEFQCU(AR_Q6_CBRCFG,        "Q6_CBR"),
 142     DEFQCU(AR_Q7_CBRCFG,        "Q7_CBR"),
 143     DEFQCU(AR_Q8_CBRCFG,        "Q8_CBR"),
 144     DEFQCU(AR_Q9_CBRCFG,        "Q9_CBR"),
 145
 146     DEFQCU(AR_Q0_RDYTIMECFG,    "Q0_RDYT"),
 147     DEFQCU(AR_Q1_RDYTIMECFG,    "Q1_RDYT"),
 148     DEFQCU(AR_Q2_RDYTIMECFG,    "Q2_RDYT"),
 149     DEFQCU(AR_Q3_RDYTIMECFG,    "Q3_RDYT"),
 150     DEFQCU(AR_Q4_RDYTIMECFG,    "Q4_RDYT"),
 151     DEFQCU(AR_Q5_RDYTIMECFG,    "Q5_RDYT"),
 152     DEFQCU(AR_Q6_RDYTIMECFG,    "Q6_RDYT"),
 153     DEFQCU(AR_Q7_RDYTIMECFG,    "Q7_RDYT"),
 154     DEFQCU(AR_Q8_RDYTIMECFG,    "Q8_RDYT"),
 155     DEFQCU(AR_Q9_RDYTIMECFG,    "Q9_RDYT"),
 156
 157     DEFQCU(AR_Q_ONESHOTARM_SC,  "Q_ONESHOTARM_SC"),
 158     DEFQCU(AR_Q_ONESHOTARM_CC,  "Q_ONESHOTARM_CC"),
 159
 160     DEFQCU(AR_Q0_MISC,          "Q0_MISC"),
 161     DEFQCU(AR_Q1_MISC,          "Q1_MISC"),
 162     DEFQCU(AR_Q2_MISC,          "Q2_MISC"),
 163     DEFQCU(AR_Q3_MISC,          "Q3_MISC"),
 164     DEFQCU(AR_Q4_MISC,          "Q4_MISC"),
 165     DEFQCU(AR_Q5_MISC,          "Q5_MISC"),
 166     DEFQCU(AR_Q6_MISC,          "Q6_MISC"),
 167     DEFQCU(AR_Q7_MISC,          "Q7_MISC"),
 168     DEFQCU(AR_Q8_MISC,          "Q8_MISC"),
 169     DEFQCU(AR_Q9_MISC,          "Q9_MISC"),
 170
 171     DEFQCU(AR_Q0_STS,           "Q0_STS"),
 172     DEFQCU(AR_Q1_STS,           "Q1_STS"),
 173     DEFQCU(AR_Q2_STS,           "Q2_STS"),
 174     DEFQCU(AR_Q3_STS,           "Q3_STS"),
 175     DEFQCU(AR_Q4_STS,           "Q4_STS"),
 176     DEFQCU(AR_Q5_STS,           "Q5_STS"),
 177     DEFQCU(AR_Q6_STS,           "Q6_STS"),
 178     DEFQCU(AR_Q7_STS,           "Q7_STS"),
 179     DEFQCU(AR_Q8_STS,           "Q8_STS"),
 180     DEFQCU(AR_Q9_STS,           "Q9_STS"),
 181
 182     DEFQCU(AR_Q_RDYTIMESHDN,    "Q_RDYTIMSHD"),
 183
 184     DEFQCU(AR_Q_CBBS,           "Q_CBBS"),
 185     DEFQCU(AR_Q_CBBA,           "Q_CBBA"),
 186     DEFQCU(AR_Q_CBC,            "Q_CBC"),
 187
 188     DEFDCU(AR_D0_QCUMASK,       "D0_MASK"),
 189     DEFDCU(AR_D1_QCUMASK,       "D1_MASK"),
 190     DEFDCU(AR_D2_QCUMASK,       "D2_MASK"),
 191     DEFDCU(AR_D3_QCUMASK,       "D3_MASK"),
 192     DEFDCU(AR_D4_QCUMASK,       "D4_MASK"),
 193     DEFDCU(AR_D5_QCUMASK,       "D5_MASK"),
 194     DEFDCU(AR_D6_QCUMASK,       "D6_MASK"),
 195     DEFDCU(AR_D7_QCUMASK,       "D7_MASK"),
 196     DEFDCU(AR_D8_QCUMASK,       "D8_MASK"),
 197     DEFDCU(AR_D9_QCUMASK,       "D9_MASK"),
 198
 199     DEFDCU(AR_D0_LCL_IFS,       "D0_IFS"),
 200     DEFDCU(AR_D1_LCL_IFS,       "D1_IFS"),
 201     DEFDCU(AR_D2_LCL_IFS,       "D2_IFS"),
 202     DEFDCU(AR_D3_LCL_IFS,       "D3_IFS"),
 203     DEFDCU(AR_D4_LCL_IFS,       "D4_IFS"),
 204     DEFDCU(AR_D5_LCL_IFS,       "D5_IFS"),
 205     DEFDCU(AR_D6_LCL_IFS,       "D6_IFS"),
 206     DEFDCU(AR_D7_LCL_IFS,       "D7_IFS"),
 207     DEFDCU(AR_D8_LCL_IFS,       "D8_IFS"),
 208     DEFDCU(AR_D9_LCL_IFS,       "D9_IFS"),
 209
 210     DEFDCU(AR_D0_RETRY_LIMIT,   "D0_RTRY"),
 211     DEFDCU(AR_D1_RETRY_LIMIT,   "D1_RTRY"),
 212     DEFDCU(AR_D2_RETRY_LIMIT,   "D2_RTRY"),
 213     DEFDCU(AR_D3_RETRY_LIMIT,   "D3_RTRY"),
 214     DEFDCU(AR_D4_RETRY_LIMIT,   "D4_RTRY"),
 215     DEFDCU(AR_D5_RETRY_LIMIT,   "D5_RTRY"),
 216     DEFDCU(AR_D6_RETRY_LIMIT,   "D6_RTRY"),
 217     DEFDCU(AR_D7_RETRY_LIMIT,   "D7_RTRY"),
 218     DEFDCU(AR_D8_RETRY_LIMIT,   "D8_RTRY"),
 219     DEFDCU(AR_D9_RETRY_LIMIT,   "D9_RTRY"),
 220
 221     DEFDCU(AR_D0_CHNTIME,       "D0_CHNT"),
 222     DEFDCU(AR_D1_CHNTIME,       "D1_CHNT"),
 223     DEFDCU(AR_D2_CHNTIME,       "D2_CHNT"),
 224     DEFDCU(AR_D3_CHNTIME,       "D3_CHNT"),
 225     DEFDCU(AR_D4_CHNTIME,       "D4_CHNT"),
 226     DEFDCU(AR_D5_CHNTIME,       "D5_CHNT"),
 227     DEFDCU(AR_D6_CHNTIME,       "D6_CHNT"),
 228     DEFDCU(AR_D7_CHNTIME,       "D7_CHNT"),
 229     DEFDCU(AR_D8_CHNTIME,       "D8_CHNT"),
 230     DEFDCU(AR_D9_CHNTIME,       "D9_CHNT"),
 231
 232     DEFDCU(AR_D0_MISC,          "D0_MISC"),
 233     DEFDCU(AR_D1_MISC,          "D1_MISC"),
 234     DEFDCU(AR_D2_MISC,          "D2_MISC"),
 235     DEFDCU(AR_D3_MISC,          "D3_MISC"),
 236     DEFDCU(AR_D4_MISC,          "D4_MISC"),
 237     DEFDCU(AR_D5_MISC,          "D5_MISC"),
 238     DEFDCU(AR_D6_MISC,          "D6_MISC"),
 239     DEFDCU(AR_D7_MISC,          "D7_MISC"),
 240     DEFDCU(AR_D8_MISC,          "D8_MISC"),
 241     DEFDCU(AR_D9_MISC,          "D9_MISC"),
 242
 243     _DEFREG(AR_D_SEQNUM,        "D_SEQ",        DUMP_BASIC | DUMP_DCU),
 244     DEFBASIC(AR_D_GBL_IFS_SIFS, "D_SIFS"),
 245     DEFBASIC(AR_D_GBL_IFS_SLOT, "D_SLOT"),
 246     DEFBASIC(AR_D_GBL_IFS_EIFS, "D_EIFS"),
 247     DEFBASIC(AR_D_GBL_IFS_MISC, "D_MISC"),
 248     DEFBASIC(AR_D_FPCTL,        "D_FPCTL"),
 249     DEFBASIC(AR_D_TXPSE,        "D_TXPSE"),
 250     DEFVOID(AR_D_TXBLK_CMD,     "D_CMD"),
 251 #if 0
 252     DEFVOID(AR_D_TXBLK_DATA,    "D_DATA"),
 253 #endif
 254     DEFVOID(AR_D_TXBLK_CLR,     "D_CLR"),
 255     DEFVOID(AR_D_TXBLK_SET,     "D_SET"),
 256
 257     DEFBASIC(AR_MAC_LED,        "MAC_LED"),
 258     DEFBASICfmt(AR_RC,          "RC",
 259         "\20\1AHB\2APB\11HOSTIF"),
 260     DEFBASIC(AR_SCR,            "SCR"),
 261     DEFBASIC(AR_INTPEND,        "INTPEND"),
 262     DEFBASIC(AR_SFR,            "SFR"),
 263     DEFBASIC(AR_PCICFG,         "PCICFG"),
 264     DEFBASIC(AR_SREV,           "SREV"),
 265
 266     DEFBASIC(AR_AHB_MODE,       "AHBMODE"),
 267     DEFBASIC(AR_PCIE_PM_CTRL,   "PCIEPMC"),
 268     DEFBASIC(AR5416_PCIE_SERDES,"SERDES"),
 269     DEFBASIC(AR5416_PCIE_SERDES2, "SERDES2"),
 270
 271     DEFVOID(AR_INTR_SYNC_CAUSE_CLR,     "INTR_SYNC_CAUSE_CLR"),
 272     DEFVOID(AR_INTR_SYNC_CAUSE, "INTR_SYNC_CAUSE"),
 273     DEFVOID(AR_INTR_SYNC_ENABLE,"INTR_SYNC_ENABLE"),
 274     DEFBASIC(AR_INTR_ASYNC_MASK,"IASYNCM"),
 275     DEFBASIC(AR_INTR_SYNC_MASK, "ISYNCM"),
 276     DEFVOID(AR_INTR_ASYNC_CAUSE,"INTR_ASYNC_CAUSE"),
 277     DEFVOID(AR_INTR_ASYNC_ENABLE,"INTR_ASYNC_ENABLE"),
 278
 279     DEFBASICfmt(AR_RTC_RC,      "RTC_RC",
 280         "\20\1MAC_WARM\2MAC_COLD"),
 281     DEFBASIC(AR_RTC_PLL_CONTROL,"RTC_PLL"),
 282     DEFVOID(AR_RTC_RESET,       "RTC_RESET"),
 283     DEFVOIDfmt(AR_RTC_STATUS,   "RTC_STATUS",
 284         "\20\1SHUTDOWN\2ON\3SLEEP\4WAKEUP\5COLDRESET\6PLLCHANGE"),
 285     DEFVOID(AR_RTC_SLEEP_CLK,   "RTC_SLEEP_CLK"),
 286     DEFVOIDfmt(AR_RTC_FORCE_WAKE,"RTC_FORCE_WAKE",
 287         "\20\1EN\2WAKE_ON_INT"),
 288     DEFVOID(AR_RTC_INTR_CAUSE,  "RTC_INTR_CAUSE"),
 289     DEFVOID(AR_RTC_INTR_MASK,   "RTC_INTR_MASK"),
 290
 291     DEFBASIC(AR_GPIO_IN_OUT,    "GPIOIO"),
 292     DEFBASIC(AR_GPIO_OE_OUT,    "GPIOOE"),
 293     DEFBASIC(AR_GPIO_INTR_POL,  "GPIOPOL"),
 294     DEFBASIC(AR_GPIO_INPUT_EN_VAL,      "GPIOIEV"),
 295     DEFBASIC(AR_GPIO_INPUT_MUX1,        "GPIMUX1"),
 296     DEFBASIC(AR_GPIO_INPUT_MUX2,        "GPIMUX2"),
 297     DEFBASIC(AR_GPIO_OUTPUT_MUX1,       "GPOMUX1"),
 298     DEFBASIC(AR_GPIO_OUTPUT_MUX2,       "GPOMUX2"),
 299     DEFBASIC(AR_GPIO_OUTPUT_MUX3,       "GPOMUX3"),
 300     DEFBASIC(AR_OBS,            "OBS"),
 301     DEFVOID(AR_EEPROM_ADDR,     "EEADDR"),
 302     DEFVOID(AR_EEPROM_DATA,     "EEDATA"),
 303     DEFVOID(AR_EEPROM_CMD,      "EECMD"),
 304     DEFVOID(AR_EEPROM_STS,      "EESTS"),
 305     DEFVOID(AR_EEPROM_CFG,      "EECFG"),
 306     DEFBASIC(AR_STA_ID0,        "STA_ID0"),
 307     DEFBASICfmt(AR_STA_ID1,     "STA_ID1",
 308         "\20\21AP\22ADHOC\23PWR_SAV\24KSRCHDIS\25PCF\26USE_DEFANT"
 309         "\27UPD_DEFANT\30RTS_USE_DEF\31ACKCTS_6MB\32BASE_RATE_11B"
 310         "\33USE_DA_SG\34CRPT_MIC_ENABLE\35KSRCH_MODE\36PRE_SEQNUM"
 311         "\37CBCIV_ENDIAN\40MCAST_KSRC"),
 312     DEFBASIC(AR_BSS_ID0,        "BSS_ID0"),
 313     DEFBASIC(AR_BSS_ID1,        "BSS_ID1"),
 314     DEFBASIC(AR_SLOT_TIME,      "SLOTTIME"),
 315     DEFBASIC(AR_TIME_OUT,       "TIME_OUT"),
 316     DEFBASIC(AR_RSSI_THR,       "RSSI_THR"),
 317     DEFBASIC(AR_USEC,           "USEC"),
 318     DEFBASIC(AR_BEACON,         "BEACON"),
 319     DEFBASIC(AR_CFP_PERIOD,     "CFP_PER"),
 320     DEFBASIC(AR_TIMER0,         "TIMER0"),
 321     DEFBASIC(AR_TIMER1,         "TIMER1"),
 322     DEFBASIC(AR_TIMER2,         "TIMER2"),
 323     DEFBASIC(AR_TIMER3,         "TIMER3"),
 324     DEFBASIC(AR_CFP_DUR,        "CFP_DUR"),
 325     DEFBASIC(AR_RX_FILTER,      "RXFILTER"),
 326     DEFBASIC(AR_MCAST_FIL0,     "MCAST_0"),
 327     DEFBASIC(AR_MCAST_FIL1,     "MCAST_1"),
 328     DEFBASICfmt(AR_DIAG_SW,     "DIAG_SW",
 329           "\20\1CACHE_ACK\2ACK_DIS\3CTS_DIS\4ENCRYPT_DIS\5DECRYPT_DIS\6RX_DIS"
 330           "\7CORR_FCS\10CHAN_INFO\11EN_SCRAMSD\22FRAME_NV0\25RX_CLR_HI"
 331           "\26IGNORE_CS\27CHAN_IDLE\30PHEAR_ME"),
 332     DEFBASIC(AR_TSF_L32,        "TSF_L32"),
 333     DEFBASIC(AR_TSF_U32,        "TSF_U32"),
 334     DEFBASIC(AR_TST_ADDAC,      "TST_ADAC"),
 335     DEFBASIC(AR_DEF_ANTENNA,    "DEF_ANT"),
 336     DEFBASIC(AR_QOS_MASK,       "QOS_MASK"),
 337     DEFBASIC(AR_SEQ_MASK,       "SEQ_MASK"),
 338     DEFBASIC(AR_OBSERV_2,       "OBSERV2"),
 339     DEFBASIC(AR_OBSERV_1,       "OBSERV1"),
 340
 341     DEFBASIC(AR_LAST_TSTP,      "LAST_TST"),
 342     DEFBASIC(AR_NAV,            "NAV"),
 343     DEFBASIC(AR_RTS_OK,         "RTS_OK"),
 344     DEFBASIC(AR_RTS_FAIL,       "RTS_FAIL"),
 345     DEFBASIC(AR_ACK_FAIL,       "ACK_FAIL"),
 346     DEFBASIC(AR_FCS_FAIL,       "FCS_FAIL"),
 347     DEFBASIC(AR_BEACON_CNT,     "BEAC_CNT"),
 348
 349     DEFBASIC(AR_SLEEP1,         "SLEEP1"),
 350     DEFBASIC(AR_SLEEP2,         "SLEEP2"),
 351     DEFBASIC(AR_SLEEP3,         "SLEEP3"),
 352     DEFBASIC(AR_BSSMSKL,        "BSSMSKL"),
 353     DEFBASIC(AR_BSSMSKU,        "BSSMSKU"),
 354     DEFBASIC(AR_TPC,            "TPC"),
 355     DEFBASIC(AR_TFCNT,          "TFCNT"),
 356     DEFBASIC(AR_RFCNT,          "RFCNT"),
 357     DEFBASIC(AR_RCCNT,          "RCCNT"),
 358     DEFBASIC(AR_CCCNT,          "CCCNT"),
 359     DEFBASIC(AR_QUIET1,         "QUIET1"),
 360     DEFBASIC(AR_QUIET2,         "QUIET2"),
 361     DEFBASIC(AR_TSF_PARM,       "TSF_PARM"),
 362     DEFBASIC(AR_NOACK,          "NOACK"),
 363     DEFBASIC(AR_PHY_ERR,        "PHY_ERR"),
 364     DEFBASIC(AR_QOS_CONTROL,    "QOS_CTRL"),
 365     DEFBASIC(AR_QOS_SELECT,     "QOS_SEL"),
 366     DEFBASIC(AR_MISC_MODE,      "MISCMODE"),
 367     DEFBASIC(AR_FILTOFDM,       "FILTOFDM"),
 368     DEFBASIC(AR_FILTCCK,        "FILTCCK"),
 369     DEFBASIC(AR_PHYCNT1,        "PHYCNT1"),
 370     DEFBASIC(AR_PHYCNTMASK1,    "PHYCMSK1"),
 371     DEFBASIC(AR_PHYCNT2,        "PHYCNT2"),
 372     DEFBASIC(AR_PHYCNTMASK2,    "PHYCMSK2"),
 373
 374     DEFBASIC(AR_TXOP_X,         "TXOPX"),
 375     DEFBASIC(AR_NEXT_TBTT,      "NXTTBTT"),
 376     DEFBASIC(AR_NEXT_DBA,       "NXTDBA"),
 377     DEFBASIC(AR_NEXT_SWBA,      "NXTSWBA"),
 378     DEFBASIC(AR_NEXT_CFP,       "NXTCFP"),
 379     DEFBASIC(AR_NEXT_HCF,       "NXTHCF"),
 380     DEFBASIC(AR_NEXT_DTIM,      "NXTDTIM"),
 381     DEFBASIC(AR_NEXT_QUIET,     "NXTQUIET"),
 382     DEFBASIC(AR_NEXT_NDP,       "NXTNDP"),
 383     DEFBASIC(AR5416_BEACON_PERIOD, "BCNPER"),
 384     DEFBASIC(AR_DBA_PERIOD,     "DBAPER"),
 385     DEFBASIC(AR_SWBA_PERIOD,    "SWBAPER"),
 386     DEFBASIC(AR_TIM_PERIOD,     "TIMPER"),
 387     DEFBASIC(AR_DTIM_PERIOD,    "DTIMPER"),
 388     DEFBASIC(AR_QUIET_PERIOD,   "QUIETPER"),
 389     DEFBASIC(AR_NDP_PERIOD,     "NDPPER"),
 390     DEFBASIC(AR_TIMER_MODE,     "TIMERMOD"),
 391     DEFBASIC(AR_2040_MODE,      "2040MODE"),
 392     DEFBASIC(AR_PCU_TXBUF_CTRL, "PCUTXBUF"),
 393     DEFBASIC(AR_SLP32_MODE,     "SLP32MOD"),
 394     DEFBASIC(AR_SLP32_WAKE,     "SLP32WAK"),
 395     DEFBASIC(AR_SLP32_INC,      "SLP32INC"),
 396     DEFBASIC(AR_SLP_CNT,        "SLPCNT"),
 397     DEFBASIC(AR_SLP_MIB_CTRL,   "SLPMIB"),
 398     DEFBASIC(AR_EXTRCCNT,       "EXTRCCNT"),
 399     DEFBASIC(AR_PHY_TURBO,      "PHYTURBO"),
 400
 401     DEFVOID(AR_PHY_ADC_SERIAL_CTL,      "PHY_ADC_SERIAL_CTL"),
 402
 403     /* XXX { AR_RATE_DURATION(0), AR_RATE_DURATION(0x20) }, */
 404 };
 405
 406 static __constructor void
 407 ar5416_ctor(void)
 408 {
 409         register_regs(ar5416regs, N(ar5416regs), MAC5416, PHYANY);
 410         register_keycache(128, MAC5416, PHYANY);
 411
 412         register_range(0x9800, 0x987c, DUMP_BASEBAND, MAC5416, PHYANY);
 413         register_range(0x9900, 0x997c, DUMP_BASEBAND, MAC5416, PHYANY);
 414         register_range(0x99a4, 0x99a4, DUMP_BASEBAND, MAC5416, PHYANY);
 415         register_range(0x9c00, 0x9c1c, DUMP_BASEBAND, MAC5416, PHYANY);
 416         register_range(0xa180, 0xa238, DUMP_BASEBAND, MAC5416, PHYANY);
 417         register_range(0xa258, 0xa26c, DUMP_BASEBAND, MAC5416, PHYANY);
 418         register_range(0xa3c8, 0xa3d4, DUMP_BASEBAND, MAC5416, PHYANY);
 419         register_range(0xa864, 0xa864, DUMP_BASEBAND, MAC5416, PHYANY);
 420         register_range(0xa9bc, 0xa9bc, DUMP_BASEBAND, MAC5416, PHYANY);
 421         register_range(0xb864, 0xb864, DUMP_BASEBAND, MAC5416, PHYANY);
 422         register_range(0xb9bc, 0xb9bc, DUMP_BASEBAND, MAC5416, PHYANY);
 423 }