2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
36 #include <sys/ioctl.h>
39 #include <sys/endian.h>
58 #define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
60 #define PxSIG_ATA 0x00000101 /* ATA drive */
61 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
64 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
65 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
66 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
67 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
68 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
69 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
70 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
71 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
77 #define TEST_UNIT_READY 0x00
78 #define REQUEST_SENSE 0x03
80 #define START_STOP_UNIT 0x1B
81 #define PREVENT_ALLOW 0x1E
82 #define READ_CAPACITY 0x25
84 #define POSITION_TO_ELEMENT 0x2B
86 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
87 #define MODE_SENSE_10 0x5A
92 * SCSI mode page codes
94 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
95 #define MODEPAGE_CD_CAPABILITIES 0x2A
102 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
104 #define DPRINTF(format, arg...)
106 #define WPRINTF(format, arg...) printf(format, ##arg)
109 struct blockif_req io_req;
110 struct ahci_port *io_pr;
111 STAILQ_ENTRY(ahci_ioreq) io_list;
120 struct blockif_ctxt *bctx;
121 struct pci_ahci_softc *pr_sc;
152 struct ahci_ioreq *ioreq;
154 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
157 struct ahci_cmd_hdr {
162 uint32_t reserved[4];
165 struct ahci_prdt_entry {
171 struct pci_ahci_softc {
172 struct pci_devinst *asc_pi;
186 struct ahci_port port[MAX_PORTS];
188 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
190 static inline void lba_to_msf(uint8_t *buf, int lba)
193 buf[0] = (lba / 75) / 60;
194 buf[1] = (lba / 75) % 60;
199 * generate HBA intr depending on whether or not ports within
200 * the controller have an interrupt pending.
203 ahci_generate_intr(struct pci_ahci_softc *sc)
207 for (i = 0; i < sc->ports; i++) {
208 struct ahci_port *pr;
214 DPRINTF("%s %x\n", __func__, sc->is);
216 if (sc->is && (sc->ghc & AHCI_GHC_IE))
217 pci_generate_msi(sc->asc_pi, 0);
221 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
223 int offset, len, irq;
225 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
229 case FIS_TYPE_REGD2H:
234 case FIS_TYPE_SETDEVBITS:
239 case FIS_TYPE_PIOSETUP:
245 WPRINTF("unsupported fis type %d\n", ft);
248 memcpy(p->rfis + offset, fis, len);
251 ahci_generate_intr(p->pr_sc);
256 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd)
261 error = (tfd >> 8) & 0xff;
262 memset(fis, 0, sizeof(fis));
265 *(uint32_t *)(fis + 4) = (1 << slot);
266 if (fis[2] & ATA_S_ERROR)
267 p->is |= AHCI_P_IX_TFE;
269 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
273 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
278 error = (tfd >> 8) & 0xff;
279 memset(fis, 0, sizeof(fis));
280 fis[0] = FIS_TYPE_REGD2H;
294 if (fis[2] & ATA_S_ERROR)
295 p->is |= AHCI_P_IX_TFE;
297 p->ci &= ~(1 << slot);
298 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
302 ahci_write_reset_fis_d2h(struct ahci_port *p)
306 memset(fis, 0, sizeof(fis));
307 fis[0] = FIS_TYPE_REGD2H;
315 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
319 ahci_port_reset(struct ahci_port *pr)
324 pr->xfermode = ATA_UDMA6;
325 pr->mult_sectors = 128;
328 pr->ssts = ATA_SS_DET_NO_DEVICE;
329 pr->sig = 0xFFFFFFFF;
333 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_SPD_GEN2 |
335 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
338 pr->tfd |= ATA_S_READY;
340 pr->sig = PxSIG_ATAPI;
341 ahci_write_reset_fis_d2h(pr);
345 ahci_reset(struct pci_ahci_softc *sc)
349 sc->ghc = AHCI_GHC_AE;
351 for (i = 0; i < sc->ports; i++) {
354 ahci_port_reset(&sc->port[i]);
359 ata_string(uint8_t *dest, const char *src, int len)
363 for (i = 0; i < len; i++) {
365 dest[i ^ 1] = *src++;
372 atapi_string(uint8_t *dest, const char *src, int len)
376 for (i = 0; i < len; i++) {
385 ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
388 struct ahci_ioreq *aior;
389 struct blockif_req *breq;
390 struct pci_ahci_softc *sc;
391 struct ahci_prdt_entry *prdt;
392 struct ahci_cmd_hdr *hdr;
395 int i, err, iovcnt, ncq, readop;
398 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
399 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
404 if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
405 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
408 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
409 cfis[2] == ATA_READ_FPDMA_QUEUED) {
410 lba = ((uint64_t)cfis[10] << 40) |
411 ((uint64_t)cfis[9] << 32) |
412 ((uint64_t)cfis[8] << 24) |
413 ((uint64_t)cfis[6] << 16) |
414 ((uint64_t)cfis[5] << 8) |
416 len = cfis[11] << 8 | cfis[3];
420 } else if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
421 lba = ((uint64_t)cfis[10] << 40) |
422 ((uint64_t)cfis[9] << 32) |
423 ((uint64_t)cfis[8] << 24) |
424 ((uint64_t)cfis[6] << 16) |
425 ((uint64_t)cfis[5] << 8) |
427 len = cfis[13] << 8 | cfis[12];
431 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
432 (cfis[5] << 8) | cfis[4];
437 lba *= blockif_sectsz(p->bctx);
438 len *= blockif_sectsz(p->bctx);
441 * Pull request off free list
443 aior = STAILQ_FIRST(&p->iofhd);
444 assert(aior != NULL);
445 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
450 breq = &aior->io_req;
451 breq->br_offset = lba + done;
452 iovcnt = hdr->prdtl - seek;
453 if (iovcnt > BLOCKIF_IOV_MAX) {
454 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
455 iovcnt = BLOCKIF_IOV_MAX;
458 breq->br_iovcnt = iovcnt;
461 * Build up the iovec based on the prdt
463 for (i = 0; i < iovcnt; i++) {
464 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
465 prdt->dba, prdt->dbc + 1);
466 breq->br_iov[i].iov_len = prdt->dbc + 1;
467 aior->done += (prdt->dbc + 1);
471 err = blockif_read(p->bctx, breq);
473 err = blockif_write(p->bctx, breq);
476 if (!aior->prdtl && ncq)
477 p->ci &= ~(1 << slot);
481 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
483 struct ahci_ioreq *aior;
484 struct blockif_req *breq;
488 * Pull request off free list
490 aior = STAILQ_FIRST(&p->iofhd);
491 assert(aior != NULL);
492 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
496 breq = &aior->io_req;
498 err = blockif_flush(p->bctx, breq);
503 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
506 struct ahci_cmd_hdr *hdr;
507 struct ahci_prdt_entry *prdt;
511 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
514 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
515 for (i = 0; i < hdr->prdtl && len; i++) {
516 uint8_t *ptr = paddr_guest2host(ahci_ctx(p->pr_sc),
517 prdt->dba, prdt->dbc + 1);
518 memcpy(ptr, from, prdt->dbc + 1);
519 len -= (prdt->dbc + 1);
520 from += (prdt->dbc + 1);
523 hdr->prdbc = size - len;
527 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
529 struct ahci_cmd_hdr *hdr;
531 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
532 if (p->atapi || hdr->prdtl == 0) {
533 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
534 p->is |= AHCI_P_IX_TFE;
539 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
540 memset(buf, 0, sizeof(buf));
542 /* TODO emulate different serial? */
543 ata_string((uint8_t *)(buf+10), "123456", 20);
544 ata_string((uint8_t *)(buf+23), "001", 8);
545 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
546 buf[47] = (0x8000 | 128);
548 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
550 buf[53] = (1 << 1 | 1 << 2);
552 buf[59] = (0x100 | p->mult_sectors);
554 buf[61] = (sectors >> 16);
556 if (p->xfermode & ATA_WDMA0)
557 buf[63] |= (1 << ((p->xfermode & 7) + 8));
564 buf[76] = (1 << 8 | 1 << 2);
567 buf[82] = (1 << 5 | 1 << 14);
568 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14);
570 buf[85] = (1 << 5 | 1 << 14);
571 buf[86] = (1 << 10 | 1 << 12 | 1 << 13);
574 if (p->xfermode & ATA_UDMA0)
575 buf[88] |= (1 << ((p->xfermode & 7) + 8));
576 buf[93] = (1 | 1 <<14);
578 buf[101] = (sectors >> 16);
579 buf[102] = (sectors >> 32);
580 buf[103] = (sectors >> 48);
581 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
582 p->tfd = ATA_S_DSC | ATA_S_READY;
583 p->is |= AHCI_P_IX_DP;
585 p->ci &= ~(1 << slot);
586 ahci_generate_intr(p->pr_sc);
590 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
593 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
594 p->is |= AHCI_P_IX_TFE;
598 memset(buf, 0, sizeof(buf));
599 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
600 /* TODO emulate different serial? */
601 ata_string((uint8_t *)(buf+10), "123456", 20);
602 ata_string((uint8_t *)(buf+23), "001", 8);
603 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
604 buf[49] = (1 << 9 | 1 << 8);
605 buf[50] = (1 << 14 | 1);
606 buf[53] = (1 << 2 | 1 << 1);
614 buf[76] = (1 << 2 | 1 << 1);
616 buf[80] = (0x1f << 4);
622 buf[88] = (1 << 14 | 0x7f);
623 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
624 p->tfd = ATA_S_DSC | ATA_S_READY;
625 p->is |= AHCI_P_IX_DHR;
627 p->ci &= ~(1 << slot);
628 ahci_generate_intr(p->pr_sc);
632 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
648 atapi_string(buf + 8, "BHYVE", 8);
649 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
650 atapi_string(buf + 32, "001", 4);
655 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
656 write_prdt(p, slot, cfis, buf, len);
657 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
661 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
666 sectors = blockif_size(p->bctx) / 2048;
667 be32enc(buf, sectors - 1);
668 be32enc(buf + 4, 2048);
669 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
670 write_prdt(p, slot, cfis, buf, sizeof(buf));
671 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
675 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
683 len = be16dec(acmd + 7);
684 format = acmd[9] >> 6;
690 uint8_t start_track, buf[20], *bp;
692 msf = (acmd[1] >> 1) & 1;
693 start_track = acmd[6];
694 if (start_track > 1 && start_track != 0xaa) {
696 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
698 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
699 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
700 ahci_write_fis_d2h(p, slot, cfis, tfd);
706 if (start_track <= 1) {
726 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
730 lba_to_msf(bp, sectors);
733 be32enc(bp, sectors);
737 be16enc(buf, size - 2);
740 write_prdt(p, slot, cfis, buf, len);
741 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
742 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
749 memset(buf, 0, sizeof(buf));
753 if (len > sizeof(buf))
755 write_prdt(p, slot, cfis, buf, len);
756 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
757 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
764 uint8_t start_track, *bp, buf[50];
766 msf = (acmd[1] >> 1) & 1;
767 start_track = acmd[6];
803 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
807 lba_to_msf(bp, sectors);
810 be32enc(bp, sectors);
833 be16enc(buf, size - 2);
836 write_prdt(p, slot, cfis, buf, len);
837 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
838 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
845 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
847 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
848 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
849 ahci_write_fis_d2h(p, slot, cfis, tfd);
856 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
857 uint32_t done, int seek)
859 struct ahci_ioreq *aior;
860 struct ahci_cmd_hdr *hdr;
861 struct ahci_prdt_entry *prdt;
862 struct blockif_req *breq;
863 struct pci_ahci_softc *sc;
871 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
872 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
875 lba = be32dec(acmd + 2);
876 if (acmd[0] == READ_10)
877 len = be16dec(acmd + 7);
879 len = be32dec(acmd + 6);
881 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
882 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
888 * Pull request off free list
890 aior = STAILQ_FIRST(&p->iofhd);
891 assert(aior != NULL);
892 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
897 breq = &aior->io_req;
898 breq->br_offset = lba + done;
899 iovcnt = hdr->prdtl - seek;
900 if (iovcnt > BLOCKIF_IOV_MAX) {
901 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
902 iovcnt = BLOCKIF_IOV_MAX;
905 breq->br_iovcnt = iovcnt;
908 * Build up the iovec based on the prdt
910 for (i = 0; i < iovcnt; i++) {
911 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
912 prdt->dba, prdt->dbc + 1);
913 breq->br_iov[i].iov_len = prdt->dbc + 1;
914 aior->done += (prdt->dbc + 1);
917 err = blockif_read(p->bctx, breq);
922 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
930 if (len > sizeof(buf))
933 buf[0] = 0x70 | (1 << 7);
934 buf[2] = p->sense_key;
937 write_prdt(p, slot, cfis, buf, len);
938 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
939 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
943 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
945 uint8_t *acmd = cfis + 0x40;
948 switch (acmd[4] & 3) {
952 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
953 tfd = ATA_S_READY | ATA_S_DSC;
956 /* TODO eject media */
957 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
958 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
960 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
963 ahci_write_fis_d2h(p, slot, cfis, tfd);
967 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
975 len = be16dec(acmd + 7);
977 code = acmd[2] & 0x3f;
982 case MODEPAGE_RW_ERROR_RECOVERY:
986 if (len > sizeof(buf))
989 memset(buf, 0, sizeof(buf));
990 be16enc(buf, 16 - 2);
995 write_prdt(p, slot, cfis, buf, len);
996 tfd = ATA_S_READY | ATA_S_DSC;
999 case MODEPAGE_CD_CAPABILITIES:
1003 if (len > sizeof(buf))
1006 memset(buf, 0, sizeof(buf));
1007 be16enc(buf, 30 - 2);
1013 be16enc(&buf[18], 2);
1014 be16enc(&buf[20], 512);
1015 write_prdt(p, slot, cfis, buf, len);
1016 tfd = ATA_S_READY | ATA_S_DSC;
1025 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1027 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1032 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1034 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1037 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1038 ahci_write_fis_d2h(p, slot, cfis, tfd);
1042 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1050 /* we don't support asynchronous operation */
1051 if (!(acmd[1] & 1)) {
1052 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1054 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1059 len = be16dec(acmd + 7);
1060 if (len > sizeof(buf))
1063 memset(buf, 0, sizeof(buf));
1064 be16enc(buf, 8 - 2);
1068 write_prdt(p, slot, cfis, buf, len);
1069 tfd = ATA_S_READY | ATA_S_DSC;
1071 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1072 ahci_write_fis_d2h(p, slot, cfis, tfd);
1076 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1086 for (i = 0; i < 16; i++)
1087 DPRINTF("%02x ", acmd[i]);
1093 case TEST_UNIT_READY:
1094 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1095 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1098 atapi_inquiry(p, slot, cfis);
1101 atapi_read_capacity(p, slot, cfis);
1105 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1106 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1109 atapi_read_toc(p, slot, cfis);
1113 atapi_read(p, slot, cfis, 0, 0);
1116 atapi_request_sense(p, slot, cfis);
1118 case START_STOP_UNIT:
1119 atapi_start_stop_unit(p, slot, cfis);
1122 atapi_mode_sense(p, slot, cfis);
1124 case GET_EVENT_STATUS_NOTIFICATION:
1125 atapi_get_event_status_notification(p, slot, cfis);
1128 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1129 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1131 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1132 ATA_S_READY | ATA_S_ERROR);
1138 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1142 case ATA_ATA_IDENTIFY:
1143 handle_identify(p, slot, cfis);
1145 case ATA_SETFEATURES:
1148 case ATA_SF_ENAB_WCACHE:
1149 case ATA_SF_DIS_WCACHE:
1150 case ATA_SF_ENAB_RCACHE:
1151 case ATA_SF_DIS_RCACHE:
1152 p->tfd = ATA_S_DSC | ATA_S_READY;
1154 case ATA_SF_SETXFER:
1156 switch (cfis[12] & 0xf8) {
1162 p->xfermode = (cfis[12] & 0x7);
1165 p->tfd = ATA_S_DSC | ATA_S_READY;
1169 p->tfd = ATA_S_ERROR | ATA_S_READY;
1170 p->tfd |= (ATA_ERROR_ABORT << 8);
1173 p->is |= AHCI_P_IX_DP;
1174 p->ci &= ~(1 << slot);
1175 ahci_generate_intr(p->pr_sc);
1179 if (cfis[12] != 0 &&
1180 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1181 p->tfd = ATA_S_ERROR | ATA_S_READY;
1182 p->tfd |= (ATA_ERROR_ABORT << 8);
1184 p->mult_sectors = cfis[12];
1185 p->tfd = ATA_S_DSC | ATA_S_READY;
1187 p->is |= AHCI_P_IX_DP;
1188 p->ci &= ~(1 << slot);
1189 ahci_generate_intr(p->pr_sc);
1193 case ATA_READ_DMA48:
1194 case ATA_WRITE_DMA48:
1195 case ATA_READ_FPDMA_QUEUED:
1196 case ATA_WRITE_FPDMA_QUEUED:
1197 ahci_handle_dma(p, slot, cfis, 0, 0);
1199 case ATA_FLUSHCACHE:
1200 case ATA_FLUSHCACHE48:
1201 ahci_handle_flush(p, slot, cfis);
1203 case ATA_STANDBY_CMD:
1206 case ATA_STANDBY_IMMEDIATE:
1207 case ATA_IDLE_IMMEDIATE:
1209 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1211 case ATA_ATAPI_IDENTIFY:
1212 handle_atapi_identify(p, slot, cfis);
1214 case ATA_PACKET_CMD:
1216 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1217 p->is |= AHCI_P_IX_TFE;
1218 p->ci &= ~(1 << slot);
1219 ahci_generate_intr(p->pr_sc);
1221 handle_packet_cmd(p, slot, cfis);
1224 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1225 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1226 p->is |= AHCI_P_IX_TFE;
1227 p->ci &= ~(1 << slot);
1228 ahci_generate_intr(p->pr_sc);
1234 ahci_handle_slot(struct ahci_port *p, int slot)
1236 struct ahci_cmd_hdr *hdr;
1237 struct ahci_prdt_entry *prdt;
1238 struct pci_ahci_softc *sc;
1243 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1244 cfl = (hdr->flags & 0x1f) * 4;
1245 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1246 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1247 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1251 for (i = 0; i < cfl; i++) {
1254 DPRINTF("%02x ", cfis[i]);
1258 for (i = 0; i < hdr->prdtl; i++) {
1259 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1264 if (cfis[0] != FIS_TYPE_REGH2D) {
1265 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1269 if (cfis[1] & 0x80) {
1270 ahci_handle_cmd(p, slot, cfis);
1272 if (cfis[15] & (1 << 2))
1274 else if (p->reset) {
1278 p->ci &= ~(1 << slot);
1283 ahci_handle_port(struct ahci_port *p)
1287 if (!(p->cmd & AHCI_P_CMD_ST))
1290 for (i = 0; (i < 32) && p->ci; i++) {
1291 if (p->ci & (1 << i))
1292 ahci_handle_slot(p, i);
1297 * blockif callback routine - this runs in the context of the blockif
1298 * i/o thread, so the mutex needs to be acquired.
1301 ata_ioreq_cb(struct blockif_req *br, int err)
1303 struct ahci_cmd_hdr *hdr;
1304 struct ahci_ioreq *aior;
1305 struct ahci_port *p;
1306 struct pci_ahci_softc *sc;
1309 int pending, slot, ncq;
1311 DPRINTF("%s %d\n", __func__, err);
1314 aior = br->br_param;
1318 pending = aior->prdtl;
1320 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1322 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1323 cfis[2] == ATA_READ_FPDMA_QUEUED)
1326 pthread_mutex_lock(&sc->mtx);
1329 * Move the blockif request back to the free list
1331 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1333 if (pending && !err) {
1334 ahci_handle_dma(p, slot, cfis, aior->done,
1335 hdr->prdtl - pending);
1339 if (!err && aior->done == aior->len) {
1340 tfd = ATA_S_READY | ATA_S_DSC;
1344 hdr->prdbc = aior->len;
1346 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1349 p->serr |= (1 << slot);
1353 p->sact &= ~(1 << slot);
1354 ahci_write_fis_sdb(p, slot, tfd);
1356 ahci_write_fis_d2h(p, slot, cfis, tfd);
1359 pthread_mutex_unlock(&sc->mtx);
1360 DPRINTF("%s exit\n", __func__);
1364 atapi_ioreq_cb(struct blockif_req *br, int err)
1366 struct ahci_cmd_hdr *hdr;
1367 struct ahci_ioreq *aior;
1368 struct ahci_port *p;
1369 struct pci_ahci_softc *sc;
1374 DPRINTF("%s %d\n", __func__, err);
1376 aior = br->br_param;
1380 pending = aior->prdtl;
1382 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1384 pthread_mutex_lock(&sc->mtx);
1387 * Move the blockif request back to the free list
1389 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1391 if (pending && !err) {
1392 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1396 if (!err && aior->done == aior->len) {
1397 tfd = ATA_S_READY | ATA_S_DSC;
1398 hdr->prdbc = aior->len;
1400 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1402 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1406 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1407 ahci_write_fis_d2h(p, slot, cfis, tfd);
1410 pthread_mutex_unlock(&sc->mtx);
1411 DPRINTF("%s exit\n", __func__);
1415 pci_ahci_ioreq_init(struct ahci_port *pr)
1417 struct ahci_ioreq *vr;
1420 pr->ioqsz = blockif_queuesz(pr->bctx);
1421 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1422 STAILQ_INIT(&pr->iofhd);
1425 * Add all i/o request entries to the free queue
1427 for (i = 0; i < pr->ioqsz; i++) {
1431 vr->io_req.br_callback = ata_ioreq_cb;
1433 vr->io_req.br_callback = atapi_ioreq_cb;
1434 vr->io_req.br_param = vr;
1435 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_list);
1440 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1442 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1443 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1444 struct ahci_port *p = &sc->port[port];
1446 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1447 port, offset, value);
1466 p->ie = value & 0xFDC000FF;
1467 ahci_generate_intr(sc);
1473 if (!(value & AHCI_P_CMD_ST)) {
1474 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
1480 p->cmd |= AHCI_P_CMD_CR;
1481 clb = (uint64_t)p->clbu << 32 | p->clb;
1482 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1483 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1486 if (value & AHCI_P_CMD_FRE) {
1489 p->cmd |= AHCI_P_CMD_FR;
1490 fb = (uint64_t)p->fbu << 32 | p->fb;
1491 /* we don't support FBSCP, so rfis size is 256Bytes */
1492 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1494 p->cmd &= ~AHCI_P_CMD_FR;
1497 if (value & AHCI_P_CMD_CLO) {
1499 p->cmd &= ~AHCI_P_CMD_CLO;
1502 ahci_handle_port(p);
1508 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1511 if (!(p->cmd & AHCI_P_CMD_ST)) {
1512 if (value & ATA_SC_DET_RESET)
1525 ahci_handle_port(p);
1535 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1537 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1545 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
1548 if (value & AHCI_GHC_HR)
1550 else if (value & AHCI_GHC_IE) {
1551 sc->ghc |= AHCI_GHC_IE;
1552 ahci_generate_intr(sc);
1557 ahci_generate_intr(sc);
1565 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1566 int baridx, uint64_t offset, int size, uint64_t value)
1568 struct pci_ahci_softc *sc = pi->pi_arg;
1570 assert(baridx == 5);
1573 pthread_mutex_lock(&sc->mtx);
1575 if (offset < AHCI_OFFSET)
1576 pci_ahci_host_write(sc, offset, value);
1577 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1578 pci_ahci_port_write(sc, offset, value);
1580 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
1582 pthread_mutex_unlock(&sc->mtx);
1586 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
1602 uint32_t *p = &sc->cap;
1603 p += (offset - AHCI_CAP) / sizeof(uint32_t);
1611 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
1618 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
1621 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1622 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1642 uint32_t *p= &sc->port[port].clb;
1643 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
1652 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
1653 port, offset, value);
1659 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1660 uint64_t offset, int size)
1662 struct pci_ahci_softc *sc = pi->pi_arg;
1665 assert(baridx == 5);
1668 pthread_mutex_lock(&sc->mtx);
1670 if (offset < AHCI_OFFSET)
1671 value = pci_ahci_host_read(sc, offset);
1672 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1673 value = pci_ahci_port_read(sc, offset);
1676 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
1679 pthread_mutex_unlock(&sc->mtx);
1685 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
1687 char bident[sizeof("XX:X:X")];
1688 struct blockif_ctxt *bctxt;
1689 struct pci_ahci_softc *sc;
1695 fprintf(stderr, "pci_ahci: backing device required\n");
1700 dbg = fopen("/tmp/log", "w+");
1703 sc = malloc(sizeof(struct pci_ahci_softc));
1704 memset(sc, 0, sizeof(struct pci_ahci_softc));
1707 sc->ports = MAX_PORTS;
1710 * Only use port 0 for a backing device. All other ports will be
1713 sc->port[0].atapi = atapi;
1716 * Attempt to open the backing image. Use the PCI
1717 * slot/func/ahci_port for the identifier string
1718 * since that uniquely identifies a storage device.
1720 snprintf(bident, sizeof(bident), "%d:%d:%d", pi->pi_slot, pi->pi_func,
1722 bctxt = blockif_open(opts, bident);
1723 if (bctxt == NULL) {
1727 sc->port[0].bctx = bctxt;
1728 sc->port[0].pr_sc = sc;
1731 * Allocate blockif request structures and add them
1734 pci_ahci_ioreq_init(&sc->port[0]);
1736 pthread_mutex_init(&sc->mtx, NULL);
1738 /* Intel ICH8 AHCI */
1739 slots = sc->port[0].ioqsz;
1743 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
1744 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
1745 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
1746 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
1747 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
1749 /* Only port 0 implemented */
1752 sc->cap2 = AHCI_CAP2_APST;
1755 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
1756 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
1757 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
1758 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
1759 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
1760 pci_emul_add_msicap(pi, 1);
1761 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
1762 AHCI_OFFSET + sc->ports * AHCI_STEP);
1766 blockif_close(sc->port[0].bctx);
1774 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1777 return (pci_ahci_init(ctx, pi, opts, 0));
1781 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1784 return (pci_ahci_init(ctx, pi, opts, 1));
1788 * Use separate emulation names to distinguish drive and atapi devices
1790 struct pci_devemu pci_de_ahci_hd = {
1791 .pe_emu = "ahci-hd",
1792 .pe_init = pci_ahci_hd_init,
1793 .pe_barwrite = pci_ahci_write,
1794 .pe_barread = pci_ahci_read
1796 PCI_EMUL_SET(pci_de_ahci_hd);
1798 struct pci_devemu pci_de_ahci_cd = {
1799 .pe_emu = "ahci-cd",
1800 .pe_init = pci_ahci_atapi_init,
1801 .pe_barwrite = pci_ahci_write,
1802 .pe_barread = pci_ahci_read
1804 PCI_EMUL_SET(pci_de_ahci_cd);