2 * Copyright (c) 2012 NetApp, Inc.
3 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/types.h>
34 #include <dev/ic/ns16550.h>
47 #include "uart_emul.h"
49 #define COM1_BASE 0x3F8
51 #define COM2_BASE 0x2F8
54 #define DEFAULT_RCLK 1843200
55 #define DEFAULT_BAUD 9600
57 #define FCR_RX_MASK 0xC0
62 #define MSR_DELTA_MASK 0x0f
65 #define REG_SCR com_scr
70 static bool uart_stdio; /* stdio in use for i/o */
71 static struct termios tio_stdio_orig;
78 { COM1_BASE, COM1_IRQ, false},
79 { COM2_BASE, COM2_IRQ, false},
82 #define UART_NLDEVS (sizeof(uart_lres) / sizeof(uart_lres[0]))
86 int rindex; /* index to read from */
87 int windex; /* index to write to */
88 int num; /* number of characters in the fifo */
89 int size; /* size of the fifo */
94 int fd; /* tty device file descriptor */
95 struct termios tio_orig, tio_new; /* I/O Terminals */
99 pthread_mutex_t mtx; /* protects all softc elements */
100 uint8_t data; /* Data register (R/W) */
101 uint8_t ier; /* Interrupt enable register (R/W) */
102 uint8_t lcr; /* Line control register (R/W) */
103 uint8_t mcr; /* Modem control register (R/W) */
104 uint8_t lsr; /* Line status register (R/W) */
105 uint8_t msr; /* Modem status register (R/W) */
106 uint8_t fcr; /* FIFO control register (W) */
107 uint8_t scr; /* Scratch register (R/W) */
109 uint8_t dll; /* Baudrate divisor latch LSB */
110 uint8_t dlh; /* Baudrate divisor latch MSB */
115 bool thre_int_pending; /* THRE interrupt pending */
118 uart_intr_func_t intr_assert;
119 uart_intr_func_t intr_deassert;
122 static void uart_drain(int fd, enum ev_type ev, void *arg);
128 tcsetattr(STDIN_FILENO, TCSANOW, &tio_stdio_orig);
132 ttyopen(struct ttyfd *tf)
135 tcgetattr(tf->fd, &tf->tio_orig);
137 tf->tio_new = tf->tio_orig;
138 cfmakeraw(&tf->tio_new);
139 tf->tio_new.c_cflag |= CLOCAL;
140 tcsetattr(tf->fd, TCSANOW, &tf->tio_new);
142 if (tf->fd == STDIN_FILENO) {
143 tio_stdio_orig = tf->tio_orig;
149 tty_char_available(struct ttyfd *tf)
155 FD_SET(tf->fd, &rfds);
158 if (select(tf->fd + 1, &rfds, NULL, NULL, &tv) > 0 ) {
166 ttyread(struct ttyfd *tf)
170 if (tty_char_available(tf)) {
171 read(tf->fd, &rb, 1);
179 ttywrite(struct ttyfd *tf, unsigned char wb)
182 (void)write(tf->fd, &wb, 1);
186 fifo_reset(struct fifo *fifo, int size)
189 bzero(fifo, sizeof(struct fifo));
194 fifo_putchar(struct fifo *fifo, uint8_t ch)
197 if (fifo->num < fifo->size) {
198 fifo->buf[fifo->windex] = ch;
199 fifo->windex = (fifo->windex + 1) % fifo->size;
207 fifo_getchar(struct fifo *fifo)
212 c = fifo->buf[fifo->rindex];
213 fifo->rindex = (fifo->rindex + 1) % fifo->size;
221 fifo_numchars(struct fifo *fifo)
228 fifo_available(struct fifo *fifo)
231 return (fifo->num < fifo->size);
235 uart_opentty(struct uart_softc *sc)
240 mev = mevent_add(sc->tty.fd, EVF_READ, uart_drain, sc);
245 * The IIR returns a prioritized interrupt reason:
246 * - receive data available
247 * - transmit holding register empty
248 * - modem status change
250 * Return an interrupt reason if one is available.
253 uart_intr_reason(struct uart_softc *sc)
256 if ((sc->lsr & LSR_OE) != 0 && (sc->ier & IER_ERLS) != 0)
258 else if (fifo_numchars(&sc->rxfifo) > 0 && (sc->ier & IER_ERXRDY) != 0)
260 else if (sc->thre_int_pending && (sc->ier & IER_ETXRDY) != 0)
262 else if ((sc->msr & MSR_DELTA_MASK) != 0 && (sc->ier & IER_EMSC) != 0)
269 uart_reset(struct uart_softc *sc)
273 divisor = DEFAULT_RCLK / DEFAULT_BAUD / 16;
275 sc->dlh = divisor >> 16;
277 fifo_reset(&sc->rxfifo, 1); /* no fifo until enabled by software */
281 * Toggle the COM port's intr pin depending on whether or not we have an
282 * interrupt condition to report to the processor.
285 uart_toggle_intr(struct uart_softc *sc)
289 intr_reason = uart_intr_reason(sc);
291 if (intr_reason == IIR_NOPEND)
292 (*sc->intr_deassert)(sc->arg);
294 (*sc->intr_assert)(sc->arg);
298 uart_drain(int fd, enum ev_type ev, void *arg)
300 struct uart_softc *sc;
305 assert(fd == sc->tty.fd);
306 assert(ev == EVF_READ);
309 * This routine is called in the context of the mevent thread
310 * to take out the softc lock to protect against concurrent
311 * access from a vCPU i/o exit
313 pthread_mutex_lock(&sc->mtx);
315 if ((sc->mcr & MCR_LOOPBACK) != 0) {
316 (void) ttyread(&sc->tty);
318 while (fifo_available(&sc->rxfifo) &&
319 ((ch = ttyread(&sc->tty)) != -1)) {
320 fifo_putchar(&sc->rxfifo, ch);
322 uart_toggle_intr(sc);
325 pthread_mutex_unlock(&sc->mtx);
329 uart_write(struct uart_softc *sc, int offset, uint8_t value)
334 pthread_mutex_lock(&sc->mtx);
337 * Take care of the special case DLAB accesses first
339 if ((sc->lcr & LCR_DLAB) != 0) {
340 if (offset == REG_DLL) {
345 if (offset == REG_DLH) {
353 if (sc->mcr & MCR_LOOPBACK) {
354 if (fifo_putchar(&sc->rxfifo, value) != 0)
356 } else if (sc->tty.opened) {
357 ttywrite(&sc->tty, value);
358 } /* else drop on floor */
359 sc->thre_int_pending = true;
363 * Apply mask so that bits 4-7 are 0
364 * Also enables bits 0-3 only if they're 1
366 sc->ier = value & 0x0F;
370 * When moving from FIFO and 16450 mode and vice versa,
371 * the FIFO contents are reset.
373 if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) {
374 fifosz = (value & FCR_ENABLE) ? FIFOSZ : 1;
375 fifo_reset(&sc->rxfifo, fifosz);
379 * The FCR_ENABLE bit must be '1' for the programming
380 * of other FCR bits to be effective.
382 if ((value & FCR_ENABLE) == 0) {
385 if ((value & FCR_RCV_RST) != 0)
386 fifo_reset(&sc->rxfifo, FIFOSZ);
389 (FCR_ENABLE | FCR_DMA | FCR_RX_MASK);
396 /* Apply mask so that bits 5-7 are 0 */
397 sc->mcr = value & 0x1F;
400 if (sc->mcr & MCR_LOOPBACK) {
402 * In the loopback mode certain bits from the
403 * MCR are reflected back into MSR
405 if (sc->mcr & MCR_RTS)
407 if (sc->mcr & MCR_DTR)
409 if (sc->mcr & MCR_OUT1)
411 if (sc->mcr & MCR_OUT2)
416 * Detect if there has been any change between the
417 * previous and the new value of MSR. If there is
418 * then assert the appropriate MSR delta bit.
420 if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS))
422 if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR))
424 if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD))
426 if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
430 * Update the value of MSR while retaining the delta
433 sc->msr &= MSR_DELTA_MASK;
438 * Line status register is not meant to be written to
439 * during normal operation.
444 * As far as I can tell MSR is a read-only register.
455 uart_toggle_intr(sc);
456 pthread_mutex_unlock(&sc->mtx);
460 uart_read(struct uart_softc *sc, int offset)
462 uint8_t iir, intr_reason, reg;
464 pthread_mutex_lock(&sc->mtx);
467 * Take care of the special case DLAB accesses first
469 if ((sc->lcr & LCR_DLAB) != 0) {
470 if (offset == REG_DLL) {
475 if (offset == REG_DLH) {
483 reg = fifo_getchar(&sc->rxfifo);
489 iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0;
491 intr_reason = uart_intr_reason(sc);
494 * Deal with side effects of reading the IIR register
496 if (intr_reason == IIR_TXRDY)
497 sc->thre_int_pending = false;
510 /* Transmitter is always ready for more data */
511 sc->lsr |= LSR_TEMT | LSR_THRE;
513 /* Check for new receive data */
514 if (fifo_numchars(&sc->rxfifo) > 0)
515 sc->lsr |= LSR_RXRDY;
517 sc->lsr &= ~LSR_RXRDY;
521 /* The LSR_OE bit is cleared on LSR read */
526 * MSR delta bits are cleared on read
529 sc->msr &= ~MSR_DELTA_MASK;
540 uart_toggle_intr(sc);
541 pthread_mutex_unlock(&sc->mtx);
547 uart_legacy_alloc(int which, int *baseaddr, int *irq)
550 if (which < 0 || which >= UART_NLDEVS || uart_lres[which].inuse)
553 uart_lres[which].inuse = true;
554 *baseaddr = uart_lres[which].baseaddr;
555 *irq = uart_lres[which].irq;
561 uart_init(uart_intr_func_t intr_assert, uart_intr_func_t intr_deassert,
564 struct uart_softc *sc;
566 sc = malloc(sizeof(struct uart_softc));
567 bzero(sc, sizeof(struct uart_softc));
570 sc->intr_assert = intr_assert;
571 sc->intr_deassert = intr_deassert;
573 pthread_mutex_init(&sc->mtx, NULL);
581 uart_tty_backend(struct uart_softc *sc, const char *opts)
588 fd = open(opts, O_RDWR);
589 if (fd > 0 && isatty(fd)) {
591 sc->tty.opened = true;
599 uart_set_backend(struct uart_softc *sc, const char *opts)
608 if (strcmp("stdio", opts) == 0) {
610 sc->tty.fd = STDIN_FILENO;
611 sc->tty.opened = true;
615 } else if (uart_tty_backend(sc, opts) == 0) {