1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 static const struct objfile_data *mips_pdr_data;
59 static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off);
60 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
62 /* A useful bit in the CP0 status register (PS_REGNUM). */
63 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
64 #define ST0_FR (1 << 26)
66 /* The sizes of floating point registers. */
70 MIPS_FPU_SINGLE_REGSIZE = 4,
71 MIPS_FPU_DOUBLE_REGSIZE = 8
75 static const char *mips_abi_string;
77 static const char *mips_abi_strings[] = {
88 struct frame_extra_info
90 mips_extra_func_info_t proc_desc;
94 /* Various MIPS ISA options (related to stack analysis) can be
95 overridden dynamically. Establish an enum/array for managing
98 static const char size_auto[] = "auto";
99 static const char size_32[] = "32";
100 static const char size_64[] = "64";
102 static const char *size_enums[] = {
109 /* Some MIPS boards don't support floating point while others only
110 support single-precision floating-point operations. See also
111 FP_REGISTER_DOUBLE. */
115 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE /* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto = 1;
124 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
126 static int mips_debug = 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi;
136 enum mips_abi found_abi;
137 enum mips_fpu_type mips_fpu_type;
138 int mips_last_arg_regnum;
139 int mips_last_fp_arg_regnum;
140 int mips_default_saved_regsize;
141 int mips_fp_register_double;
142 int mips_default_stack_argsize;
143 int default_mask_address_p;
144 /* Is the target using 64-bit raw integer registers but only
145 storing a left-aligned 32-bit value in each? */
146 int mips64_transfers_32bit_regs_p;
147 /* Indexes for various registers. IRIX and embedded have
148 different values. This contains the "public" fields. Don't
149 add any that do not need to be public. */
150 const struct mips_regnum *regnum;
151 /* Register names table for the current register set. */
152 const char **mips_processor_reg_names;
155 const struct mips_regnum *
156 mips_regnum (struct gdbarch *gdbarch)
158 return gdbarch_tdep (gdbarch)->regnum;
162 mips_fpa0_regnum (struct gdbarch *gdbarch)
164 return mips_regnum (gdbarch)->fp0 + 12;
167 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
168 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
170 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
172 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
174 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
176 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
177 functions to test, set, or clear bit 0 of addresses. */
180 is_mips16_addr (CORE_ADDR addr)
186 make_mips16_addr (CORE_ADDR addr)
192 unmake_mips16_addr (CORE_ADDR addr)
194 return ((addr) & ~1);
197 /* Return the contents of register REGNUM as a signed integer. */
200 read_signed_register (int regnum)
202 void *buf = alloca (register_size (current_gdbarch, regnum));
203 deprecated_read_register_gen (regnum, buf);
204 return (extract_signed_integer
205 (buf, register_size (current_gdbarch, regnum)));
209 read_signed_register_pid (int regnum, ptid_t ptid)
214 if (ptid_equal (ptid, inferior_ptid))
215 return read_signed_register (regnum);
217 save_ptid = inferior_ptid;
219 inferior_ptid = ptid;
221 retval = read_signed_register (regnum);
223 inferior_ptid = save_ptid;
228 /* Return the MIPS ABI associated with GDBARCH. */
230 mips_abi (struct gdbarch *gdbarch)
232 return gdbarch_tdep (gdbarch)->mips_abi;
236 mips_regsize (struct gdbarch *gdbarch)
238 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
239 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
242 /* Return the currently configured (or set) saved register size. */
244 static const char *mips_saved_regsize_string = size_auto;
247 mips_saved_regsize (struct gdbarch_tdep *tdep)
249 if (mips_saved_regsize_string == size_auto)
250 return tdep->mips_default_saved_regsize;
251 else if (mips_saved_regsize_string == size_64)
253 else /* if (mips_saved_regsize_string == size_32) */
257 /* Functions for setting and testing a bit in a minimal symbol that
258 marks it as 16-bit function. The MSB of the minimal symbol's
259 "info" field is used for this purpose.
261 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
262 i.e. refers to a 16-bit function, and sets a "special" bit in a
263 minimal symbol to mark it as a 16-bit function
265 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
268 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
270 if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16)
272 MSYMBOL_INFO (msym) = (char *)
273 (((long) MSYMBOL_INFO (msym)) | 0x80000000);
274 SYMBOL_VALUE_ADDRESS (msym) |= 1;
279 msymbol_is_special (struct minimal_symbol *msym)
281 return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0);
284 /* XFER a value from the big/little/left end of the register.
285 Depending on the size of the value it might occupy the entire
286 register or just part of it. Make an allowance for this, aligning
287 things accordingly. */
290 mips_xfer_register (struct regcache *regcache, int reg_num, int length,
291 enum bfd_endian endian, bfd_byte * in,
292 const bfd_byte * out, int buf_offset)
295 gdb_assert (reg_num >= NUM_REGS);
296 /* Need to transfer the left or right part of the register, based on
297 the targets byte order. */
301 reg_offset = register_size (current_gdbarch, reg_num) - length;
303 case BFD_ENDIAN_LITTLE:
306 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
310 internal_error (__FILE__, __LINE__, "bad switch");
313 fprintf_unfiltered (gdb_stderr,
314 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
315 reg_num, reg_offset, buf_offset, length);
316 if (mips_debug && out != NULL)
319 fprintf_unfiltered (gdb_stdlog, "out ");
320 for (i = 0; i < length; i++)
321 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
324 regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
327 regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
329 if (mips_debug && in != NULL)
332 fprintf_unfiltered (gdb_stdlog, "in ");
333 for (i = 0; i < length; i++)
334 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
337 fprintf_unfiltered (gdb_stdlog, "\n");
340 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
341 compatiblity mode. A return value of 1 means that we have
342 physical 64-bit registers, but should treat them as 32-bit registers. */
345 mips2_fp_compat (void)
347 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
349 if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) ==
354 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
355 in all the places we deal with FP registers. PR gdb/413. */
356 /* Otherwise check the FR bit in the status register - it controls
357 the FP compatiblity mode. If it is clear we are in compatibility
359 if ((read_register (PS_REGNUM) & ST0_FR) == 0)
366 /* Indicate that the ABI makes use of double-precision registers
367 provided by the FPU (rather than combining pairs of registers to
368 form double-precision values). See also MIPS_FPU_TYPE. */
369 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
371 /* The amount of space reserved on the stack for registers. This is
372 different to MIPS_SAVED_REGSIZE as it determines the alignment of
373 data allocated after the registers have run out. */
375 static const char *mips_stack_argsize_string = size_auto;
378 mips_stack_argsize (struct gdbarch_tdep *tdep)
380 if (mips_stack_argsize_string == size_auto)
381 return tdep->mips_default_stack_argsize;
382 else if (mips_stack_argsize_string == size_64)
384 else /* if (mips_stack_argsize_string == size_32) */
388 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
390 static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR,
391 struct frame_info *, int);
393 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
395 static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
397 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
399 static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc,
400 struct frame_info *next_frame,
403 static CORE_ADDR after_prologue (CORE_ADDR pc,
404 mips_extra_func_info_t proc_desc);
406 static struct type *mips_float_register_type (void);
407 static struct type *mips_double_register_type (void);
409 /* The list of available "set mips " and "show mips " commands */
411 static struct cmd_list_element *setmipscmdlist = NULL;
412 static struct cmd_list_element *showmipscmdlist = NULL;
414 /* Integer registers 0 thru 31 are handled explicitly by
415 mips_register_name(). Processor specific registers 32 and above
416 are listed in the followign tables. */
419 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
423 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
424 "sr", "lo", "hi", "bad", "cause", "pc",
425 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
426 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
427 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
428 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
429 "fsr", "fir", "" /*"fp" */ , "",
430 "", "", "", "", "", "", "", "",
431 "", "", "", "", "", "", "", "",
434 /* Names of IDT R3041 registers. */
436 static const char *mips_r3041_reg_names[] = {
437 "sr", "lo", "hi", "bad", "cause", "pc",
438 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
439 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
440 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
441 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
442 "fsr", "fir", "", /*"fp" */ "",
443 "", "", "bus", "ccfg", "", "", "", "",
444 "", "", "port", "cmp", "", "", "epc", "prid",
447 /* Names of tx39 registers. */
449 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
450 "sr", "lo", "hi", "bad", "cause", "pc",
451 "", "", "", "", "", "", "", "",
452 "", "", "", "", "", "", "", "",
453 "", "", "", "", "", "", "", "",
454 "", "", "", "", "", "", "", "",
456 "", "", "", "", "", "", "", "",
457 "", "", "config", "cache", "debug", "depc", "epc", ""
460 /* Names of IRIX registers. */
461 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
462 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
463 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
464 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
465 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
466 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
470 /* Return the name of the register corresponding to REGNO. */
472 mips_register_name (int regno)
474 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
475 /* GPR names for all ABIs other than n32/n64. */
476 static char *mips_gpr_names[] = {
477 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
478 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
479 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
480 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
483 /* GPR names for n32 and n64 ABIs. */
484 static char *mips_n32_n64_gpr_names[] = {
485 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
486 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
487 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
488 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
491 enum mips_abi abi = mips_abi (current_gdbarch);
493 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
494 don't make the raw register names visible. */
495 int rawnum = regno % NUM_REGS;
496 if (regno < NUM_REGS)
499 /* The MIPS integer registers are always mapped from 0 to 31. The
500 names of the registers (which reflects the conventions regarding
501 register use) vary depending on the ABI. */
502 if (0 <= rawnum && rawnum < 32)
504 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
505 return mips_n32_n64_gpr_names[rawnum];
507 return mips_gpr_names[rawnum];
509 else if (32 <= rawnum && rawnum < NUM_REGS)
511 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
512 return tdep->mips_processor_reg_names[rawnum - 32];
515 internal_error (__FILE__, __LINE__,
516 "mips_register_name: bad register number %d", rawnum);
519 /* Return the groups that a MIPS register can be categorised into. */
522 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
523 struct reggroup *reggroup)
528 int rawnum = regnum % NUM_REGS;
529 int pseudo = regnum / NUM_REGS;
530 if (reggroup == all_reggroup)
532 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
533 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
534 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
535 (gdbarch), as not all architectures are multi-arch. */
536 raw_p = rawnum < NUM_REGS;
537 if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0')
539 if (reggroup == float_reggroup)
540 return float_p && pseudo;
541 if (reggroup == vector_reggroup)
542 return vector_p && pseudo;
543 if (reggroup == general_reggroup)
544 return (!vector_p && !float_p) && pseudo;
545 /* Save the pseudo registers. Need to make certain that any code
546 extracting register values from a saved register cache also uses
548 if (reggroup == save_reggroup)
549 return raw_p && pseudo;
550 /* Restore the same pseudo register. */
551 if (reggroup == restore_reggroup)
552 return raw_p && pseudo;
556 /* Map the symbol table registers which live in the range [1 *
557 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
558 registers. Take care of alignment and size problems. */
561 mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
562 int cookednum, void *buf)
564 int rawnum = cookednum % NUM_REGS;
565 gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
566 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
567 regcache_raw_read (regcache, rawnum, buf);
568 else if (register_size (gdbarch, rawnum) >
569 register_size (gdbarch, cookednum))
571 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
572 || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
573 regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
575 regcache_raw_read_part (regcache, rawnum, 4, 4, buf);
578 internal_error (__FILE__, __LINE__, "bad register size");
582 mips_pseudo_register_write (struct gdbarch *gdbarch,
583 struct regcache *regcache, int cookednum,
586 int rawnum = cookednum % NUM_REGS;
587 gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
588 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
589 regcache_raw_write (regcache, rawnum, buf);
590 else if (register_size (gdbarch, rawnum) >
591 register_size (gdbarch, cookednum))
593 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
594 || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
595 regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
597 regcache_raw_write_part (regcache, rawnum, 4, 4, buf);
600 internal_error (__FILE__, __LINE__, "bad register size");
603 /* Table to translate MIPS16 register field to actual register number. */
604 static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
606 /* Heuristic_proc_start may hunt through the text section for a long
607 time across a 2400 baud serial line. Allows the user to limit this
610 static unsigned int heuristic_fence_post = 0;
612 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
613 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
614 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
615 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
616 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
617 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
618 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
619 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
620 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
621 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
622 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
623 this will corrupt pdr.iline. Fortunately we don't use it. */
624 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
625 #define _PROC_MAGIC_ 0x0F0F0F0F
626 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
627 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
629 struct linked_proc_info
631 struct mips_extra_func_info info;
632 struct linked_proc_info *next;
634 *linked_proc_desc_table = NULL;
636 /* Number of bytes of storage in the actual machine representation for
637 register N. NOTE: This defines the pseudo register type so need to
638 rebuild the architecture vector. */
640 static int mips64_transfers_32bit_regs_p = 0;
643 set_mips64_transfers_32bit_regs (char *args, int from_tty,
644 struct cmd_list_element *c)
646 struct gdbarch_info info;
647 gdbarch_info_init (&info);
648 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
649 instead of relying on globals. Doing that would let generic code
650 handle the search for this specific architecture. */
651 if (!gdbarch_update_p (info))
653 mips64_transfers_32bit_regs_p = 0;
654 error ("32-bit compatibility mode not supported");
658 /* Convert to/from a register and the corresponding memory value. */
661 mips_convert_register_p (int regnum, struct type *type)
663 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
664 && register_size (current_gdbarch, regnum) == 4
665 && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0
666 && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32
667 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
671 mips_register_to_value (struct frame_info *frame, int regnum,
672 struct type *type, void *to)
674 get_frame_register (frame, regnum + 0, (char *) to + 4);
675 get_frame_register (frame, regnum + 1, (char *) to + 0);
679 mips_value_to_register (struct frame_info *frame, int regnum,
680 struct type *type, const void *from)
682 put_frame_register (frame, regnum + 0, (const char *) from + 4);
683 put_frame_register (frame, regnum + 1, (const char *) from + 0);
686 /* Return the GDB type object for the "standard" data type of data in
690 mips_register_type (struct gdbarch *gdbarch, int regnum)
692 gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS);
693 if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0
694 && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32)
696 /* The floating-point registers raw, or cooked, always match
697 mips_regsize(), and also map 1:1, byte for byte. */
698 switch (gdbarch_byte_order (gdbarch))
701 if (mips_regsize (gdbarch) == 4)
702 return builtin_type_ieee_single_big;
704 return builtin_type_ieee_double_big;
705 case BFD_ENDIAN_LITTLE:
706 if (mips_regsize (gdbarch) == 4)
707 return builtin_type_ieee_single_little;
709 return builtin_type_ieee_double_little;
710 case BFD_ENDIAN_UNKNOWN:
712 internal_error (__FILE__, __LINE__, "bad switch");
716 (NUM_REGS + mips_regnum (current_gdbarch)->fp_control_status)
717 && regnum <= NUM_REGS + LAST_EMBED_REGNUM)
718 /* The pseudo/cooked view of the embedded registers is always
719 32-bit. The raw view is handled below. */
720 return builtin_type_int32;
721 else if (regnum >= NUM_REGS && mips_regsize (gdbarch)
722 && gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
723 /* The target, while using a 64-bit register buffer, is only
724 transfering 32-bits of each integer register. Reflect this in
725 the cooked/pseudo register value. */
726 return builtin_type_int32;
727 else if (mips_regsize (gdbarch) == 8)
729 return builtin_type_int64;
732 return builtin_type_int32;
735 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
740 return read_signed_register (SP_REGNUM);
743 /* Should the upper word of 64-bit addresses be zeroed? */
744 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
747 mips_mask_address_p (struct gdbarch_tdep *tdep)
749 switch (mask_address_var)
751 case AUTO_BOOLEAN_TRUE:
753 case AUTO_BOOLEAN_FALSE:
756 case AUTO_BOOLEAN_AUTO:
757 return tdep->default_mask_address_p;
759 internal_error (__FILE__, __LINE__, "mips_mask_address_p: bad switch");
765 show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c)
767 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
768 switch (mask_address_var)
770 case AUTO_BOOLEAN_TRUE:
771 printf_filtered ("The 32 bit mips address mask is enabled\n");
773 case AUTO_BOOLEAN_FALSE:
774 printf_filtered ("The 32 bit mips address mask is disabled\n");
776 case AUTO_BOOLEAN_AUTO:
778 ("The 32 bit address mask is set automatically. Currently %s\n",
779 mips_mask_address_p (tdep) ? "enabled" : "disabled");
782 internal_error (__FILE__, __LINE__, "show_mask_address: bad switch");
787 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
790 pc_is_mips16 (bfd_vma memaddr)
792 struct minimal_symbol *sym;
794 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
795 if (is_mips16_addr (memaddr))
798 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
799 the high bit of the info field. Use this to decide if the function is
800 MIPS16 or normal MIPS. */
801 sym = lookup_minimal_symbol_by_pc (memaddr);
803 return msymbol_is_special (sym);
808 /* MIPS believes that the PC has a sign extended value. Perhaphs the
809 all registers should be sign extended for simplicity? */
812 mips_read_pc (ptid_t ptid)
814 return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid);
818 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
820 return frame_unwind_register_signed (next_frame,
821 NUM_REGS + mips_regnum (gdbarch)->pc);
824 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
825 dummy frame. The frame ID's base needs to match the TOS value
826 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
829 static struct frame_id
830 mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
832 return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + SP_REGNUM),
833 frame_pc_unwind (next_frame));
837 mips_write_pc (CORE_ADDR pc, ptid_t ptid)
839 write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid);
842 /* This returns the PC of the first inst after the prologue. If we can't
843 find the prologue, then return 0. */
846 after_prologue (CORE_ADDR pc, mips_extra_func_info_t proc_desc)
848 struct symtab_and_line sal;
849 CORE_ADDR func_addr, func_end;
851 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
852 to read the stack pointer from the current machine state, because
853 the current machine state has nothing to do with the information
854 we need from the proc_desc; and the process may or may not exist
857 proc_desc = find_proc_desc (pc, NULL, 0);
861 /* If function is frameless, then we need to do it the hard way. I
862 strongly suspect that frameless always means prologueless... */
863 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
864 && PROC_FRAME_OFFSET (proc_desc) == 0)
868 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
869 return 0; /* Unknown */
871 sal = find_pc_line (func_addr, 0);
873 if (sal.end < func_end)
876 /* The line after the prologue is after the end of the function. In this
877 case, tell the caller to find the prologue the hard way. */
882 /* Decode a MIPS32 instruction that saves a register in the stack, and
883 set the appropriate bit in the general register mask or float register mask
884 to indicate which register is saved. This is a helper function
885 for mips_find_saved_regs. */
888 mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
889 unsigned long *float_mask)
893 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
894 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
895 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
897 /* It might be possible to use the instruction to
898 find the offset, rather than the code below which
899 is based on things being in a certain order in the
900 frame, but figuring out what the instruction's offset
901 is relative to might be a little tricky. */
902 reg = (inst & 0x001f0000) >> 16;
903 *gen_mask |= (1 << reg);
905 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
906 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
907 || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
910 reg = ((inst & 0x001f0000) >> 16);
911 *float_mask |= (1 << reg);
915 /* Decode a MIPS16 instruction that saves a register in the stack, and
916 set the appropriate bit in the general register or float register mask
917 to indicate which register is saved. This is a helper function
918 for mips_find_saved_regs. */
921 mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask)
923 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
925 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
926 *gen_mask |= (1 << reg);
928 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
930 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
931 *gen_mask |= (1 << reg);
933 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
934 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
935 *gen_mask |= (1 << RA_REGNUM);
939 /* Fetch and return instruction from the specified location. If the PC
940 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
943 mips_fetch_instruction (CORE_ADDR addr)
945 char buf[MIPS_INSTLEN];
949 if (pc_is_mips16 (addr))
951 instlen = MIPS16_INSTLEN;
952 addr = unmake_mips16_addr (addr);
955 instlen = MIPS_INSTLEN;
956 status = read_memory_nobpt (addr, buf, instlen);
958 memory_error (status, addr);
959 return extract_unsigned_integer (buf, instlen);
963 mips16_fetch_instruction (CORE_ADDR addr)
965 char buf[MIPS_INSTLEN];
969 instlen = MIPS16_INSTLEN;
970 addr = unmake_mips16_addr (addr);
971 status = read_memory_nobpt (addr, buf, instlen);
973 memory_error (status, addr);
974 return extract_unsigned_integer (buf, instlen);
978 mips32_fetch_instruction (CORE_ADDR addr)
980 char buf[MIPS_INSTLEN];
983 instlen = MIPS_INSTLEN;
984 status = read_memory_nobpt (addr, buf, instlen);
986 memory_error (status, addr);
987 return extract_unsigned_integer (buf, instlen);
991 /* These the fields of 32 bit mips instructions */
992 #define mips32_op(x) (x >> 26)
993 #define itype_op(x) (x >> 26)
994 #define itype_rs(x) ((x >> 21) & 0x1f)
995 #define itype_rt(x) ((x >> 16) & 0x1f)
996 #define itype_immediate(x) (x & 0xffff)
998 #define jtype_op(x) (x >> 26)
999 #define jtype_target(x) (x & 0x03ffffff)
1001 #define rtype_op(x) (x >> 26)
1002 #define rtype_rs(x) ((x >> 21) & 0x1f)
1003 #define rtype_rt(x) ((x >> 16) & 0x1f)
1004 #define rtype_rd(x) ((x >> 11) & 0x1f)
1005 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1006 #define rtype_funct(x) (x & 0x3f)
1009 mips32_relative_offset (unsigned long inst)
1012 x = itype_immediate (inst);
1013 if (x & 0x8000) /* sign bit set */
1015 x |= 0xffff0000; /* sign extension */
1021 /* Determine whate to set a single step breakpoint while considering
1022 branch prediction */
1024 mips32_next_pc (CORE_ADDR pc)
1028 inst = mips_fetch_instruction (pc);
1029 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1031 if (itype_op (inst) >> 2 == 5)
1032 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1034 op = (itype_op (inst) & 0x03);
1044 goto greater_branch;
1049 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
1050 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1052 int tf = itype_rt (inst) & 0x01;
1053 int cnum = itype_rt (inst) >> 2;
1055 read_signed_register (mips_regnum (current_gdbarch)->
1057 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
1059 if (((cond >> cnum) & 0x01) == tf)
1060 pc += mips32_relative_offset (inst) + 4;
1065 pc += 4; /* Not a branch, next instruction is easy */
1068 { /* This gets way messy */
1070 /* Further subdivide into SPECIAL, REGIMM and other */
1071 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
1073 case 0: /* SPECIAL */
1074 op = rtype_funct (inst);
1079 /* Set PC to that address */
1080 pc = read_signed_register (rtype_rs (inst));
1086 break; /* end SPECIAL */
1087 case 1: /* REGIMM */
1089 op = itype_rt (inst); /* branch condition */
1094 case 16: /* BLTZAL */
1095 case 18: /* BLTZALL */
1097 if (read_signed_register (itype_rs (inst)) < 0)
1098 pc += mips32_relative_offset (inst) + 4;
1100 pc += 8; /* after the delay slot */
1104 case 17: /* BGEZAL */
1105 case 19: /* BGEZALL */
1106 if (read_signed_register (itype_rs (inst)) >= 0)
1107 pc += mips32_relative_offset (inst) + 4;
1109 pc += 8; /* after the delay slot */
1111 /* All of the other instructions in the REGIMM category */
1116 break; /* end REGIMM */
1121 reg = jtype_target (inst) << 2;
1122 /* Upper four bits get never changed... */
1123 pc = reg + ((pc + 4) & 0xf0000000);
1126 /* FIXME case JALX : */
1129 reg = jtype_target (inst) << 2;
1130 pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */
1131 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1133 break; /* The new PC will be alternate mode */
1134 case 4: /* BEQ, BEQL */
1136 if (read_signed_register (itype_rs (inst)) ==
1137 read_signed_register (itype_rt (inst)))
1138 pc += mips32_relative_offset (inst) + 4;
1142 case 5: /* BNE, BNEL */
1144 if (read_signed_register (itype_rs (inst)) !=
1145 read_signed_register (itype_rt (inst)))
1146 pc += mips32_relative_offset (inst) + 4;
1150 case 6: /* BLEZ, BLEZL */
1151 if (read_signed_register (itype_rs (inst) <= 0))
1152 pc += mips32_relative_offset (inst) + 4;
1158 greater_branch: /* BGTZ, BGTZL */
1159 if (read_signed_register (itype_rs (inst) > 0))
1160 pc += mips32_relative_offset (inst) + 4;
1167 } /* mips32_next_pc */
1169 /* Decoding the next place to set a breakpoint is irregular for the
1170 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1171 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1172 We dont want to set a single step instruction on the extend instruction
1176 /* Lots of mips16 instruction formats */
1177 /* Predicting jumps requires itype,ritype,i8type
1178 and their extensions extItype,extritype,extI8type
1180 enum mips16_inst_fmts
1182 itype, /* 0 immediate 5,10 */
1183 ritype, /* 1 5,3,8 */
1184 rrtype, /* 2 5,3,3,5 */
1185 rritype, /* 3 5,3,3,5 */
1186 rrrtype, /* 4 5,3,3,3,2 */
1187 rriatype, /* 5 5,3,3,1,4 */
1188 shifttype, /* 6 5,3,3,3,2 */
1189 i8type, /* 7 5,3,8 */
1190 i8movtype, /* 8 5,3,3,5 */
1191 i8mov32rtype, /* 9 5,3,5,3 */
1192 i64type, /* 10 5,3,8 */
1193 ri64type, /* 11 5,3,3,5 */
1194 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1195 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1196 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1197 extRRItype, /* 15 5,5,5,5,3,3,5 */
1198 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1199 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1200 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1201 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1202 extRi64type, /* 20 5,6,5,5,3,3,5 */
1203 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1205 /* I am heaping all the fields of the formats into one structure and
1206 then, only the fields which are involved in instruction extension */
1210 unsigned int regx; /* Function in i8 type */
1215 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1216 for the bits which make up the immediatate extension. */
1219 extended_offset (unsigned int extension)
1222 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1224 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1226 value |= extension & 0x01f; /* extract 4:0 */
1230 /* Only call this function if you know that this is an extendable
1231 instruction, It wont malfunction, but why make excess remote memory references?
1232 If the immediate operands get sign extended or somthing, do it after
1233 the extension is performed.
1235 /* FIXME: Every one of these cases needs to worry about sign extension
1236 when the offset is to be used in relative addressing */
1240 fetch_mips_16 (CORE_ADDR pc)
1243 pc &= 0xfffffffe; /* clear the low order bit */
1244 target_read_memory (pc, buf, 2);
1245 return extract_unsigned_integer (buf, 2);
1249 unpack_mips16 (CORE_ADDR pc,
1250 unsigned int extension,
1252 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
1257 switch (insn_format)
1264 value = extended_offset (extension);
1265 value = value << 11; /* rom for the original value */
1266 value |= inst & 0x7ff; /* eleven bits from instruction */
1270 value = inst & 0x7ff;
1271 /* FIXME : Consider sign extension */
1280 { /* A register identifier and an offset */
1281 /* Most of the fields are the same as I type but the
1282 immediate value is of a different length */
1286 value = extended_offset (extension);
1287 value = value << 8; /* from the original instruction */
1288 value |= inst & 0xff; /* eleven bits from instruction */
1289 regx = (extension >> 8) & 0x07; /* or i8 funct */
1290 if (value & 0x4000) /* test the sign bit , bit 26 */
1292 value &= ~0x3fff; /* remove the sign bit */
1298 value = inst & 0xff; /* 8 bits */
1299 regx = (inst >> 8) & 0x07; /* or i8 funct */
1300 /* FIXME: Do sign extension , this format needs it */
1301 if (value & 0x80) /* THIS CONFUSES ME */
1303 value &= 0xef; /* remove the sign bit */
1313 unsigned long value;
1314 unsigned int nexthalf;
1315 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1316 value = value << 16;
1317 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1325 internal_error (__FILE__, __LINE__, "bad switch");
1327 upk->offset = offset;
1334 add_offset_16 (CORE_ADDR pc, int offset)
1336 return ((offset << 2) | ((pc + 2) & (0xf0000000)));
1340 extended_mips16_next_pc (CORE_ADDR pc,
1341 unsigned int extension, unsigned int insn)
1343 int op = (insn >> 11);
1346 case 2: /* Branch */
1349 struct upk_mips16 upk;
1350 unpack_mips16 (pc, extension, insn, itype, &upk);
1351 offset = upk.offset;
1357 pc += (offset << 1) + 2;
1360 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1362 struct upk_mips16 upk;
1363 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1364 pc = add_offset_16 (pc, upk.offset);
1365 if ((insn >> 10) & 0x01) /* Exchange mode */
1366 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1373 struct upk_mips16 upk;
1375 unpack_mips16 (pc, extension, insn, ritype, &upk);
1376 reg = read_signed_register (upk.regx);
1378 pc += (upk.offset << 1) + 2;
1385 struct upk_mips16 upk;
1387 unpack_mips16 (pc, extension, insn, ritype, &upk);
1388 reg = read_signed_register (upk.regx);
1390 pc += (upk.offset << 1) + 2;
1395 case 12: /* I8 Formats btez btnez */
1397 struct upk_mips16 upk;
1399 unpack_mips16 (pc, extension, insn, i8type, &upk);
1400 /* upk.regx contains the opcode */
1401 reg = read_signed_register (24); /* Test register is 24 */
1402 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1403 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1404 /* pc = add_offset_16(pc,upk.offset) ; */
1405 pc += (upk.offset << 1) + 2;
1410 case 29: /* RR Formats JR, JALR, JALR-RA */
1412 struct upk_mips16 upk;
1413 /* upk.fmt = rrtype; */
1418 upk.regx = (insn >> 8) & 0x07;
1419 upk.regy = (insn >> 5) & 0x07;
1427 break; /* Function return instruction */
1433 break; /* BOGUS Guess */
1435 pc = read_signed_register (reg);
1442 /* This is an instruction extension. Fetch the real instruction
1443 (which follows the extension) and decode things based on
1447 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1460 mips16_next_pc (CORE_ADDR pc)
1462 unsigned int insn = fetch_mips_16 (pc);
1463 return extended_mips16_next_pc (pc, 0, insn);
1466 /* The mips_next_pc function supports single_step when the remote
1467 target monitor or stub is not developed enough to do a single_step.
1468 It works by decoding the current instruction and predicting where a
1469 branch will go. This isnt hard because all the data is available.
1470 The MIPS32 and MIPS16 variants are quite different */
1472 mips_next_pc (CORE_ADDR pc)
1475 return mips16_next_pc (pc);
1477 return mips32_next_pc (pc);
1480 struct mips_frame_cache
1483 struct trad_frame_saved_reg *saved_regs;
1487 static struct mips_frame_cache *
1488 mips_mdebug_frame_cache (struct frame_info *next_frame, void **this_cache)
1490 mips_extra_func_info_t proc_desc;
1491 struct mips_frame_cache *cache;
1492 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1493 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1494 /* r0 bit means kernel trap */
1496 /* What registers have been saved? Bitmasks. */
1497 unsigned long gen_mask, float_mask;
1499 if ((*this_cache) != NULL)
1500 return (*this_cache);
1501 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
1502 (*this_cache) = cache;
1503 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1505 /* Get the mdebug proc descriptor. */
1506 proc_desc = find_proc_desc (frame_pc_unwind (next_frame), next_frame, 1);
1507 if (proc_desc == NULL)
1508 /* I'm not sure how/whether this can happen. Normally when we
1509 can't find a proc_desc, we "synthesize" one using
1510 heuristic_proc_desc and set the saved_regs right away. */
1513 /* Extract the frame's base. */
1514 cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc))
1515 + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc));
1517 kernel_trap = PROC_REG_MASK (proc_desc) & 1;
1518 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
1519 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
1521 /* In any frame other than the innermost or a frame interrupted by a
1522 signal, we assume that all registers have been saved. This
1523 assumes that all register saves in a function happen before the
1524 first function call. */
1525 if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc))
1526 /* Not sure exactly what kernel_trap means, but if it means the
1527 kernel saves the registers without a prologue doing it, we
1528 better not examine the prologue to see whether registers
1529 have been saved yet. */
1532 /* We need to figure out whether the registers that the
1533 proc_desc claims are saved have been saved yet. */
1537 /* Bitmasks; set if we have found a save for the register. */
1538 unsigned long gen_save_found = 0;
1539 unsigned long float_save_found = 0;
1542 /* If the address is odd, assume this is MIPS16 code. */
1543 addr = PROC_LOW_ADDR (proc_desc);
1544 mips16 = pc_is_mips16 (addr);
1546 /* Scan through this function's instructions preceding the
1547 current PC, and look for those that save registers. */
1548 while (addr < frame_pc_unwind (next_frame))
1552 mips16_decode_reg_save (mips16_fetch_instruction (addr),
1554 addr += MIPS16_INSTLEN;
1558 mips32_decode_reg_save (mips32_fetch_instruction (addr),
1559 &gen_save_found, &float_save_found);
1560 addr += MIPS_INSTLEN;
1563 gen_mask = gen_save_found;
1564 float_mask = float_save_found;
1567 /* Fill in the offsets for the registers which gen_mask says were
1570 CORE_ADDR reg_position = (cache->base
1571 + PROC_REG_OFFSET (proc_desc));
1573 for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
1574 if (gen_mask & 0x80000000)
1576 cache->saved_regs[NUM_REGS + ireg].addr = reg_position;
1577 reg_position -= mips_saved_regsize (tdep);
1581 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1582 order of that normally used by gcc. Therefore, we have to fetch
1583 the first instruction of the function, and if it's an entry
1584 instruction that saves $s0 or $s1, correct their saved addresses. */
1585 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
1587 ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc));
1588 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700)
1592 int sreg_count = (inst >> 6) & 3;
1594 /* Check if the ra register was pushed on the stack. */
1595 CORE_ADDR reg_position = (cache->base
1596 + PROC_REG_OFFSET (proc_desc));
1598 reg_position -= mips_saved_regsize (tdep);
1600 /* Check if the s0 and s1 registers were pushed on the
1602 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1604 for (reg = 16; reg < sreg_count + 16; reg++)
1606 cache->saved_regs[NUM_REGS + reg].addr = reg_position;
1607 reg_position -= mips_saved_regsize (tdep);
1612 /* Fill in the offsets for the registers which float_mask says were
1615 CORE_ADDR reg_position = (cache->base
1616 + PROC_FREG_OFFSET (proc_desc));
1618 /* Fill in the offsets for the float registers which float_mask
1620 for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
1621 if (float_mask & 0x80000000)
1623 if (mips_saved_regsize (tdep) == 4
1624 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1626 /* On a big endian 32 bit ABI, floating point registers
1627 are paired to form doubles such that the most
1628 significant part is in $f[N+1] and the least
1629 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1630 registers are also spilled as a pair and stored as a
1633 When little-endian the least significant part is
1634 stored first leading to the memory order $f[N] and
1637 Unfortunately, when big-endian the most significant
1638 part of the double is stored first, and the least
1639 significant is stored second. This leads to the
1640 registers being ordered in memory as firt $f[N+1] and
1643 For the big-endian case make certain that the
1644 addresses point at the correct (swapped) locations
1645 $f[N] and $f[N+1] pair (keep in mind that
1646 reg_position is decremented each time through the
1649 cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
1650 .addr = reg_position - mips_saved_regsize (tdep);
1652 cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
1653 .addr = reg_position + mips_saved_regsize (tdep);
1656 cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
1657 .addr = reg_position;
1658 reg_position -= mips_saved_regsize (tdep);
1661 cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc]
1662 = cache->saved_regs[NUM_REGS + RA_REGNUM];
1665 /* SP_REGNUM, contains the value and not the address. */
1666 trad_frame_set_value (cache->saved_regs, NUM_REGS + SP_REGNUM, cache->base);
1668 return (*this_cache);
1672 mips_mdebug_frame_this_id (struct frame_info *next_frame, void **this_cache,
1673 struct frame_id *this_id)
1675 struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame,
1677 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
1681 mips_mdebug_frame_prev_register (struct frame_info *next_frame,
1683 int regnum, int *optimizedp,
1684 enum lval_type *lvalp, CORE_ADDR *addrp,
1685 int *realnump, void *valuep)
1687 struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame,
1689 trad_frame_prev_register (next_frame, info->saved_regs, regnum,
1690 optimizedp, lvalp, addrp, realnump, valuep);
1693 static const struct frame_unwind mips_mdebug_frame_unwind =
1696 mips_mdebug_frame_this_id,
1697 mips_mdebug_frame_prev_register
1700 static const struct frame_unwind *
1701 mips_mdebug_frame_sniffer (struct frame_info *next_frame)
1703 return &mips_mdebug_frame_unwind;
1707 mips_mdebug_frame_base_address (struct frame_info *next_frame,
1710 struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame,
1715 static const struct frame_base mips_mdebug_frame_base = {
1716 &mips_mdebug_frame_unwind,
1717 mips_mdebug_frame_base_address,
1718 mips_mdebug_frame_base_address,
1719 mips_mdebug_frame_base_address
1722 static const struct frame_base *
1723 mips_mdebug_frame_base_sniffer (struct frame_info *next_frame)
1725 return &mips_mdebug_frame_base;
1729 read_next_frame_reg (struct frame_info *fi, int regno)
1731 /* Always a pseudo. */
1732 gdb_assert (regno >= NUM_REGS);
1736 regcache_cooked_read_signed (current_regcache, regno, &val);
1739 else if ((regno % NUM_REGS) == SP_REGNUM)
1740 /* The SP_REGNUM is special, its value is stored in saved_regs.
1741 In fact, it is so special that it can even only be fetched
1742 using a raw register number! Once this code as been converted
1743 to frame-unwind the problem goes away. */
1744 return frame_unwind_register_signed (fi, regno % NUM_REGS);
1746 return frame_unwind_register_signed (fi, regno);
1750 /* mips_addr_bits_remove - remove useless address bits */
1753 mips_addr_bits_remove (CORE_ADDR addr)
1755 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1756 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
1757 /* This hack is a work-around for existing boards using PMON, the
1758 simulator, and any other 64-bit targets that doesn't have true
1759 64-bit addressing. On these targets, the upper 32 bits of
1760 addresses are ignored by the hardware. Thus, the PC or SP are
1761 likely to have been sign extended to all 1s by instruction
1762 sequences that load 32-bit addresses. For example, a typical
1763 piece of code that loads an address is this:
1765 lui $r2, <upper 16 bits>
1766 ori $r2, <lower 16 bits>
1768 But the lui sign-extends the value such that the upper 32 bits
1769 may be all 1s. The workaround is simply to mask off these
1770 bits. In the future, gcc may be changed to support true 64-bit
1771 addressing, and this masking will have to be disabled. */
1772 return addr &= 0xffffffffUL;
1777 /* mips_software_single_step() is called just before we want to resume
1778 the inferior, if we want to single-step it but there is no hardware
1779 or kernel single-step support (MIPS on GNU/Linux for example). We find
1780 the target of the coming instruction and breakpoint it.
1782 single_step is also called just after the inferior stops. If we had
1783 set up a simulated single-step, we undo our damage. */
1786 mips_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1788 static CORE_ADDR next_pc;
1789 typedef char binsn_quantum[BREAKPOINT_MAX];
1790 static binsn_quantum break_mem;
1793 if (insert_breakpoints_p)
1795 pc = read_register (mips_regnum (current_gdbarch)->pc);
1796 next_pc = mips_next_pc (pc);
1798 target_insert_breakpoint (next_pc, break_mem);
1801 target_remove_breakpoint (next_pc, break_mem);
1804 static struct mips_extra_func_info temp_proc_desc;
1806 /* This hack will go away once the get_prev_frame() code has been
1807 modified to set the frame's type first. That is BEFORE init extra
1808 frame info et.al. is called. This is because it will become
1809 possible to skip the init extra info call for sigtramp and dummy
1811 static CORE_ADDR *temp_saved_regs;
1813 /* Set a register's saved stack address in temp_saved_regs. If an
1814 address has already been set for this register, do nothing; this
1815 way we will only recognize the first save of a given register in a
1818 For simplicity, save the address in both [0 .. NUM_REGS) and
1819 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1820 is used as it is only second range (the ABI instead of ISA
1821 registers) that comes into play when finding saved registers in a
1825 set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset)
1827 if (saved_regs[regno] == 0)
1829 saved_regs[regno + 0 * NUM_REGS] = offset;
1830 saved_regs[regno + 1 * NUM_REGS] = offset;
1835 /* Test whether the PC points to the return instruction at the
1836 end of a function. */
1839 mips_about_to_return (CORE_ADDR pc)
1841 if (pc_is_mips16 (pc))
1842 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1843 generates a "jr $ra"; other times it generates code to load
1844 the return address from the stack to an accessible register (such
1845 as $a3), then a "jr" using that register. This second case
1846 is almost impossible to distinguish from an indirect jump
1847 used for switch statements, so we don't even try. */
1848 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
1850 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
1854 /* This fencepost looks highly suspicious to me. Removing it also
1855 seems suspicious as it could affect remote debugging across serial
1859 heuristic_proc_start (CORE_ADDR pc)
1866 pc = ADDR_BITS_REMOVE (pc);
1868 fence = start_pc - heuristic_fence_post;
1872 if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS)
1873 fence = VM_MIN_ADDRESS;
1875 instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1877 /* search back for previous return */
1878 for (start_pc -= instlen;; start_pc -= instlen)
1879 if (start_pc < fence)
1881 /* It's not clear to me why we reach this point when
1882 stop_soon, but with this test, at least we
1883 don't print out warnings for every child forked (eg, on
1884 decstation). 22apr93 rich@cygnus.com. */
1885 if (stop_soon == NO_STOP_QUIETLY)
1887 static int blurb_printed = 0;
1890 ("Warning: GDB can't find the start of the function at 0x%s.",
1895 /* This actually happens frequently in embedded
1896 development, when you first connect to a board
1897 and your stack pointer and pc are nowhere in
1898 particular. This message needs to give people
1899 in that situation enough information to
1900 determine that it's no big deal. */
1901 printf_filtered ("\n\
1902 GDB is unable to find the start of the function at 0x%s\n\
1903 and thus can't determine the size of that function's stack frame.\n\
1904 This means that GDB may be unable to access that stack frame, or\n\
1905 the frames below it.\n\
1906 This problem is most likely caused by an invalid program counter or\n\
1908 However, if you think GDB should simply search farther back\n\
1909 from 0x%s for code which looks like the beginning of a\n\
1910 function, you can increase the range of the search using the `set\n\
1911 heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc));
1918 else if (pc_is_mips16 (start_pc))
1920 unsigned short inst;
1922 /* On MIPS16, any one of the following is likely to be the
1923 start of a function:
1927 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1928 inst = mips_fetch_instruction (start_pc);
1929 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1930 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
1931 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
1932 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
1934 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
1935 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1940 else if (mips_about_to_return (start_pc))
1942 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
1949 /* Fetch the immediate value from a MIPS16 instruction.
1950 If the previous instruction was an EXTEND, use it to extend
1951 the upper bits of the immediate value. This is a helper function
1952 for mips16_heuristic_proc_desc. */
1955 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1956 unsigned short inst, /* current instruction */
1957 int nbits, /* number of bits in imm field */
1958 int scale, /* scale factor to be applied to imm */
1959 int is_signed) /* is the imm field signed? */
1963 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1965 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1966 if (offset & 0x8000) /* check for negative extend */
1967 offset = 0 - (0x10000 - (offset & 0xffff));
1968 return offset | (inst & 0x1f);
1972 int max_imm = 1 << nbits;
1973 int mask = max_imm - 1;
1974 int sign_bit = max_imm >> 1;
1976 offset = inst & mask;
1977 if (is_signed && (offset & sign_bit))
1978 offset = 0 - (max_imm - offset);
1979 return offset * scale;
1984 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1985 stream from start_pc to limit_pc. */
1988 mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1989 struct frame_info *next_frame, CORE_ADDR sp)
1992 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1993 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1994 unsigned inst = 0; /* current instruction */
1995 unsigned entry_inst = 0; /* the entry instruction */
1997 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1999 PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
2000 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
2002 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
2004 /* Save the previous instruction. If it's an EXTEND, we'll extract
2005 the immediate offset extension from it in mips16_get_imm. */
2008 /* Fetch and decode the instruction. */
2009 inst = (unsigned short) mips_fetch_instruction (cur_pc);
2010 if ((inst & 0xff00) == 0x6300 /* addiu sp */
2011 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2013 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
2014 if (offset < 0) /* negative stack adjustment? */
2015 PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
2017 /* Exit loop if a positive stack adjustment is found, which
2018 usually means that the stack cleanup code in the function
2019 epilogue is reached. */
2022 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
2024 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2025 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
2026 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
2027 set_reg_offset (temp_saved_regs, reg, sp + offset);
2029 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
2031 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2032 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
2033 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
2034 set_reg_offset (temp_saved_regs, reg, sp + offset);
2036 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
2038 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2039 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
2040 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
2042 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2044 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
2045 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
2046 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
2048 else if (inst == 0x673d) /* move $s1, $sp */
2051 PROC_FRAME_REG (&temp_proc_desc) = 17;
2053 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
2055 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2056 frame_addr = sp + offset;
2057 PROC_FRAME_REG (&temp_proc_desc) = 17;
2058 PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
2060 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2062 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
2063 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
2064 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2065 set_reg_offset (temp_saved_regs, reg, frame_addr + offset);
2067 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2069 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2070 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
2071 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2072 set_reg_offset (temp_saved_regs, reg, frame_addr + offset);
2074 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
2075 entry_inst = inst; /* save for later processing */
2076 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
2077 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
2080 /* The entry instruction is typically the first instruction in a function,
2081 and it stores registers at offsets relative to the value of the old SP
2082 (before the prologue). But the value of the sp parameter to this
2083 function is the new SP (after the prologue has been executed). So we
2084 can't calculate those offsets until we've seen the entire prologue,
2085 and can calculate what the old SP must have been. */
2086 if (entry_inst != 0)
2088 int areg_count = (entry_inst >> 8) & 7;
2089 int sreg_count = (entry_inst >> 6) & 3;
2091 /* The entry instruction always subtracts 32 from the SP. */
2092 PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
2094 /* Now we can calculate what the SP must have been at the
2095 start of the function prologue. */
2096 sp += PROC_FRAME_OFFSET (&temp_proc_desc);
2098 /* Check if a0-a3 were saved in the caller's argument save area. */
2099 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
2101 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2102 set_reg_offset (temp_saved_regs, reg, sp + offset);
2103 offset += mips_saved_regsize (tdep);
2106 /* Check if the ra register was pushed on the stack. */
2108 if (entry_inst & 0x20)
2110 PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
2111 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
2112 offset -= mips_saved_regsize (tdep);
2115 /* Check if the s0 and s1 registers were pushed on the stack. */
2116 for (reg = 16; reg < sreg_count + 16; reg++)
2118 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2119 set_reg_offset (temp_saved_regs, reg, sp + offset);
2120 offset -= mips_saved_regsize (tdep);
2126 mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2127 struct frame_info *next_frame, CORE_ADDR sp)
2130 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
2132 temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2133 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2134 PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
2135 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
2136 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
2138 unsigned long inst, high_word, low_word;
2141 /* Fetch the instruction. */
2142 inst = (unsigned long) mips_fetch_instruction (cur_pc);
2144 /* Save some code by pre-extracting some useful fields. */
2145 high_word = (inst >> 16) & 0xffff;
2146 low_word = inst & 0xffff;
2147 reg = high_word & 0x1f;
2149 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
2150 || high_word == 0x23bd /* addi $sp,$sp,-i */
2151 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
2153 if (low_word & 0x8000) /* negative stack adjustment? */
2154 PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
2156 /* Exit loop if a positive stack adjustment is found, which
2157 usually means that the stack cleanup code in the function
2158 epilogue is reached. */
2161 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2163 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2164 set_reg_offset (temp_saved_regs, reg, sp + low_word);
2166 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2168 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2169 but the register size used is only 32 bits. Make the address
2170 for the saved register point to the lower 32 bits. */
2171 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2172 set_reg_offset (temp_saved_regs, reg,
2173 sp + low_word + 8 - mips_regsize (current_gdbarch));
2175 else if (high_word == 0x27be) /* addiu $30,$sp,size */
2177 /* Old gcc frame, r30 is virtual frame pointer. */
2178 if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
2179 frame_addr = sp + low_word;
2180 else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2182 unsigned alloca_adjust;
2183 PROC_FRAME_REG (&temp_proc_desc) = 30;
2184 frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
2185 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
2186 if (alloca_adjust > 0)
2188 /* FP > SP + frame_size. This may be because
2189 * of an alloca or somethings similar.
2190 * Fix sp to "pre-alloca" value, and try again.
2192 sp += alloca_adjust;
2197 /* move $30,$sp. With different versions of gas this will be either
2198 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2199 Accept any one of these. */
2200 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
2202 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2203 if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2205 unsigned alloca_adjust;
2206 PROC_FRAME_REG (&temp_proc_desc) = 30;
2207 frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
2208 alloca_adjust = (unsigned) (frame_addr - sp);
2209 if (alloca_adjust > 0)
2211 /* FP > SP + frame_size. This may be because
2212 * of an alloca or somethings similar.
2213 * Fix sp to "pre-alloca" value, and try again.
2215 sp += alloca_adjust;
2220 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2222 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2223 set_reg_offset (temp_saved_regs, reg, frame_addr + low_word);
2228 static mips_extra_func_info_t
2229 heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2230 struct frame_info *next_frame, int cur_frame)
2235 sp = read_next_frame_reg (next_frame, NUM_REGS + SP_REGNUM);
2241 memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc));
2242 temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2243 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2244 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
2245 PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM;
2246 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
2248 if (start_pc + 200 < limit_pc)
2249 limit_pc = start_pc + 200;
2250 if (pc_is_mips16 (start_pc))
2251 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2253 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2254 return &temp_proc_desc;
2257 struct mips_objfile_private
2263 /* Global used to communicate between non_heuristic_proc_desc and
2264 compare_pdr_entries within qsort (). */
2265 static bfd *the_bfd;
2268 compare_pdr_entries (const void *a, const void *b)
2270 CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a);
2271 CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b);
2275 else if (lhs == rhs)
2281 static mips_extra_func_info_t
2282 non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
2284 CORE_ADDR startaddr;
2285 mips_extra_func_info_t proc_desc;
2286 struct block *b = block_for_pc (pc);
2288 struct obj_section *sec;
2289 struct mips_objfile_private *priv;
2291 if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0))
2294 find_pc_partial_function (pc, NULL, &startaddr, NULL);
2296 *addrptr = startaddr;
2300 sec = find_pc_section (pc);
2303 priv = (struct mips_objfile_private *) objfile_data (sec->objfile, mips_pdr_data);
2305 /* Search the ".pdr" section generated by GAS. This includes most of
2306 the information normally found in ECOFF PDRs. */
2308 the_bfd = sec->objfile->obfd;
2310 && (the_bfd->format == bfd_object
2311 && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour
2312 && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64))
2314 /* Right now GAS only outputs the address as a four-byte sequence.
2315 This means that we should not bother with this method on 64-bit
2316 targets (until that is fixed). */
2318 priv = obstack_alloc (&sec->objfile->objfile_obstack,
2319 sizeof (struct mips_objfile_private));
2321 set_objfile_data (sec->objfile, mips_pdr_data, priv);
2323 else if (priv == NULL)
2327 priv = obstack_alloc (&sec->objfile->objfile_obstack,
2328 sizeof (struct mips_objfile_private));
2330 bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr");
2333 priv->size = bfd_section_size (sec->objfile->obfd, bfdsec);
2334 priv->contents = obstack_alloc (&sec->objfile->objfile_obstack,
2336 bfd_get_section_contents (sec->objfile->obfd, bfdsec,
2337 priv->contents, 0, priv->size);
2339 /* In general, the .pdr section is sorted. However, in the
2340 presence of multiple code sections (and other corner cases)
2341 it can become unsorted. Sort it so that we can use a faster
2343 qsort (priv->contents, priv->size / 32, 32,
2344 compare_pdr_entries);
2349 set_objfile_data (sec->objfile, mips_pdr_data, priv);
2353 if (priv->size != 0)
2359 high = priv->size / 32;
2365 mid = (low + high) / 2;
2367 ptr = priv->contents + mid * 32;
2368 pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr);
2369 pdr_pc += ANOFFSET (sec->objfile->section_offsets,
2370 SECT_OFF_TEXT (sec->objfile));
2371 if (pdr_pc == startaddr)
2373 if (pdr_pc > startaddr)
2378 while (low != high);
2382 struct symbol *sym = find_pc_function (pc);
2384 /* Fill in what we need of the proc_desc. */
2385 proc_desc = (mips_extra_func_info_t)
2386 obstack_alloc (&sec->objfile->objfile_obstack,
2387 sizeof (struct mips_extra_func_info));
2388 PROC_LOW_ADDR (proc_desc) = startaddr;
2390 /* Only used for dummy frames. */
2391 PROC_HIGH_ADDR (proc_desc) = 0;
2393 PROC_FRAME_OFFSET (proc_desc)
2394 = bfd_get_32 (sec->objfile->obfd, ptr + 20);
2395 PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2397 PROC_FRAME_ADJUST (proc_desc) = 0;
2398 PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2400 PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2402 PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2404 PROC_FREG_OFFSET (proc_desc)
2405 = bfd_get_32 (sec->objfile->obfd, ptr + 16);
2406 PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2408 proc_desc->pdr.isym = (long) sym;
2418 if (startaddr > BLOCK_START (b))
2420 /* This is the "pathological" case referred to in a comment in
2421 print_frame_info. It might be better to move this check into
2426 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL);
2428 /* If we never found a PDR for this function in symbol reading, then
2429 examine prologues to find the information. */
2432 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
2433 if (PROC_FRAME_REG (proc_desc) == -1)
2443 static mips_extra_func_info_t
2444 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame)
2446 mips_extra_func_info_t proc_desc;
2447 CORE_ADDR startaddr = 0;
2449 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
2453 /* IF this is the topmost frame AND
2454 * (this proc does not have debugging information OR
2455 * the PC is in the procedure prologue)
2456 * THEN create a "heuristic" proc_desc (by analyzing
2457 * the actual code) to replace the "official" proc_desc.
2459 if (next_frame == NULL)
2461 struct symtab_and_line val;
2462 struct symbol *proc_symbol =
2463 PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc);
2467 val = find_pc_line (BLOCK_START
2468 (SYMBOL_BLOCK_VALUE (proc_symbol)), 0);
2469 val.pc = val.end ? val.end : pc;
2471 if (!proc_symbol || pc < val.pc)
2473 mips_extra_func_info_t found_heuristic =
2474 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
2475 pc, next_frame, cur_frame);
2476 if (found_heuristic)
2477 proc_desc = found_heuristic;
2483 /* Is linked_proc_desc_table really necessary? It only seems to be used
2484 by procedure call dummys. However, the procedures being called ought
2485 to have their own proc_descs, and even if they don't,
2486 heuristic_proc_desc knows how to create them! */
2488 struct linked_proc_info *link;
2490 for (link = linked_proc_desc_table; link; link = link->next)
2491 if (PROC_LOW_ADDR (&link->info) <= pc
2492 && PROC_HIGH_ADDR (&link->info) > pc)
2496 startaddr = heuristic_proc_start (pc);
2498 proc_desc = heuristic_proc_desc (startaddr, pc, next_frame, cur_frame);
2503 /* MIPS stack frames are almost impenetrable. When execution stops,
2504 we basically have to look at symbol information for the function
2505 that we stopped in, which tells us *which* register (if any) is
2506 the base of the frame pointer, and what offset from that register
2507 the frame itself is at.
2509 This presents a problem when trying to examine a stack in memory
2510 (that isn't executing at the moment), using the "frame" command. We
2511 don't have a PC, nor do we have any registers except SP.
2513 This routine takes two arguments, SP and PC, and tries to make the
2514 cached frames look as if these two arguments defined a frame on the
2515 cache. This allows the rest of info frame to extract the important
2516 arguments without difficulty. */
2519 setup_arbitrary_frame (int argc, CORE_ADDR *argv)
2522 error ("MIPS frame specifications require two arguments: sp and pc");
2524 return create_new_frame (argv[0], argv[1]);
2527 /* According to the current ABI, should the type be passed in a
2528 floating-point register (assuming that there is space)? When there
2529 is no FPU, FP are not even considered as possibile candidates for
2530 FP registers and, consequently this returns false - forces FP
2531 arguments into integer registers. */
2534 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2536 return ((typecode == TYPE_CODE_FLT
2538 && (typecode == TYPE_CODE_STRUCT
2539 || typecode == TYPE_CODE_UNION)
2540 && TYPE_NFIELDS (arg_type) == 1
2541 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
2542 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2545 /* On o32, argument passing in GPRs depends on the alignment of the type being
2546 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2549 mips_type_needs_double_align (struct type *type)
2551 enum type_code typecode = TYPE_CODE (type);
2553 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2555 else if (typecode == TYPE_CODE_STRUCT)
2557 if (TYPE_NFIELDS (type) < 1)
2559 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2561 else if (typecode == TYPE_CODE_UNION)
2565 n = TYPE_NFIELDS (type);
2566 for (i = 0; i < n; i++)
2567 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2574 /* Adjust the address downward (direction of stack growth) so that it
2575 is correctly aligned for a new stack frame. */
2577 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2579 return align_down (addr, 16);
2582 /* Determine how a return value is stored within the MIPS register
2583 file, given the return type `valtype'. */
2585 struct return_value_word
2594 return_value_location (struct type *valtype,
2595 struct return_value_word *hi,
2596 struct return_value_word *lo)
2598 int len = TYPE_LENGTH (valtype);
2599 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2601 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
2602 && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
2603 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
2605 if (!FP_REGISTER_DOUBLE && len == 8)
2607 /* We need to break a 64bit float in two 32 bit halves and
2608 spread them across a floating-point register pair. */
2609 lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2610 hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4;
2611 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2612 && register_size (current_gdbarch,
2613 mips_regnum (current_gdbarch)->
2614 fp0) == 8) ? 4 : 0);
2615 hi->reg_offset = lo->reg_offset;
2616 lo->reg = mips_regnum (current_gdbarch)->fp0 + 0;
2617 hi->reg = mips_regnum (current_gdbarch)->fp0 + 1;
2623 /* The floating point value fits in a single floating-point
2625 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2626 && register_size (current_gdbarch,
2627 mips_regnum (current_gdbarch)->
2629 && len == 4) ? 4 : 0);
2630 lo->reg = mips_regnum (current_gdbarch)->fp0;
2641 /* Locate a result possibly spread across two registers. */
2643 lo->reg = regnum + 0;
2644 hi->reg = regnum + 1;
2645 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2646 && len < mips_saved_regsize (tdep))
2648 /* "un-left-justify" the value in the low register */
2649 lo->reg_offset = mips_saved_regsize (tdep) - len;
2654 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG && len > mips_saved_regsize (tdep) /* odd-size structs */
2655 && len < mips_saved_regsize (tdep) * 2
2656 && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
2657 TYPE_CODE (valtype) == TYPE_CODE_UNION))
2659 /* "un-left-justify" the value spread across two registers. */
2660 lo->reg_offset = 2 * mips_saved_regsize (tdep) - len;
2661 lo->len = mips_saved_regsize (tdep) - lo->reg_offset;
2663 hi->len = len - lo->len;
2667 /* Only perform a partial copy of the second register. */
2670 if (len > mips_saved_regsize (tdep))
2672 lo->len = mips_saved_regsize (tdep);
2673 hi->len = len - mips_saved_regsize (tdep);
2681 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2682 && register_size (current_gdbarch, regnum) == 8
2683 && mips_saved_regsize (tdep) == 4)
2685 /* Account for the fact that only the least-signficant part
2686 of the register is being used */
2687 lo->reg_offset += 4;
2688 hi->reg_offset += 4;
2691 hi->buf_offset = lo->len;
2695 /* Should call_function allocate stack space for a struct return? */
2698 mips_eabi_use_struct_convention (int gcc_p, struct type *type)
2700 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2701 return (TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep));
2704 /* Should call_function pass struct by reference?
2705 For each architecture, structs are passed either by
2706 value or by reference, depending on their size. */
2709 mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type)
2711 enum type_code typecode = TYPE_CODE (check_typedef (type));
2712 int len = TYPE_LENGTH (check_typedef (type));
2713 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2715 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
2716 return (len > mips_saved_regsize (tdep));
2722 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
2723 struct regcache *regcache, CORE_ADDR bp_addr,
2724 int nargs, struct value **args, CORE_ADDR sp,
2725 int struct_return, CORE_ADDR struct_addr)
2731 int stack_offset = 0;
2732 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2734 /* For shared libraries, "t9" needs to point at the function
2736 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
2738 /* Set the return address register to point to the entry point of
2739 the program, where a breakpoint lies in wait. */
2740 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
2742 /* First ensure that the stack and structure return address (if any)
2743 are properly aligned. The stack has to be at least 64-bit
2744 aligned even on 32-bit machines, because doubles must be 64-bit
2745 aligned. For n32 and n64, stack frames need to be 128-bit
2746 aligned, so we round to this widest known alignment. */
2748 sp = align_down (sp, 16);
2749 struct_addr = align_down (struct_addr, 16);
2751 /* Now make space on the stack for the args. We allocate more
2752 than necessary for EABI, because the first few arguments are
2753 passed in registers, but that's OK. */
2754 for (argnum = 0; argnum < nargs; argnum++)
2755 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
2756 mips_stack_argsize (tdep));
2757 sp -= align_up (len, 16);
2760 fprintf_unfiltered (gdb_stdlog,
2761 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2762 paddr_nz (sp), (long) align_up (len, 16));
2764 /* Initialize the integer and float register pointers. */
2766 float_argreg = mips_fpa0_regnum (current_gdbarch);
2768 /* The struct_return pointer occupies the first parameter-passing reg. */
2772 fprintf_unfiltered (gdb_stdlog,
2773 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2774 argreg, paddr_nz (struct_addr));
2775 write_register (argreg++, struct_addr);
2778 /* Now load as many as possible of the first arguments into
2779 registers, and push the rest onto the stack. Loop thru args
2780 from first to last. */
2781 for (argnum = 0; argnum < nargs; argnum++)
2784 char valbuf[MAX_REGISTER_SIZE];
2785 struct value *arg = args[argnum];
2786 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2787 int len = TYPE_LENGTH (arg_type);
2788 enum type_code typecode = TYPE_CODE (arg_type);
2791 fprintf_unfiltered (gdb_stdlog,
2792 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2793 argnum + 1, len, (int) typecode);
2795 /* The EABI passes structures that do not fit in a register by
2797 if (len > mips_saved_regsize (tdep)
2798 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2800 store_unsigned_integer (valbuf, mips_saved_regsize (tdep),
2801 VALUE_ADDRESS (arg));
2802 typecode = TYPE_CODE_PTR;
2803 len = mips_saved_regsize (tdep);
2806 fprintf_unfiltered (gdb_stdlog, " push");
2809 val = (char *) VALUE_CONTENTS (arg);
2811 /* 32-bit ABIs always start floating point arguments in an
2812 even-numbered floating point register. Round the FP register
2813 up before the check to see if there are any FP registers
2814 left. Non MIPS_EABI targets also pass the FP in the integer
2815 registers so also round up normal registers. */
2816 if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type))
2818 if ((float_argreg & 1))
2822 /* Floating point arguments passed in registers have to be
2823 treated specially. On 32-bit architectures, doubles
2824 are passed in register pairs; the even register gets
2825 the low word, and the odd register gets the high word.
2826 On non-EABI processors, the first two floating point arguments are
2827 also copied to general registers, because MIPS16 functions
2828 don't use float registers for arguments. This duplication of
2829 arguments in general registers can't hurt non-MIPS16 functions
2830 because those registers are normally skipped. */
2831 /* MIPS_EABI squeezes a struct that contains a single floating
2832 point value into an FP register instead of pushing it onto the
2834 if (fp_register_arg_p (typecode, arg_type)
2835 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2837 if (!FP_REGISTER_DOUBLE && len == 8)
2839 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2840 unsigned long regval;
2842 /* Write the low word of the double to the even register(s). */
2843 regval = extract_unsigned_integer (val + low_offset, 4);
2845 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2846 float_argreg, phex (regval, 4));
2847 write_register (float_argreg++, regval);
2849 /* Write the high word of the double to the odd register(s). */
2850 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2852 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2853 float_argreg, phex (regval, 4));
2854 write_register (float_argreg++, regval);
2858 /* This is a floating point value that fits entirely
2859 in a single register. */
2860 /* On 32 bit ABI's the float_argreg is further adjusted
2861 above to ensure that it is even register aligned. */
2862 LONGEST regval = extract_unsigned_integer (val, len);
2864 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2865 float_argreg, phex (regval, len));
2866 write_register (float_argreg++, regval);
2871 /* Copy the argument to general registers or the stack in
2872 register-sized pieces. Large arguments are split between
2873 registers and stack. */
2874 /* Note: structs whose size is not a multiple of
2875 mips_regsize() are treated specially: Irix cc passes them
2876 in registers where gcc sometimes puts them on the stack.
2877 For maximum compatibility, we will put them in both
2879 int odd_sized_struct = ((len > mips_saved_regsize (tdep))
2880 && (len % mips_saved_regsize (tdep) != 0));
2882 /* Note: Floating-point values that didn't fit into an FP
2883 register are only written to memory. */
2886 /* Remember if the argument was written to the stack. */
2887 int stack_used_p = 0;
2888 int partial_len = (len < mips_saved_regsize (tdep)
2889 ? len : mips_saved_regsize (tdep));
2892 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2895 /* Write this portion of the argument to the stack. */
2896 if (argreg > MIPS_LAST_ARG_REGNUM
2898 || fp_register_arg_p (typecode, arg_type))
2900 /* Should shorter than int integer values be
2901 promoted to int before being stored? */
2902 int longword_offset = 0;
2905 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2907 if (mips_stack_argsize (tdep) == 8
2908 && (typecode == TYPE_CODE_INT
2909 || typecode == TYPE_CODE_PTR
2910 || typecode == TYPE_CODE_FLT) && len <= 4)
2911 longword_offset = mips_stack_argsize (tdep) - len;
2912 else if ((typecode == TYPE_CODE_STRUCT
2913 || typecode == TYPE_CODE_UNION)
2914 && (TYPE_LENGTH (arg_type)
2915 < mips_stack_argsize (tdep)))
2916 longword_offset = mips_stack_argsize (tdep) - len;
2921 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2922 paddr_nz (stack_offset));
2923 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2924 paddr_nz (longword_offset));
2927 addr = sp + stack_offset + longword_offset;
2932 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2934 for (i = 0; i < partial_len; i++)
2936 fprintf_unfiltered (gdb_stdlog, "%02x",
2940 write_memory (addr, val, partial_len);
2943 /* Note!!! This is NOT an else clause. Odd sized
2944 structs may go thru BOTH paths. Floating point
2945 arguments will not. */
2946 /* Write this portion of the argument to a general
2947 purpose register. */
2948 if (argreg <= MIPS_LAST_ARG_REGNUM
2949 && !fp_register_arg_p (typecode, arg_type))
2952 extract_unsigned_integer (val, partial_len);
2955 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2958 mips_saved_regsize (tdep)));
2959 write_register (argreg, regval);
2966 /* Compute the the offset into the stack at which we
2967 will copy the next parameter.
2969 In the new EABI (and the NABI32), the stack_offset
2970 only needs to be adjusted when it has been used. */
2973 stack_offset += align_up (partial_len,
2974 mips_stack_argsize (tdep));
2978 fprintf_unfiltered (gdb_stdlog, "\n");
2981 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
2983 /* Return adjusted stack pointer. */
2987 /* Given a return value in `regbuf' with a type `valtype', extract and
2988 copy its value into `valbuf'. */
2991 mips_eabi_extract_return_value (struct type *valtype,
2992 char regbuf[], char *valbuf)
2994 struct return_value_word lo;
2995 struct return_value_word hi;
2996 return_value_location (valtype, &hi, &lo);
2998 memcpy (valbuf + lo.buf_offset,
2999 regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) +
3000 lo.reg_offset, lo.len);
3003 memcpy (valbuf + hi.buf_offset,
3004 regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) +
3005 hi.reg_offset, hi.len);
3008 /* Given a return value in `valbuf' with a type `valtype', write it's
3009 value into the appropriate register. */
3012 mips_eabi_store_return_value (struct type *valtype, char *valbuf)
3014 char raw_buffer[MAX_REGISTER_SIZE];
3015 struct return_value_word lo;
3016 struct return_value_word hi;
3017 return_value_location (valtype, &hi, &lo);
3019 memset (raw_buffer, 0, sizeof (raw_buffer));
3020 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
3021 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg),
3022 raw_buffer, register_size (current_gdbarch,
3027 memset (raw_buffer, 0, sizeof (raw_buffer));
3028 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
3029 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg),
3031 register_size (current_gdbarch,
3036 /* N32/N64 ABI stuff. */
3039 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
3040 struct regcache *regcache, CORE_ADDR bp_addr,
3041 int nargs, struct value **args, CORE_ADDR sp,
3042 int struct_return, CORE_ADDR struct_addr)
3048 int stack_offset = 0;
3049 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3051 /* For shared libraries, "t9" needs to point at the function
3053 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3055 /* Set the return address register to point to the entry point of
3056 the program, where a breakpoint lies in wait. */
3057 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3059 /* First ensure that the stack and structure return address (if any)
3060 are properly aligned. The stack has to be at least 64-bit
3061 aligned even on 32-bit machines, because doubles must be 64-bit
3062 aligned. For n32 and n64, stack frames need to be 128-bit
3063 aligned, so we round to this widest known alignment. */
3065 sp = align_down (sp, 16);
3066 struct_addr = align_down (struct_addr, 16);
3068 /* Now make space on the stack for the args. */
3069 for (argnum = 0; argnum < nargs; argnum++)
3070 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3071 mips_stack_argsize (tdep));
3072 sp -= align_up (len, 16);
3075 fprintf_unfiltered (gdb_stdlog,
3076 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3077 paddr_nz (sp), (long) align_up (len, 16));
3079 /* Initialize the integer and float register pointers. */
3081 float_argreg = mips_fpa0_regnum (current_gdbarch);
3083 /* The struct_return pointer occupies the first parameter-passing reg. */
3087 fprintf_unfiltered (gdb_stdlog,
3088 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3089 argreg, paddr_nz (struct_addr));
3090 write_register (argreg++, struct_addr);
3093 /* Now load as many as possible of the first arguments into
3094 registers, and push the rest onto the stack. Loop thru args
3095 from first to last. */
3096 for (argnum = 0; argnum < nargs; argnum++)
3099 struct value *arg = args[argnum];
3100 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3101 int len = TYPE_LENGTH (arg_type);
3102 enum type_code typecode = TYPE_CODE (arg_type);
3105 fprintf_unfiltered (gdb_stdlog,
3106 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3107 argnum + 1, len, (int) typecode);
3109 val = (char *) VALUE_CONTENTS (arg);
3111 if (fp_register_arg_p (typecode, arg_type)
3112 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3114 /* This is a floating point value that fits entirely
3115 in a single register. */
3116 /* On 32 bit ABI's the float_argreg is further adjusted
3117 above to ensure that it is even register aligned. */
3118 LONGEST regval = extract_unsigned_integer (val, len);
3120 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3121 float_argreg, phex (regval, len));
3122 write_register (float_argreg++, regval);
3125 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3126 argreg, phex (regval, len));
3127 write_register (argreg, regval);
3132 /* Copy the argument to general registers or the stack in
3133 register-sized pieces. Large arguments are split between
3134 registers and stack. */
3135 /* Note: structs whose size is not a multiple of
3136 mips_regsize() are treated specially: Irix cc passes them
3137 in registers where gcc sometimes puts them on the stack.
3138 For maximum compatibility, we will put them in both
3140 int odd_sized_struct = ((len > mips_saved_regsize (tdep))
3141 && (len % mips_saved_regsize (tdep) != 0));
3142 /* Note: Floating-point values that didn't fit into an FP
3143 register are only written to memory. */
3146 /* Rememer if the argument was written to the stack. */
3147 int stack_used_p = 0;
3148 int partial_len = (len < mips_saved_regsize (tdep)
3149 ? len : mips_saved_regsize (tdep));
3152 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3155 /* Write this portion of the argument to the stack. */
3156 if (argreg > MIPS_LAST_ARG_REGNUM
3158 || fp_register_arg_p (typecode, arg_type))
3160 /* Should shorter than int integer values be
3161 promoted to int before being stored? */
3162 int longword_offset = 0;
3165 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3167 if (mips_stack_argsize (tdep) == 8
3168 && (typecode == TYPE_CODE_INT
3169 || typecode == TYPE_CODE_PTR
3170 || typecode == TYPE_CODE_FLT) && len <= 4)
3171 longword_offset = mips_stack_argsize (tdep) - len;
3176 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3177 paddr_nz (stack_offset));
3178 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3179 paddr_nz (longword_offset));
3182 addr = sp + stack_offset + longword_offset;
3187 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3189 for (i = 0; i < partial_len; i++)
3191 fprintf_unfiltered (gdb_stdlog, "%02x",
3195 write_memory (addr, val, partial_len);
3198 /* Note!!! This is NOT an else clause. Odd sized
3199 structs may go thru BOTH paths. Floating point
3200 arguments will not. */
3201 /* Write this portion of the argument to a general
3202 purpose register. */
3203 if (argreg <= MIPS_LAST_ARG_REGNUM
3204 && !fp_register_arg_p (typecode, arg_type))
3207 extract_unsigned_integer (val, partial_len);
3209 /* A non-floating-point argument being passed in a
3210 general register. If a struct or union, and if
3211 the remaining length is smaller than the register
3212 size, we have to adjust the register value on
3215 It does not seem to be necessary to do the
3216 same for integral types.
3218 cagney/2001-07-23: gdb/179: Also, GCC, when
3219 outputting LE O32 with sizeof (struct) <
3220 mips_saved_regsize(), generates a left shift as
3221 part of storing the argument in a register a
3222 register (the left shift isn't generated when
3223 sizeof (struct) >= mips_saved_regsize()). Since
3224 it is quite possible that this is GCC
3225 contradicting the LE/O32 ABI, GDB has not been
3226 adjusted to accommodate this. Either someone
3227 needs to demonstrate that the LE/O32 ABI
3228 specifies such a left shift OR this new ABI gets
3229 identified as such and GDB gets tweaked
3232 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3233 && partial_len < mips_saved_regsize (tdep)
3234 && (typecode == TYPE_CODE_STRUCT ||
3235 typecode == TYPE_CODE_UNION))
3236 regval <<= ((mips_saved_regsize (tdep) - partial_len) *
3240 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3243 mips_saved_regsize (tdep)));
3244 write_register (argreg, regval);
3251 /* Compute the the offset into the stack at which we
3252 will copy the next parameter.
3254 In N32 (N64?), the stack_offset only needs to be
3255 adjusted when it has been used. */
3258 stack_offset += align_up (partial_len,
3259 mips_stack_argsize (tdep));
3263 fprintf_unfiltered (gdb_stdlog, "\n");
3266 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
3268 /* Return adjusted stack pointer. */
3272 static enum return_value_convention
3273 mips_n32n64_return_value (struct gdbarch *gdbarch,
3274 struct type *type, struct regcache *regcache,
3275 void *readbuf, const void *writebuf)
3277 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3278 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3279 || TYPE_CODE (type) == TYPE_CODE_UNION
3280 || TYPE_CODE (type) == TYPE_CODE_ARRAY
3281 || TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep))
3282 return RETURN_VALUE_STRUCT_CONVENTION;
3283 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3284 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3286 /* A floating-point value belongs in the least significant part
3289 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3290 mips_xfer_register (regcache,
3291 NUM_REGS + mips_regnum (current_gdbarch)->fp0,
3293 TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3294 return RETURN_VALUE_REGISTER_CONVENTION;
3296 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3297 && TYPE_NFIELDS (type) <= 2
3298 && TYPE_NFIELDS (type) >= 1
3299 && ((TYPE_NFIELDS (type) == 1
3300 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3302 || (TYPE_NFIELDS (type) == 2
3303 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3305 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
3307 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3309 /* A struct that contains one or two floats. Each value is part
3310 in the least significant part of their floating point
3314 for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
3315 field < TYPE_NFIELDS (type); field++, regnum += 2)
3317 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3320 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3322 mips_xfer_register (regcache, NUM_REGS + regnum,
3323 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3324 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3326 return RETURN_VALUE_REGISTER_CONVENTION;
3328 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3329 || TYPE_CODE (type) == TYPE_CODE_UNION)
3331 /* A structure or union. Extract the left justified value,
3332 regardless of the byte order. I.e. DO NOT USE
3336 for (offset = 0, regnum = V0_REGNUM;
3337 offset < TYPE_LENGTH (type);
3338 offset += register_size (current_gdbarch, regnum), regnum++)
3340 int xfer = register_size (current_gdbarch, regnum);
3341 if (offset + xfer > TYPE_LENGTH (type))
3342 xfer = TYPE_LENGTH (type) - offset;
3344 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3345 offset, xfer, regnum);
3346 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3347 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
3349 return RETURN_VALUE_REGISTER_CONVENTION;
3353 /* A scalar extract each part but least-significant-byte
3357 for (offset = 0, regnum = V0_REGNUM;
3358 offset < TYPE_LENGTH (type);
3359 offset += register_size (current_gdbarch, regnum), regnum++)
3361 int xfer = register_size (current_gdbarch, regnum);
3362 if (offset + xfer > TYPE_LENGTH (type))
3363 xfer = TYPE_LENGTH (type) - offset;
3365 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3366 offset, xfer, regnum);
3367 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3368 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3370 return RETURN_VALUE_REGISTER_CONVENTION;
3374 /* O32 ABI stuff. */
3377 mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
3378 struct regcache *regcache, CORE_ADDR bp_addr,
3379 int nargs, struct value **args, CORE_ADDR sp,
3380 int struct_return, CORE_ADDR struct_addr)
3386 int stack_offset = 0;
3387 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3389 /* For shared libraries, "t9" needs to point at the function
3391 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3393 /* Set the return address register to point to the entry point of
3394 the program, where a breakpoint lies in wait. */
3395 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3397 /* First ensure that the stack and structure return address (if any)
3398 are properly aligned. The stack has to be at least 64-bit
3399 aligned even on 32-bit machines, because doubles must be 64-bit
3400 aligned. For n32 and n64, stack frames need to be 128-bit
3401 aligned, so we round to this widest known alignment. */
3403 sp = align_down (sp, 16);
3404 struct_addr = align_down (struct_addr, 16);
3406 /* Now make space on the stack for the args. */
3407 for (argnum = 0; argnum < nargs; argnum++)
3408 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3409 mips_stack_argsize (tdep));
3410 sp -= align_up (len, 16);
3413 fprintf_unfiltered (gdb_stdlog,
3414 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3415 paddr_nz (sp), (long) align_up (len, 16));
3417 /* Initialize the integer and float register pointers. */
3419 float_argreg = mips_fpa0_regnum (current_gdbarch);
3421 /* The struct_return pointer occupies the first parameter-passing reg. */
3425 fprintf_unfiltered (gdb_stdlog,
3426 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3427 argreg, paddr_nz (struct_addr));
3428 write_register (argreg++, struct_addr);
3429 stack_offset += mips_stack_argsize (tdep);
3432 /* Now load as many as possible of the first arguments into
3433 registers, and push the rest onto the stack. Loop thru args
3434 from first to last. */
3435 for (argnum = 0; argnum < nargs; argnum++)
3438 struct value *arg = args[argnum];
3439 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3440 int len = TYPE_LENGTH (arg_type);
3441 enum type_code typecode = TYPE_CODE (arg_type);
3444 fprintf_unfiltered (gdb_stdlog,
3445 "mips_o32_push_dummy_call: %d len=%d type=%d",
3446 argnum + 1, len, (int) typecode);
3448 val = (char *) VALUE_CONTENTS (arg);
3450 /* 32-bit ABIs always start floating point arguments in an
3451 even-numbered floating point register. Round the FP register
3452 up before the check to see if there are any FP registers
3453 left. O32/O64 targets also pass the FP in the integer
3454 registers so also round up normal registers. */
3455 if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type))
3457 if ((float_argreg & 1))
3461 /* Floating point arguments passed in registers have to be
3462 treated specially. On 32-bit architectures, doubles
3463 are passed in register pairs; the even register gets
3464 the low word, and the odd register gets the high word.
3465 On O32/O64, the first two floating point arguments are
3466 also copied to general registers, because MIPS16 functions
3467 don't use float registers for arguments. This duplication of
3468 arguments in general registers can't hurt non-MIPS16 functions
3469 because those registers are normally skipped. */
3471 if (fp_register_arg_p (typecode, arg_type)
3472 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3474 if (!FP_REGISTER_DOUBLE && len == 8)
3476 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3477 unsigned long regval;
3479 /* Write the low word of the double to the even register(s). */
3480 regval = extract_unsigned_integer (val + low_offset, 4);
3482 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3483 float_argreg, phex (regval, 4));
3484 write_register (float_argreg++, regval);
3486 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3487 argreg, phex (regval, 4));
3488 write_register (argreg++, regval);
3490 /* Write the high word of the double to the odd register(s). */
3491 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3493 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3494 float_argreg, phex (regval, 4));
3495 write_register (float_argreg++, regval);
3498 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3499 argreg, phex (regval, 4));
3500 write_register (argreg++, regval);
3504 /* This is a floating point value that fits entirely
3505 in a single register. */
3506 /* On 32 bit ABI's the float_argreg is further adjusted
3507 above to ensure that it is even register aligned. */
3508 LONGEST regval = extract_unsigned_integer (val, len);
3510 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3511 float_argreg, phex (regval, len));
3512 write_register (float_argreg++, regval);
3513 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3514 registers for each argument. The below is (my
3515 guess) to ensure that the corresponding integer
3516 register has reserved the same space. */
3518 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3519 argreg, phex (regval, len));
3520 write_register (argreg, regval);
3521 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3523 /* Reserve space for the FP register. */
3524 stack_offset += align_up (len, mips_stack_argsize (tdep));
3528 /* Copy the argument to general registers or the stack in
3529 register-sized pieces. Large arguments are split between
3530 registers and stack. */
3531 /* Note: structs whose size is not a multiple of
3532 mips_regsize() are treated specially: Irix cc passes them
3533 in registers where gcc sometimes puts them on the stack.
3534 For maximum compatibility, we will put them in both
3536 int odd_sized_struct = ((len > mips_saved_regsize (tdep))
3537 && (len % mips_saved_regsize (tdep) != 0));
3538 /* Structures should be aligned to eight bytes (even arg registers)
3539 on MIPS_ABI_O32, if their first member has double precision. */
3540 if (mips_saved_regsize (tdep) < 8
3541 && mips_type_needs_double_align (arg_type))
3546 /* Note: Floating-point values that didn't fit into an FP
3547 register are only written to memory. */
3550 /* Remember if the argument was written to the stack. */
3551 int stack_used_p = 0;
3552 int partial_len = (len < mips_saved_regsize (tdep)
3553 ? len : mips_saved_regsize (tdep));
3556 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3559 /* Write this portion of the argument to the stack. */
3560 if (argreg > MIPS_LAST_ARG_REGNUM
3562 || fp_register_arg_p (typecode, arg_type))
3564 /* Should shorter than int integer values be
3565 promoted to int before being stored? */
3566 int longword_offset = 0;
3569 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3571 if (mips_stack_argsize (tdep) == 8
3572 && (typecode == TYPE_CODE_INT
3573 || typecode == TYPE_CODE_PTR
3574 || typecode == TYPE_CODE_FLT) && len <= 4)
3575 longword_offset = mips_stack_argsize (tdep) - len;
3580 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3581 paddr_nz (stack_offset));
3582 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3583 paddr_nz (longword_offset));
3586 addr = sp + stack_offset + longword_offset;
3591 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3593 for (i = 0; i < partial_len; i++)
3595 fprintf_unfiltered (gdb_stdlog, "%02x",
3599 write_memory (addr, val, partial_len);
3602 /* Note!!! This is NOT an else clause. Odd sized
3603 structs may go thru BOTH paths. Floating point
3604 arguments will not. */
3605 /* Write this portion of the argument to a general
3606 purpose register. */
3607 if (argreg <= MIPS_LAST_ARG_REGNUM
3608 && !fp_register_arg_p (typecode, arg_type))
3610 LONGEST regval = extract_signed_integer (val, partial_len);
3611 /* Value may need to be sign extended, because
3612 mips_regsize() != mips_saved_regsize(). */
3614 /* A non-floating-point argument being passed in a
3615 general register. If a struct or union, and if
3616 the remaining length is smaller than the register
3617 size, we have to adjust the register value on
3620 It does not seem to be necessary to do the
3621 same for integral types.
3623 Also don't do this adjustment on O64 binaries.
3625 cagney/2001-07-23: gdb/179: Also, GCC, when
3626 outputting LE O32 with sizeof (struct) <
3627 mips_saved_regsize(), generates a left shift as
3628 part of storing the argument in a register a
3629 register (the left shift isn't generated when
3630 sizeof (struct) >= mips_saved_regsize()). Since
3631 it is quite possible that this is GCC
3632 contradicting the LE/O32 ABI, GDB has not been
3633 adjusted to accommodate this. Either someone
3634 needs to demonstrate that the LE/O32 ABI
3635 specifies such a left shift OR this new ABI gets
3636 identified as such and GDB gets tweaked
3639 if (mips_saved_regsize (tdep) < 8
3640 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3641 && partial_len < mips_saved_regsize (tdep)
3642 && (typecode == TYPE_CODE_STRUCT ||
3643 typecode == TYPE_CODE_UNION))
3644 regval <<= ((mips_saved_regsize (tdep) - partial_len) *
3648 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3651 mips_saved_regsize (tdep)));
3652 write_register (argreg, regval);
3655 /* Prevent subsequent floating point arguments from
3656 being passed in floating point registers. */
3657 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3663 /* Compute the the offset into the stack at which we
3664 will copy the next parameter.
3666 In older ABIs, the caller reserved space for
3667 registers that contained arguments. This was loosely
3668 refered to as their "home". Consequently, space is
3669 always allocated. */
3671 stack_offset += align_up (partial_len,
3672 mips_stack_argsize (tdep));
3676 fprintf_unfiltered (gdb_stdlog, "\n");
3679 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
3681 /* Return adjusted stack pointer. */
3685 static enum return_value_convention
3686 mips_o32_return_value (struct gdbarch *gdbarch, struct type *type,
3687 struct regcache *regcache,
3688 void *readbuf, const void *writebuf)
3690 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3692 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3693 || TYPE_CODE (type) == TYPE_CODE_UNION
3694 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
3695 return RETURN_VALUE_STRUCT_CONVENTION;
3696 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3697 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3699 /* A single-precision floating-point value. It fits in the
3700 least significant part of FP0. */
3702 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3703 mips_xfer_register (regcache,
3704 NUM_REGS + mips_regnum (current_gdbarch)->fp0,
3706 TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3707 return RETURN_VALUE_REGISTER_CONVENTION;
3709 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3710 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3712 /* A double-precision floating-point value. The most
3713 significant part goes in FP1, and the least significant in
3716 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
3717 switch (TARGET_BYTE_ORDER)
3719 case BFD_ENDIAN_LITTLE:
3720 mips_xfer_register (regcache,
3721 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3722 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3723 mips_xfer_register (regcache,
3724 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3725 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4);
3727 case BFD_ENDIAN_BIG:
3728 mips_xfer_register (regcache,
3729 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3730 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3731 mips_xfer_register (regcache,
3732 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3733 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4);
3736 internal_error (__FILE__, __LINE__, "bad switch");
3738 return RETURN_VALUE_REGISTER_CONVENTION;
3741 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3742 && TYPE_NFIELDS (type) <= 2
3743 && TYPE_NFIELDS (type) >= 1
3744 && ((TYPE_NFIELDS (type) == 1
3745 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3747 || (TYPE_NFIELDS (type) == 2
3748 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3750 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
3752 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3754 /* A struct that contains one or two floats. Each value is part
3755 in the least significant part of their floating point
3757 bfd_byte reg[MAX_REGISTER_SIZE];
3760 for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
3761 field < TYPE_NFIELDS (type); field++, regnum += 2)
3763 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3766 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3768 mips_xfer_register (regcache, NUM_REGS + regnum,
3769 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3770 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3772 return RETURN_VALUE_REGISTER_CONVENTION;
3776 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3777 || TYPE_CODE (type) == TYPE_CODE_UNION)
3779 /* A structure or union. Extract the left justified value,
3780 regardless of the byte order. I.e. DO NOT USE
3784 for (offset = 0, regnum = V0_REGNUM;
3785 offset < TYPE_LENGTH (type);
3786 offset += register_size (current_gdbarch, regnum), regnum++)
3788 int xfer = register_size (current_gdbarch, regnum);
3789 if (offset + xfer > TYPE_LENGTH (type))
3790 xfer = TYPE_LENGTH (type) - offset;
3792 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3793 offset, xfer, regnum);
3794 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3795 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
3797 return RETURN_VALUE_REGISTER_CONVENTION;
3802 /* A scalar extract each part but least-significant-byte
3803 justified. o32 thinks registers are 4 byte, regardless of
3804 the ISA. mips_stack_argsize controls this. */
3807 for (offset = 0, regnum = V0_REGNUM;
3808 offset < TYPE_LENGTH (type);
3809 offset += mips_stack_argsize (tdep), regnum++)
3811 int xfer = mips_stack_argsize (tdep);
3812 if (offset + xfer > TYPE_LENGTH (type))
3813 xfer = TYPE_LENGTH (type) - offset;
3815 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3816 offset, xfer, regnum);
3817 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3818 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3820 return RETURN_VALUE_REGISTER_CONVENTION;
3824 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3828 mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
3829 struct regcache *regcache, CORE_ADDR bp_addr,
3831 struct value **args, CORE_ADDR sp,
3832 int struct_return, CORE_ADDR struct_addr)
3838 int stack_offset = 0;
3839 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3841 /* For shared libraries, "t9" needs to point at the function
3843 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3845 /* Set the return address register to point to the entry point of
3846 the program, where a breakpoint lies in wait. */
3847 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3849 /* First ensure that the stack and structure return address (if any)
3850 are properly aligned. The stack has to be at least 64-bit
3851 aligned even on 32-bit machines, because doubles must be 64-bit
3852 aligned. For n32 and n64, stack frames need to be 128-bit
3853 aligned, so we round to this widest known alignment. */
3855 sp = align_down (sp, 16);
3856 struct_addr = align_down (struct_addr, 16);
3858 /* Now make space on the stack for the args. */
3859 for (argnum = 0; argnum < nargs; argnum++)
3860 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3861 mips_stack_argsize (tdep));
3862 sp -= align_up (len, 16);
3865 fprintf_unfiltered (gdb_stdlog,
3866 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3867 paddr_nz (sp), (long) align_up (len, 16));
3869 /* Initialize the integer and float register pointers. */
3871 float_argreg = mips_fpa0_regnum (current_gdbarch);
3873 /* The struct_return pointer occupies the first parameter-passing reg. */
3877 fprintf_unfiltered (gdb_stdlog,
3878 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3879 argreg, paddr_nz (struct_addr));
3880 write_register (argreg++, struct_addr);
3881 stack_offset += mips_stack_argsize (tdep);
3884 /* Now load as many as possible of the first arguments into
3885 registers, and push the rest onto the stack. Loop thru args
3886 from first to last. */
3887 for (argnum = 0; argnum < nargs; argnum++)
3890 struct value *arg = args[argnum];
3891 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3892 int len = TYPE_LENGTH (arg_type);
3893 enum type_code typecode = TYPE_CODE (arg_type);
3896 fprintf_unfiltered (gdb_stdlog,
3897 "mips_o64_push_dummy_call: %d len=%d type=%d",
3898 argnum + 1, len, (int) typecode);
3900 val = (char *) VALUE_CONTENTS (arg);
3902 /* 32-bit ABIs always start floating point arguments in an
3903 even-numbered floating point register. Round the FP register
3904 up before the check to see if there are any FP registers
3905 left. O32/O64 targets also pass the FP in the integer
3906 registers so also round up normal registers. */
3907 if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type))
3909 if ((float_argreg & 1))
3913 /* Floating point arguments passed in registers have to be
3914 treated specially. On 32-bit architectures, doubles
3915 are passed in register pairs; the even register gets
3916 the low word, and the odd register gets the high word.
3917 On O32/O64, the first two floating point arguments are
3918 also copied to general registers, because MIPS16 functions
3919 don't use float registers for arguments. This duplication of
3920 arguments in general registers can't hurt non-MIPS16 functions
3921 because those registers are normally skipped. */
3923 if (fp_register_arg_p (typecode, arg_type)
3924 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3926 if (!FP_REGISTER_DOUBLE && len == 8)
3928 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3929 unsigned long regval;
3931 /* Write the low word of the double to the even register(s). */
3932 regval = extract_unsigned_integer (val + low_offset, 4);
3934 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3935 float_argreg, phex (regval, 4));
3936 write_register (float_argreg++, regval);
3938 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3939 argreg, phex (regval, 4));
3940 write_register (argreg++, regval);
3942 /* Write the high word of the double to the odd register(s). */
3943 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3945 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3946 float_argreg, phex (regval, 4));
3947 write_register (float_argreg++, regval);
3950 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3951 argreg, phex (regval, 4));
3952 write_register (argreg++, regval);
3956 /* This is a floating point value that fits entirely
3957 in a single register. */
3958 /* On 32 bit ABI's the float_argreg is further adjusted
3959 above to ensure that it is even register aligned. */
3960 LONGEST regval = extract_unsigned_integer (val, len);
3962 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3963 float_argreg, phex (regval, len));
3964 write_register (float_argreg++, regval);
3965 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3966 registers for each argument. The below is (my
3967 guess) to ensure that the corresponding integer
3968 register has reserved the same space. */
3970 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3971 argreg, phex (regval, len));
3972 write_register (argreg, regval);
3973 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3975 /* Reserve space for the FP register. */
3976 stack_offset += align_up (len, mips_stack_argsize (tdep));
3980 /* Copy the argument to general registers or the stack in
3981 register-sized pieces. Large arguments are split between
3982 registers and stack. */
3983 /* Note: structs whose size is not a multiple of
3984 mips_regsize() are treated specially: Irix cc passes them
3985 in registers where gcc sometimes puts them on the stack.
3986 For maximum compatibility, we will put them in both
3988 int odd_sized_struct = ((len > mips_saved_regsize (tdep))
3989 && (len % mips_saved_regsize (tdep) != 0));
3990 /* Structures should be aligned to eight bytes (even arg registers)
3991 on MIPS_ABI_O32, if their first member has double precision. */
3992 if (mips_saved_regsize (tdep) < 8
3993 && mips_type_needs_double_align (arg_type))
3998 /* Note: Floating-point values that didn't fit into an FP
3999 register are only written to memory. */
4002 /* Remember if the argument was written to the stack. */
4003 int stack_used_p = 0;
4004 int partial_len = (len < mips_saved_regsize (tdep)
4005 ? len : mips_saved_regsize (tdep));
4008 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
4011 /* Write this portion of the argument to the stack. */
4012 if (argreg > MIPS_LAST_ARG_REGNUM
4014 || fp_register_arg_p (typecode, arg_type))
4016 /* Should shorter than int integer values be
4017 promoted to int before being stored? */
4018 int longword_offset = 0;
4021 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4023 if (mips_stack_argsize (tdep) == 8
4024 && (typecode == TYPE_CODE_INT
4025 || typecode == TYPE_CODE_PTR
4026 || typecode == TYPE_CODE_FLT) && len <= 4)
4027 longword_offset = mips_stack_argsize (tdep) - len;
4032 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
4033 paddr_nz (stack_offset));
4034 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
4035 paddr_nz (longword_offset));
4038 addr = sp + stack_offset + longword_offset;
4043 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
4045 for (i = 0; i < partial_len; i++)
4047 fprintf_unfiltered (gdb_stdlog, "%02x",
4051 write_memory (addr, val, partial_len);
4054 /* Note!!! This is NOT an else clause. Odd sized
4055 structs may go thru BOTH paths. Floating point
4056 arguments will not. */
4057 /* Write this portion of the argument to a general
4058 purpose register. */
4059 if (argreg <= MIPS_LAST_ARG_REGNUM
4060 && !fp_register_arg_p (typecode, arg_type))
4062 LONGEST regval = extract_signed_integer (val, partial_len);
4063 /* Value may need to be sign extended, because
4064 mips_regsize() != mips_saved_regsize(). */
4066 /* A non-floating-point argument being passed in a
4067 general register. If a struct or union, and if
4068 the remaining length is smaller than the register
4069 size, we have to adjust the register value on
4072 It does not seem to be necessary to do the
4073 same for integral types.
4075 Also don't do this adjustment on O64 binaries.
4077 cagney/2001-07-23: gdb/179: Also, GCC, when
4078 outputting LE O32 with sizeof (struct) <
4079 mips_saved_regsize(), generates a left shift as
4080 part of storing the argument in a register a
4081 register (the left shift isn't generated when
4082 sizeof (struct) >= mips_saved_regsize()). Since
4083 it is quite possible that this is GCC
4084 contradicting the LE/O32 ABI, GDB has not been
4085 adjusted to accommodate this. Either someone
4086 needs to demonstrate that the LE/O32 ABI
4087 specifies such a left shift OR this new ABI gets
4088 identified as such and GDB gets tweaked
4091 if (mips_saved_regsize (tdep) < 8
4092 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4093 && partial_len < mips_saved_regsize (tdep)
4094 && (typecode == TYPE_CODE_STRUCT ||
4095 typecode == TYPE_CODE_UNION))
4096 regval <<= ((mips_saved_regsize (tdep) - partial_len) *
4100 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
4103 mips_saved_regsize (tdep)));
4104 write_register (argreg, regval);
4107 /* Prevent subsequent floating point arguments from
4108 being passed in floating point registers. */
4109 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
4115 /* Compute the the offset into the stack at which we
4116 will copy the next parameter.
4118 In older ABIs, the caller reserved space for
4119 registers that contained arguments. This was loosely
4120 refered to as their "home". Consequently, space is
4121 always allocated. */
4123 stack_offset += align_up (partial_len,
4124 mips_stack_argsize (tdep));
4128 fprintf_unfiltered (gdb_stdlog, "\n");
4131 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
4133 /* Return adjusted stack pointer. */
4138 mips_o64_extract_return_value (struct type *valtype,
4139 char regbuf[], char *valbuf)
4141 struct return_value_word lo;
4142 struct return_value_word hi;
4143 return_value_location (valtype, &hi, &lo);
4145 memcpy (valbuf + lo.buf_offset,
4146 regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) +
4147 lo.reg_offset, lo.len);
4150 memcpy (valbuf + hi.buf_offset,
4151 regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) +
4152 hi.reg_offset, hi.len);
4156 mips_o64_store_return_value (struct type *valtype, char *valbuf)
4158 char raw_buffer[MAX_REGISTER_SIZE];
4159 struct return_value_word lo;
4160 struct return_value_word hi;
4161 return_value_location (valtype, &hi, &lo);
4163 memset (raw_buffer, 0, sizeof (raw_buffer));
4164 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
4165 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg),
4166 raw_buffer, register_size (current_gdbarch,
4171 memset (raw_buffer, 0, sizeof (raw_buffer));
4172 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
4173 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg),
4175 register_size (current_gdbarch,
4180 /* Floating point register management.
4182 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4183 64bit operations, these early MIPS cpus treat fp register pairs
4184 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4185 registers and offer a compatibility mode that emulates the MIPS2 fp
4186 model. When operating in MIPS2 fp compat mode, later cpu's split
4187 double precision floats into two 32-bit chunks and store them in
4188 consecutive fp regs. To display 64-bit floats stored in this
4189 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4190 Throw in user-configurable endianness and you have a real mess.
4192 The way this works is:
4193 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4194 double-precision value will be split across two logical registers.
4195 The lower-numbered logical register will hold the low-order bits,
4196 regardless of the processor's endianness.
4197 - If we are on a 64-bit processor, and we are looking for a
4198 single-precision value, it will be in the low ordered bits
4199 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4200 save slot in memory.
4201 - If we are in 64-bit mode, everything is straightforward.
4203 Note that this code only deals with "live" registers at the top of the
4204 stack. We will attempt to deal with saved registers later, when
4205 the raw/cooked register interface is in place. (We need a general
4206 interface that can deal with dynamic saved register sizes -- fp
4207 regs could be 32 bits wide in one frame and 64 on the frame above
4210 static struct type *
4211 mips_float_register_type (void)
4213 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4214 return builtin_type_ieee_single_big;
4216 return builtin_type_ieee_single_little;
4219 static struct type *
4220 mips_double_register_type (void)
4222 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4223 return builtin_type_ieee_double_big;
4225 return builtin_type_ieee_double_little;
4228 /* Copy a 32-bit single-precision value from the current frame
4229 into rare_buffer. */
4232 mips_read_fp_register_single (struct frame_info *frame, int regno,
4235 int raw_size = register_size (current_gdbarch, regno);
4236 char *raw_buffer = alloca (raw_size);
4238 if (!frame_register_read (frame, regno, raw_buffer))
4239 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
4242 /* We have a 64-bit value for this register. Find the low-order
4246 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4251 memcpy (rare_buffer, raw_buffer + offset, 4);
4255 memcpy (rare_buffer, raw_buffer, 4);
4259 /* Copy a 64-bit double-precision value from the current frame into
4260 rare_buffer. This may include getting half of it from the next
4264 mips_read_fp_register_double (struct frame_info *frame, int regno,
4267 int raw_size = register_size (current_gdbarch, regno);
4269 if (raw_size == 8 && !mips2_fp_compat ())
4271 /* We have a 64-bit value for this register, and we should use
4273 if (!frame_register_read (frame, regno, rare_buffer))
4274 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
4278 if ((regno - mips_regnum (current_gdbarch)->fp0) & 1)
4279 internal_error (__FILE__, __LINE__,
4280 "mips_read_fp_register_double: bad access to "
4281 "odd-numbered FP register");
4283 /* mips_read_fp_register_single will find the correct 32 bits from
4285 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4287 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
4288 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
4292 mips_read_fp_register_single (frame, regno, rare_buffer);
4293 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
4299 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
4301 { /* do values for FP (float) regs */
4303 double doub, flt1; /* doubles extracted from raw hex data */
4307 (char *) alloca (2 *
4308 register_size (current_gdbarch,
4309 mips_regnum (current_gdbarch)->fp0));
4311 fprintf_filtered (file, "%s:", REGISTER_NAME (regnum));
4312 fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)),
4315 if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ())
4317 /* 4-byte registers: Print hex and floating. Also print even
4318 numbered registers as doubles. */
4319 mips_read_fp_register_single (frame, regnum, raw_buffer);
4320 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4322 print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w',
4325 fprintf_filtered (file, " flt: ");
4327 fprintf_filtered (file, " <invalid float> ");
4329 fprintf_filtered (file, "%-17.9g", flt1);
4331 if (regnum % 2 == 0)
4333 mips_read_fp_register_double (frame, regnum, raw_buffer);
4334 doub = unpack_double (mips_double_register_type (), raw_buffer,
4337 fprintf_filtered (file, " dbl: ");
4339 fprintf_filtered (file, "<invalid double>");
4341 fprintf_filtered (file, "%-24.17g", doub);
4346 /* Eight byte registers: print each one as hex, float and double. */
4347 mips_read_fp_register_single (frame, regnum, raw_buffer);
4348 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4350 mips_read_fp_register_double (frame, regnum, raw_buffer);
4351 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2);
4354 print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g',
4357 fprintf_filtered (file, " flt: ");
4359 fprintf_filtered (file, "<invalid float>");
4361 fprintf_filtered (file, "%-17.9g", flt1);
4363 fprintf_filtered (file, " dbl: ");
4365 fprintf_filtered (file, "<invalid double>");
4367 fprintf_filtered (file, "%-24.17g", doub);
4372 mips_print_register (struct ui_file *file, struct frame_info *frame,
4373 int regnum, int all)
4375 struct gdbarch *gdbarch = get_frame_arch (frame);
4376 char raw_buffer[MAX_REGISTER_SIZE];
4379 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4381 mips_print_fp_register (file, frame, regnum);
4385 /* Get the data in raw format. */
4386 if (!frame_register_read (frame, regnum, raw_buffer))
4388 fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum));
4392 fputs_filtered (REGISTER_NAME (regnum), file);
4394 /* The problem with printing numeric register names (r26, etc.) is that
4395 the user can't use them on input. Probably the best solution is to
4396 fix it so that either the numeric or the funky (a2, etc.) names
4397 are accepted on input. */
4398 if (regnum < MIPS_NUMREGS)
4399 fprintf_filtered (file, "(r%d): ", regnum);
4401 fprintf_filtered (file, ": ");
4403 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4405 register_size (current_gdbarch,
4406 regnum) - register_size (current_gdbarch, regnum);
4410 print_scalar_formatted (raw_buffer + offset,
4411 gdbarch_register_type (gdbarch, regnum), 'x', 0,
4415 /* Replacement for generic do_registers_info.
4416 Print regs in pretty columns. */
4419 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
4422 fprintf_filtered (file, " ");
4423 mips_print_fp_register (file, frame, regnum);
4424 fprintf_filtered (file, "\n");
4429 /* Print a row's worth of GP (int) registers, with name labels above */
4432 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
4435 struct gdbarch *gdbarch = get_frame_arch (frame);
4436 /* do values for GP (int) regs */
4437 char raw_buffer[MAX_REGISTER_SIZE];
4438 int ncols = (mips_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */
4442 /* For GP registers, we print a separate row of names above the vals */
4443 fprintf_filtered (file, " ");
4444 for (col = 0, regnum = start_regnum;
4445 col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
4447 if (*REGISTER_NAME (regnum) == '\0')
4448 continue; /* unused register */
4449 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
4451 break; /* end the row: reached FP register */
4452 fprintf_filtered (file,
4453 mips_regsize (current_gdbarch) == 8 ? "%17s" : "%9s",
4454 REGISTER_NAME (regnum));
4457 /* print the R0 to R31 names */
4458 if ((start_regnum % NUM_REGS) < MIPS_NUMREGS)
4459 fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS);
4461 fprintf_filtered (file, "\n ");
4463 /* now print the values in hex, 4 or 8 to the row */
4464 for (col = 0, regnum = start_regnum;
4465 col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
4467 if (*REGISTER_NAME (regnum) == '\0')
4468 continue; /* unused register */
4469 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
4471 break; /* end row: reached FP register */
4472 /* OK: get the data in raw format. */
4473 if (!frame_register_read (frame, regnum, raw_buffer))
4474 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
4475 /* pad small registers */
4477 byte < (mips_regsize (current_gdbarch)
4478 - register_size (current_gdbarch, regnum)); byte++)
4479 printf_filtered (" ");
4480 /* Now print the register value in hex, endian order. */
4481 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4483 register_size (current_gdbarch,
4484 regnum) - register_size (current_gdbarch, regnum);
4485 byte < register_size (current_gdbarch, regnum); byte++)
4486 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]);
4488 for (byte = register_size (current_gdbarch, regnum) - 1;
4490 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]);
4491 fprintf_filtered (file, " ");
4494 if (col > 0) /* ie. if we actually printed anything... */
4495 fprintf_filtered (file, "\n");
4500 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4503 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4504 struct frame_info *frame, int regnum, int all)
4506 if (regnum != -1) /* do one specified register */
4508 gdb_assert (regnum >= NUM_REGS);
4509 if (*(REGISTER_NAME (regnum)) == '\0')
4510 error ("Not a valid register for the current processor type");
4512 mips_print_register (file, frame, regnum, 0);
4513 fprintf_filtered (file, "\n");
4516 /* do all (or most) registers */
4519 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4521 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
4524 if (all) /* true for "INFO ALL-REGISTERS" command */
4525 regnum = print_fp_register_row (file, frame, regnum);
4527 regnum += MIPS_NUMREGS; /* skip floating point regs */
4530 regnum = print_gp_register_row (file, frame, regnum);
4535 /* Is this a branch with a delay slot? */
4537 static int is_delayed (unsigned long);
4540 is_delayed (unsigned long insn)
4543 for (i = 0; i < NUMOPCODES; ++i)
4544 if (mips_opcodes[i].pinfo != INSN_MACRO
4545 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4547 return (i < NUMOPCODES
4548 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4549 | INSN_COND_BRANCH_DELAY
4550 | INSN_COND_BRANCH_LIKELY)));
4554 mips_step_skips_delay (CORE_ADDR pc)
4556 char buf[MIPS_INSTLEN];
4558 /* There is no branch delay slot on MIPS16. */
4559 if (pc_is_mips16 (pc))
4562 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
4563 /* If error reading memory, guess that it is not a delayed branch. */
4565 return is_delayed ((unsigned long)
4566 extract_unsigned_integer (buf, MIPS_INSTLEN));
4569 /* Skip the PC past function prologue instructions (32-bit version).
4570 This is a helper function for mips_skip_prologue. */
4573 mips32_skip_prologue (CORE_ADDR pc)
4577 int seen_sp_adjust = 0;
4578 int load_immediate_bytes = 0;
4580 /* Find an upper bound on the prologue. */
4581 end_pc = skip_prologue_using_sal (pc);
4583 end_pc = pc + 100; /* Magic. */
4585 /* Skip the typical prologue instructions. These are the stack adjustment
4586 instruction and the instructions that save registers on the stack
4587 or in the gcc frame. */
4588 for (; pc < end_pc; pc += MIPS_INSTLEN)
4590 unsigned long high_word;
4592 inst = mips_fetch_instruction (pc);
4593 high_word = (inst >> 16) & 0xffff;
4595 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
4596 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
4598 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
4599 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
4601 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4602 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4603 && (inst & 0x001F0000)) /* reg != $zero */
4606 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4608 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
4610 continue; /* reg != $zero */
4612 /* move $s8,$sp. With different versions of gas this will be either
4613 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4614 Accept any one of these. */
4615 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
4618 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4620 else if (high_word == 0x3c1c) /* lui $gp,n */
4622 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
4624 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
4625 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
4627 /* The following instructions load $at or $t0 with an immediate
4628 value in preparation for a stack adjustment via
4629 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4630 a local variable, so we accept them only before a stack adjustment
4631 instruction was seen. */
4632 else if (!seen_sp_adjust)
4634 if (high_word == 0x3c01 || /* lui $at,n */
4635 high_word == 0x3c08) /* lui $t0,n */
4637 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4640 else if (high_word == 0x3421 || /* ori $at,$at,n */
4641 high_word == 0x3508 || /* ori $t0,$t0,n */
4642 high_word == 0x3401 || /* ori $at,$zero,n */
4643 high_word == 0x3408) /* ori $t0,$zero,n */
4645 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4655 /* In a frameless function, we might have incorrectly
4656 skipped some load immediate instructions. Undo the skipping
4657 if the load immediate was not followed by a stack adjustment. */
4658 if (load_immediate_bytes && !seen_sp_adjust)
4659 pc -= load_immediate_bytes;
4663 /* Skip the PC past function prologue instructions (16-bit version).
4664 This is a helper function for mips_skip_prologue. */
4667 mips16_skip_prologue (CORE_ADDR pc)
4670 int extend_bytes = 0;
4671 int prev_extend_bytes;
4673 /* Table of instructions likely to be found in a function prologue. */
4676 unsigned short inst;
4677 unsigned short mask;
4683 , /* addiu $sp,offset */
4686 , /* daddiu $sp,offset */
4689 , /* sw reg,n($sp) */
4692 , /* sd reg,n($sp) */
4695 , /* sw $ra,n($sp) */
4698 , /* sd $ra,n($sp) */
4704 , /* sw $a0-$a3,n($s1) */
4707 , /* move reg,$a0-$a3 */
4710 , /* entry pseudo-op */
4713 , /* addiu $s1,$sp,n */
4715 0, 0} /* end of table marker */
4718 /* Find an upper bound on the prologue. */
4719 end_pc = skip_prologue_using_sal (pc);
4721 end_pc = pc + 100; /* Magic. */
4723 /* Skip the typical prologue instructions. These are the stack adjustment
4724 instruction and the instructions that save registers on the stack
4725 or in the gcc frame. */
4726 for (; pc < end_pc; pc += MIPS16_INSTLEN)
4728 unsigned short inst;
4731 inst = mips_fetch_instruction (pc);
4733 /* Normally we ignore an extend instruction. However, if it is
4734 not followed by a valid prologue instruction, we must adjust
4735 the pc back over the extend so that it won't be considered
4736 part of the prologue. */
4737 if ((inst & 0xf800) == 0xf000) /* extend */
4739 extend_bytes = MIPS16_INSTLEN;
4742 prev_extend_bytes = extend_bytes;
4745 /* Check for other valid prologue instructions besides extend. */
4746 for (i = 0; table[i].mask != 0; i++)
4747 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
4749 if (table[i].mask != 0) /* it was in table? */
4750 continue; /* ignore it */
4754 /* Return the current pc, adjusted backwards by 2 if
4755 the previous instruction was an extend. */
4756 return pc - prev_extend_bytes;
4762 /* To skip prologues, I use this predicate. Returns either PC itself
4763 if the code at PC does not look like a function prologue; otherwise
4764 returns an address that (if we're lucky) follows the prologue. If
4765 LENIENT, then we must skip everything which is involved in setting
4766 up the frame (it's OK to skip more, just so long as we don't skip
4767 anything which might clobber the registers which are being saved.
4768 We must skip more in the case where part of the prologue is in the
4769 delay slot of a non-prologue instruction). */
4772 mips_skip_prologue (CORE_ADDR pc)
4774 /* See if we can determine the end of the prologue via the symbol table.
4775 If so, then return either PC, or the PC after the prologue, whichever
4778 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
4780 if (post_prologue_pc != 0)
4781 return max (pc, post_prologue_pc);
4783 /* Can't determine prologue from the symbol table, need to examine
4786 if (pc_is_mips16 (pc))
4787 return mips16_skip_prologue (pc);
4789 return mips32_skip_prologue (pc);
4792 /* Exported procedure: Is PC in the signal trampoline code */
4795 mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore)
4797 if (sigtramp_address == 0)
4799 return (pc >= sigtramp_address && pc < sigtramp_end);
4802 /* Root of all "set mips "/"show mips " commands. This will eventually be
4803 used for all MIPS-specific commands. */
4806 show_mips_command (char *args, int from_tty)
4808 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
4812 set_mips_command (char *args, int from_tty)
4815 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4816 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
4819 /* Commands to show/set the MIPS FPU type. */
4822 show_mipsfpu_command (char *args, int from_tty)
4825 switch (MIPS_FPU_TYPE)
4827 case MIPS_FPU_SINGLE:
4828 fpu = "single-precision";
4830 case MIPS_FPU_DOUBLE:
4831 fpu = "double-precision";
4834 fpu = "absent (none)";
4837 internal_error (__FILE__, __LINE__, "bad switch");
4839 if (mips_fpu_type_auto)
4841 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4845 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
4850 set_mipsfpu_command (char *args, int from_tty)
4853 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4854 show_mipsfpu_command (args, from_tty);
4858 set_mipsfpu_single_command (char *args, int from_tty)
4860 struct gdbarch_info info;
4861 gdbarch_info_init (&info);
4862 mips_fpu_type = MIPS_FPU_SINGLE;
4863 mips_fpu_type_auto = 0;
4864 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4865 instead of relying on globals. Doing that would let generic code
4866 handle the search for this specific architecture. */
4867 if (!gdbarch_update_p (info))
4868 internal_error (__FILE__, __LINE__, "set mipsfpu failed");
4872 set_mipsfpu_double_command (char *args, int from_tty)
4874 struct gdbarch_info info;
4875 gdbarch_info_init (&info);
4876 mips_fpu_type = MIPS_FPU_DOUBLE;
4877 mips_fpu_type_auto = 0;
4878 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4879 instead of relying on globals. Doing that would let generic code
4880 handle the search for this specific architecture. */
4881 if (!gdbarch_update_p (info))
4882 internal_error (__FILE__, __LINE__, "set mipsfpu failed");
4886 set_mipsfpu_none_command (char *args, int from_tty)
4888 struct gdbarch_info info;
4889 gdbarch_info_init (&info);
4890 mips_fpu_type = MIPS_FPU_NONE;
4891 mips_fpu_type_auto = 0;
4892 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4893 instead of relying on globals. Doing that would let generic code
4894 handle the search for this specific architecture. */
4895 if (!gdbarch_update_p (info))
4896 internal_error (__FILE__, __LINE__, "set mipsfpu failed");
4900 set_mipsfpu_auto_command (char *args, int from_tty)
4902 mips_fpu_type_auto = 1;
4905 /* Attempt to identify the particular processor model by reading the
4906 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4907 the relevant processor still exists (it dates back to '94) and
4908 secondly this is not the way to do this. The processor type should
4909 be set by forcing an architecture change. */
4912 deprecated_mips_set_processor_regs_hack (void)
4914 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4917 prid = read_register (PRID_REGNUM);
4919 if ((prid & ~0xf) == 0x700)
4920 tdep->mips_processor_reg_names = mips_r3041_reg_names;
4923 /* Just like reinit_frame_cache, but with the right arguments to be
4924 callable as an sfunc. */
4927 reinit_frame_cache_sfunc (char *args, int from_tty,
4928 struct cmd_list_element *c)
4930 reinit_frame_cache ();
4934 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
4936 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4937 mips_extra_func_info_t proc_desc;
4939 /* Search for the function containing this address. Set the low bit
4940 of the address when searching, in case we were given an even address
4941 that is the start of a 16-bit function. If we didn't do this,
4942 the search would fail because the symbol table says the function
4943 starts at an odd address, i.e. 1 byte past the given address. */
4944 memaddr = ADDR_BITS_REMOVE (memaddr);
4945 proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL);
4947 /* Make an attempt to determine if this is a 16-bit function. If
4948 the procedure descriptor exists and the address therein is odd,
4949 it's definitely a 16-bit function. Otherwise, we have to just
4950 guess that if the address passed in is odd, it's 16-bits. */
4951 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4952 disassembler needs to be able to locally determine the ISA, and
4953 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4957 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
4958 info->mach = bfd_mach_mips16;
4962 if (pc_is_mips16 (memaddr))
4963 info->mach = bfd_mach_mips16;
4966 /* Round down the instruction address to the appropriate boundary. */
4967 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
4969 /* Set the disassembler options. */
4970 if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64)
4972 /* Set up the disassembler info, so that we get the right
4973 register names from libopcodes. */
4974 if (tdep->mips_abi == MIPS_ABI_N32)
4975 info->disassembler_options = "gpr-names=n32";
4977 info->disassembler_options = "gpr-names=64";
4978 info->flavour = bfd_target_elf_flavour;
4981 /* This string is not recognized explicitly by the disassembler,
4982 but it tells the disassembler to not try to guess the ABI from
4983 the bfd elf headers, such that, if the user overrides the ABI
4984 of a program linked as NewABI, the disassembly will follow the
4985 register naming conventions specified by the user. */
4986 info->disassembler_options = "gpr-names=32";
4988 /* Call the appropriate disassembler based on the target endian-ness. */
4989 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4990 return print_insn_big_mips (memaddr, info);
4992 return print_insn_little_mips (memaddr, info);
4995 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4996 counter value to determine whether a 16- or 32-bit breakpoint should be
4997 used. It returns a pointer to a string of bytes that encode a breakpoint
4998 instruction, stores the length of the string to *lenptr, and adjusts pc
4999 (if necessary) to point to the actual memory location where the
5000 breakpoint should be inserted. */
5002 static const unsigned char *
5003 mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
5005 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
5007 if (pc_is_mips16 (*pcptr))
5009 static unsigned char mips16_big_breakpoint[] = { 0xe8, 0xa5 };
5010 *pcptr = unmake_mips16_addr (*pcptr);
5011 *lenptr = sizeof (mips16_big_breakpoint);
5012 return mips16_big_breakpoint;
5016 /* The IDT board uses an unusual breakpoint value, and
5017 sometimes gets confused when it sees the usual MIPS
5018 breakpoint instruction. */
5019 static unsigned char big_breakpoint[] = { 0, 0x5, 0, 0xd };
5020 static unsigned char pmon_big_breakpoint[] = { 0, 0, 0, 0xd };
5021 static unsigned char idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd };
5023 *lenptr = sizeof (big_breakpoint);
5025 if (strcmp (target_shortname, "mips") == 0)
5026 return idt_big_breakpoint;
5027 else if (strcmp (target_shortname, "ddb") == 0
5028 || strcmp (target_shortname, "pmon") == 0
5029 || strcmp (target_shortname, "lsi") == 0)
5030 return pmon_big_breakpoint;
5032 return big_breakpoint;
5037 if (pc_is_mips16 (*pcptr))
5039 static unsigned char mips16_little_breakpoint[] = { 0xa5, 0xe8 };
5040 *pcptr = unmake_mips16_addr (*pcptr);
5041 *lenptr = sizeof (mips16_little_breakpoint);
5042 return mips16_little_breakpoint;
5046 static unsigned char little_breakpoint[] = { 0xd, 0, 0x5, 0 };
5047 static unsigned char pmon_little_breakpoint[] = { 0xd, 0, 0, 0 };
5048 static unsigned char idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 };
5050 *lenptr = sizeof (little_breakpoint);
5052 if (strcmp (target_shortname, "mips") == 0)
5053 return idt_little_breakpoint;
5054 else if (strcmp (target_shortname, "ddb") == 0
5055 || strcmp (target_shortname, "pmon") == 0
5056 || strcmp (target_shortname, "lsi") == 0)
5057 return pmon_little_breakpoint;
5059 return little_breakpoint;
5064 /* If PC is in a mips16 call or return stub, return the address of the target
5065 PC, which is either the callee or the caller. There are several
5066 cases which must be handled:
5068 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5069 target PC is in $31 ($ra).
5070 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5071 and the target PC is in $2.
5072 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5073 before the jal instruction, this is effectively a call stub
5074 and the the target PC is in $2. Otherwise this is effectively
5075 a return stub and the target PC is in $18.
5077 See the source code for the stubs in gcc/config/mips/mips16.S for
5080 This function implements the SKIP_TRAMPOLINE_CODE macro.
5084 mips_skip_stub (CORE_ADDR pc)
5087 CORE_ADDR start_addr;
5089 /* Find the starting address and name of the function containing the PC. */
5090 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
5093 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5094 target PC is in $31 ($ra). */
5095 if (strcmp (name, "__mips16_ret_sf") == 0
5096 || strcmp (name, "__mips16_ret_df") == 0)
5097 return read_signed_register (RA_REGNUM);
5099 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5101 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5102 and the target PC is in $2. */
5103 if (name[19] >= '0' && name[19] <= '9')
5104 return read_signed_register (2);
5106 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5107 before the jal instruction, this is effectively a call stub
5108 and the the target PC is in $2. Otherwise this is effectively
5109 a return stub and the target PC is in $18. */
5110 else if (name[19] == 's' || name[19] == 'd')
5112 if (pc == start_addr)
5114 /* Check if the target of the stub is a compiler-generated
5115 stub. Such a stub for a function bar might have a name
5116 like __fn_stub_bar, and might look like this:
5121 la $1,bar (becomes a lui/addiu pair)
5123 So scan down to the lui/addi and extract the target
5124 address from those two instructions. */
5126 CORE_ADDR target_pc = read_signed_register (2);
5130 /* See if the name of the target function is __fn_stub_*. */
5131 if (find_pc_partial_function (target_pc, &name, NULL, NULL) ==
5134 if (strncmp (name, "__fn_stub_", 10) != 0
5135 && strcmp (name, "etext") != 0
5136 && strcmp (name, "_etext") != 0)
5139 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5140 The limit on the search is arbitrarily set to 20
5141 instructions. FIXME. */
5142 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
5144 inst = mips_fetch_instruction (target_pc);
5145 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
5146 pc = (inst << 16) & 0xffff0000; /* high word */
5147 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
5148 return pc | (inst & 0xffff); /* low word */
5151 /* Couldn't find the lui/addui pair, so return stub address. */
5155 /* This is the 'return' part of a call stub. The return
5156 address is in $r18. */
5157 return read_signed_register (18);
5160 return 0; /* not a stub */
5164 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5165 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5168 mips_in_call_stub (CORE_ADDR pc, char *name)
5170 CORE_ADDR start_addr;
5172 /* Find the starting address of the function containing the PC. If the
5173 caller didn't give us a name, look it up at the same time. */
5174 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) ==
5178 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5180 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5181 if (name[19] >= '0' && name[19] <= '9')
5183 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5184 before the jal instruction, this is effectively a call stub. */
5185 else if (name[19] == 's' || name[19] == 'd')
5186 return pc == start_addr;
5189 return 0; /* not a stub */
5193 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5194 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5197 mips_in_return_stub (CORE_ADDR pc, char *name)
5199 CORE_ADDR start_addr;
5201 /* Find the starting address of the function containing the PC. */
5202 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
5205 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5206 if (strcmp (name, "__mips16_ret_sf") == 0
5207 || strcmp (name, "__mips16_ret_df") == 0)
5210 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5211 i.e. after the jal instruction, this is effectively a return stub. */
5212 if (strncmp (name, "__mips16_call_stub_", 19) == 0
5213 && (name[19] == 's' || name[19] == 'd') && pc != start_addr)
5216 return 0; /* not a stub */
5220 /* Return non-zero if the PC is in a library helper function that should
5221 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5224 mips_ignore_helper (CORE_ADDR pc)
5228 /* Find the starting address and name of the function containing the PC. */
5229 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
5232 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5233 that we want to ignore. */
5234 return (strcmp (name, "__mips16_ret_sf") == 0
5235 || strcmp (name, "__mips16_ret_df") == 0);
5239 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5240 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5243 mips_stab_reg_to_regnum (int num)
5246 if (num >= 0 && num < 32)
5248 else if (num >= 38 && num < 70)
5249 regnum = num + mips_regnum (current_gdbarch)->fp0 - 38;
5251 regnum = mips_regnum (current_gdbarch)->hi;
5253 regnum = mips_regnum (current_gdbarch)->lo;
5255 /* This will hopefully (eventually) provoke a warning. Should
5256 we be calling complaint() here? */
5257 return NUM_REGS + NUM_PSEUDO_REGS;
5258 return NUM_REGS + regnum;
5262 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5263 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5266 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num)
5269 if (num >= 0 && num < 32)
5271 else if (num >= 32 && num < 64)
5272 regnum = num + mips_regnum (current_gdbarch)->fp0 - 32;
5274 regnum = mips_regnum (current_gdbarch)->hi;
5276 regnum = mips_regnum (current_gdbarch)->lo;
5278 /* This will hopefully (eventually) provoke a warning. Should we
5279 be calling complaint() here? */
5280 return NUM_REGS + NUM_PSEUDO_REGS;
5281 return NUM_REGS + regnum;
5285 mips_register_sim_regno (int regnum)
5287 /* Only makes sense to supply raw registers. */
5288 gdb_assert (regnum >= 0 && regnum < NUM_REGS);
5289 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5290 decide if it is valid. Should instead define a standard sim/gdb
5291 register numbering scheme. */
5292 if (REGISTER_NAME (NUM_REGS + regnum) != NULL
5293 && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0')
5296 return LEGACY_SIM_REGNO_IGNORE;
5300 /* Convert an integer into an address. By first converting the value
5301 into a pointer and then extracting it signed, the address is
5302 guarenteed to be correctly sign extended. */
5305 mips_integer_to_address (struct type *type, void *buf)
5307 char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr));
5308 LONGEST val = unpack_long (type, buf);
5309 store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val);
5310 return extract_signed_integer (tmp,
5311 TYPE_LENGTH (builtin_type_void_data_ptr));
5315 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
5317 enum mips_abi *abip = (enum mips_abi *) obj;
5318 const char *name = bfd_get_section_name (abfd, sect);
5320 if (*abip != MIPS_ABI_UNKNOWN)
5323 if (strncmp (name, ".mdebug.", 8) != 0)
5326 if (strcmp (name, ".mdebug.abi32") == 0)
5327 *abip = MIPS_ABI_O32;
5328 else if (strcmp (name, ".mdebug.abiN32") == 0)
5329 *abip = MIPS_ABI_N32;
5330 else if (strcmp (name, ".mdebug.abi64") == 0)
5331 *abip = MIPS_ABI_N64;
5332 else if (strcmp (name, ".mdebug.abiO64") == 0)
5333 *abip = MIPS_ABI_O64;
5334 else if (strcmp (name, ".mdebug.eabi32") == 0)
5335 *abip = MIPS_ABI_EABI32;
5336 else if (strcmp (name, ".mdebug.eabi64") == 0)
5337 *abip = MIPS_ABI_EABI64;
5339 warning ("unsupported ABI %s.", name + 8);
5342 static enum mips_abi
5343 global_mips_abi (void)
5347 for (i = 0; mips_abi_strings[i] != NULL; i++)
5348 if (mips_abi_strings[i] == mips_abi_string)
5349 return (enum mips_abi) i;
5351 internal_error (__FILE__, __LINE__, "unknown ABI string");
5354 static struct gdbarch *
5355 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5357 struct gdbarch *gdbarch;
5358 struct gdbarch_tdep *tdep;
5360 enum mips_abi mips_abi, found_abi, wanted_abi;
5362 enum mips_fpu_type fpu_type;
5364 /* First of all, extract the elf_flags, if available. */
5365 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5366 elf_flags = elf_elfheader (info.abfd)->e_flags;
5367 else if (arches != NULL)
5368 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
5372 fprintf_unfiltered (gdb_stdlog,
5373 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
5375 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5376 switch ((elf_flags & EF_MIPS_ABI))
5378 case E_MIPS_ABI_O32:
5379 found_abi = MIPS_ABI_O32;
5381 case E_MIPS_ABI_O64:
5382 found_abi = MIPS_ABI_O64;
5384 case E_MIPS_ABI_EABI32:
5385 found_abi = MIPS_ABI_EABI32;
5387 case E_MIPS_ABI_EABI64:
5388 found_abi = MIPS_ABI_EABI64;
5391 if ((elf_flags & EF_MIPS_ABI2))
5392 found_abi = MIPS_ABI_N32;
5394 found_abi = MIPS_ABI_UNKNOWN;
5398 /* GCC creates a pseudo-section whose name describes the ABI. */
5399 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
5400 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
5402 /* If we have no usefu BFD information, use the ABI from the last
5403 MIPS architecture (if there is one). */
5404 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
5405 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
5407 /* Try the architecture for any hint of the correct ABI. */
5408 if (found_abi == MIPS_ABI_UNKNOWN
5409 && info.bfd_arch_info != NULL
5410 && info.bfd_arch_info->arch == bfd_arch_mips)
5412 switch (info.bfd_arch_info->mach)
5414 case bfd_mach_mips3900:
5415 found_abi = MIPS_ABI_EABI32;
5417 case bfd_mach_mips4100:
5418 case bfd_mach_mips5000:
5419 found_abi = MIPS_ABI_EABI64;
5421 case bfd_mach_mips8000:
5422 case bfd_mach_mips10000:
5423 /* On Irix, ELF64 executables use the N64 ABI. The
5424 pseudo-sections which describe the ABI aren't present
5425 on IRIX. (Even for executables created by gcc.) */
5426 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5427 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5428 found_abi = MIPS_ABI_N64;
5430 found_abi = MIPS_ABI_N32;
5436 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
5439 /* What has the user specified from the command line? */
5440 wanted_abi = global_mips_abi ();
5442 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
5445 /* Now that we have found what the ABI for this binary would be,
5446 check whether the user is overriding it. */
5447 if (wanted_abi != MIPS_ABI_UNKNOWN)
5448 mips_abi = wanted_abi;
5449 else if (found_abi != MIPS_ABI_UNKNOWN)
5450 mips_abi = found_abi;
5452 mips_abi = MIPS_ABI_O32;
5454 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
5457 /* Also used when doing an architecture lookup. */
5459 fprintf_unfiltered (gdb_stdlog,
5460 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5461 mips64_transfers_32bit_regs_p);
5463 /* Determine the MIPS FPU type. */
5464 if (!mips_fpu_type_auto)
5465 fpu_type = mips_fpu_type;
5466 else if (info.bfd_arch_info != NULL
5467 && info.bfd_arch_info->arch == bfd_arch_mips)
5468 switch (info.bfd_arch_info->mach)
5470 case bfd_mach_mips3900:
5471 case bfd_mach_mips4100:
5472 case bfd_mach_mips4111:
5473 fpu_type = MIPS_FPU_NONE;
5475 case bfd_mach_mips4650:
5476 fpu_type = MIPS_FPU_SINGLE;
5479 fpu_type = MIPS_FPU_DOUBLE;
5482 else if (arches != NULL)
5483 fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type;
5485 fpu_type = MIPS_FPU_DOUBLE;
5487 fprintf_unfiltered (gdb_stdlog,
5488 "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
5490 /* try to find a pre-existing architecture */
5491 for (arches = gdbarch_list_lookup_by_info (arches, &info);
5493 arches = gdbarch_list_lookup_by_info (arches->next, &info))
5495 /* MIPS needs to be pedantic about which ABI the object is
5497 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
5499 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
5501 /* Need to be pedantic about which register virtual size is
5503 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
5504 != mips64_transfers_32bit_regs_p)
5506 /* Be pedantic about which FPU is selected. */
5507 if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type)
5509 return arches->gdbarch;
5512 /* Need a new architecture. Fill in a target specific vector. */
5513 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
5514 gdbarch = gdbarch_alloc (&info, tdep);
5515 tdep->elf_flags = elf_flags;
5516 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
5517 tdep->found_abi = found_abi;
5518 tdep->mips_abi = mips_abi;
5519 tdep->mips_fpu_type = fpu_type;
5521 /* Initially set everything according to the default ABI/ISA. */
5522 set_gdbarch_short_bit (gdbarch, 16);
5523 set_gdbarch_int_bit (gdbarch, 32);
5524 set_gdbarch_float_bit (gdbarch, 32);
5525 set_gdbarch_double_bit (gdbarch, 64);
5526 set_gdbarch_long_double_bit (gdbarch, 64);
5527 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
5528 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
5529 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
5531 set_gdbarch_elf_make_msymbol_special (gdbarch,
5532 mips_elf_make_msymbol_special);
5534 /* Fill in the OS dependant register numbers and names. */
5536 const char **reg_names;
5537 struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch,
5538 struct mips_regnum);
5539 if (info.osabi == GDB_OSABI_IRIX)
5544 regnum->badvaddr = 66;
5547 regnum->fp_control_status = 69;
5548 regnum->fp_implementation_revision = 70;
5550 reg_names = mips_irix_reg_names;
5554 regnum->lo = MIPS_EMBED_LO_REGNUM;
5555 regnum->hi = MIPS_EMBED_HI_REGNUM;
5556 regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
5557 regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
5558 regnum->pc = MIPS_EMBED_PC_REGNUM;
5559 regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
5560 regnum->fp_control_status = 70;
5561 regnum->fp_implementation_revision = 71;
5563 if (info.bfd_arch_info != NULL
5564 && info.bfd_arch_info->mach == bfd_mach_mips3900)
5565 reg_names = mips_tx39_reg_names;
5567 reg_names = mips_generic_reg_names;
5569 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5570 replaced by read_pc? */
5571 set_gdbarch_pc_regnum (gdbarch, regnum->pc);
5572 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
5573 set_gdbarch_num_regs (gdbarch, num_regs);
5574 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
5575 set_gdbarch_register_name (gdbarch, mips_register_name);
5576 tdep->mips_processor_reg_names = reg_names;
5577 tdep->regnum = regnum;
5583 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
5584 set_gdbarch_return_value (gdbarch, mips_o32_return_value);
5585 tdep->mips_default_saved_regsize = 4;
5586 tdep->mips_default_stack_argsize = 4;
5587 tdep->mips_fp_register_double = 0;
5588 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5589 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5590 tdep->default_mask_address_p = 0;
5591 set_gdbarch_long_bit (gdbarch, 32);
5592 set_gdbarch_ptr_bit (gdbarch, 32);
5593 set_gdbarch_long_long_bit (gdbarch, 64);
5596 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
5597 set_gdbarch_deprecated_store_return_value (gdbarch,
5598 mips_o64_store_return_value);
5599 set_gdbarch_deprecated_extract_return_value (gdbarch,
5600 mips_o64_extract_return_value);
5601 tdep->mips_default_saved_regsize = 8;
5602 tdep->mips_default_stack_argsize = 8;
5603 tdep->mips_fp_register_double = 1;
5604 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5605 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5606 tdep->default_mask_address_p = 0;
5607 set_gdbarch_long_bit (gdbarch, 32);
5608 set_gdbarch_ptr_bit (gdbarch, 32);
5609 set_gdbarch_long_long_bit (gdbarch, 64);
5610 set_gdbarch_use_struct_convention (gdbarch,
5611 always_use_struct_convention);
5613 case MIPS_ABI_EABI32:
5614 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5615 set_gdbarch_deprecated_store_return_value (gdbarch,
5616 mips_eabi_store_return_value);
5617 set_gdbarch_deprecated_extract_return_value (gdbarch,
5618 mips_eabi_extract_return_value);
5619 tdep->mips_default_saved_regsize = 4;
5620 tdep->mips_default_stack_argsize = 4;
5621 tdep->mips_fp_register_double = 0;
5622 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5623 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5624 tdep->default_mask_address_p = 0;
5625 set_gdbarch_long_bit (gdbarch, 32);
5626 set_gdbarch_ptr_bit (gdbarch, 32);
5627 set_gdbarch_long_long_bit (gdbarch, 64);
5628 set_gdbarch_deprecated_reg_struct_has_addr
5629 (gdbarch, mips_eabi_reg_struct_has_addr);
5630 set_gdbarch_use_struct_convention (gdbarch,
5631 mips_eabi_use_struct_convention);
5633 case MIPS_ABI_EABI64:
5634 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5635 set_gdbarch_deprecated_store_return_value (gdbarch,
5636 mips_eabi_store_return_value);
5637 set_gdbarch_deprecated_extract_return_value (gdbarch,
5638 mips_eabi_extract_return_value);
5639 tdep->mips_default_saved_regsize = 8;
5640 tdep->mips_default_stack_argsize = 8;
5641 tdep->mips_fp_register_double = 1;
5642 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5643 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5644 tdep->default_mask_address_p = 0;
5645 set_gdbarch_long_bit (gdbarch, 64);
5646 set_gdbarch_ptr_bit (gdbarch, 64);
5647 set_gdbarch_long_long_bit (gdbarch, 64);
5648 set_gdbarch_deprecated_reg_struct_has_addr
5649 (gdbarch, mips_eabi_reg_struct_has_addr);
5650 set_gdbarch_use_struct_convention (gdbarch,
5651 mips_eabi_use_struct_convention);
5654 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5655 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5656 tdep->mips_default_saved_regsize = 8;
5657 tdep->mips_default_stack_argsize = 8;
5658 tdep->mips_fp_register_double = 1;
5659 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5660 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5661 tdep->default_mask_address_p = 0;
5662 set_gdbarch_long_bit (gdbarch, 32);
5663 set_gdbarch_ptr_bit (gdbarch, 32);
5664 set_gdbarch_long_long_bit (gdbarch, 64);
5667 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5668 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5669 tdep->mips_default_saved_regsize = 8;
5670 tdep->mips_default_stack_argsize = 8;
5671 tdep->mips_fp_register_double = 1;
5672 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5673 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5674 tdep->default_mask_address_p = 0;
5675 set_gdbarch_long_bit (gdbarch, 64);
5676 set_gdbarch_ptr_bit (gdbarch, 64);
5677 set_gdbarch_long_long_bit (gdbarch, 64);
5680 internal_error (__FILE__, __LINE__, "unknown ABI in switch");
5683 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5684 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5687 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5688 flag in object files because to do so would make it impossible to
5689 link with libraries compiled without "-gp32". This is
5690 unnecessarily restrictive.
5692 We could solve this problem by adding "-gp32" multilibs to gcc,
5693 but to set this flag before gcc is built with such multilibs will
5694 break too many systems.''
5696 But even more unhelpfully, the default linker output target for
5697 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5698 for 64-bit programs - you need to change the ABI to change this,
5699 and not all gcc targets support that currently. Therefore using
5700 this flag to detect 32-bit mode would do the wrong thing given
5701 the current gcc - it would make GDB treat these 64-bit programs
5702 as 32-bit programs by default. */
5704 set_gdbarch_read_pc (gdbarch, mips_read_pc);
5705 set_gdbarch_write_pc (gdbarch, mips_write_pc);
5706 set_gdbarch_read_sp (gdbarch, mips_read_sp);
5708 /* Add/remove bits from an address. The MIPS needs be careful to
5709 ensure that all 32 bit addresses are sign extended to 64 bits. */
5710 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5712 /* Unwind the frame. */
5713 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
5714 frame_unwind_append_sniffer (gdbarch, mips_mdebug_frame_sniffer);
5715 set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id);
5716 frame_base_append_sniffer (gdbarch, mips_mdebug_frame_base_sniffer);
5718 /* Map debug register numbers onto internal register numbers. */
5719 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5720 set_gdbarch_ecoff_reg_to_regnum (gdbarch,
5721 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5722 set_gdbarch_dwarf_reg_to_regnum (gdbarch,
5723 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5724 set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
5725 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5726 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
5728 /* MIPS version of CALL_DUMMY */
5730 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5731 replaced by a command, and all targets will default to on stack
5732 (regardless of the stack's execute status). */
5733 set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL);
5734 set_gdbarch_frame_align (gdbarch, mips_frame_align);
5736 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
5737 set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
5738 set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
5740 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5741 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
5743 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
5745 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
5746 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
5747 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
5749 set_gdbarch_register_type (gdbarch, mips_register_type);
5751 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
5752 set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp);
5754 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
5756 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5757 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5758 need to all be folded into the target vector. Since they are
5759 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5760 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5762 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
5764 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub);
5766 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
5767 to support MIPS16. This is a bad thing. Make sure not to do it
5768 if we have an OS ABI that actually supports shared libraries, since
5769 shared library support is more important. If we have an OS someday
5770 that supports both shared libraries and MIPS16, we'll have to find
5771 a better place for these. */
5772 if (info.osabi == GDB_OSABI_UNKNOWN)
5774 set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub);
5775 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub);
5778 /* Hook in OS ABI-specific overrides, if they have been registered. */
5779 gdbarch_init_osabi (info, gdbarch);
5785 mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
5787 struct gdbarch_info info;
5789 /* Force the architecture to update, and (if it's a MIPS architecture)
5790 mips_gdbarch_init will take care of the rest. */
5791 gdbarch_info_init (&info);
5792 gdbarch_update_p (info);
5795 /* Print out which MIPS ABI is in use. */
5798 show_mips_abi (char *ignore_args, int from_tty)
5800 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips)
5802 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
5805 enum mips_abi global_abi = global_mips_abi ();
5806 enum mips_abi actual_abi = mips_abi (current_gdbarch);
5807 const char *actual_abi_str = mips_abi_strings[actual_abi];
5809 if (global_abi == MIPS_ABI_UNKNOWN)
5811 ("The MIPS ABI is set automatically (currently \"%s\").\n",
5813 else if (global_abi == actual_abi)
5815 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5819 /* Probably shouldn't happen... */
5821 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5822 actual_abi_str, mips_abi_strings[global_abi]);
5828 mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
5830 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
5834 int ef_mips_32bitmode;
5835 /* determine the ISA */
5836 switch (tdep->elf_flags & EF_MIPS_ARCH)
5854 /* determine the size of a pointer */
5855 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
5856 fprintf_unfiltered (file,
5857 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5859 fprintf_unfiltered (file,
5860 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5862 fprintf_unfiltered (file,
5863 "mips_dump_tdep: ef_mips_arch = %d\n",
5865 fprintf_unfiltered (file,
5866 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5867 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
5868 fprintf_unfiltered (file,
5869 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5870 mips_mask_address_p (tdep),
5871 tdep->default_mask_address_p);
5873 fprintf_unfiltered (file,
5874 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5875 FP_REGISTER_DOUBLE);
5876 fprintf_unfiltered (file,
5877 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5878 MIPS_DEFAULT_FPU_TYPE,
5879 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
5880 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
5881 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
5883 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI);
5884 fprintf_unfiltered (file,
5885 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5887 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
5888 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
5889 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
5891 fprintf_unfiltered (file,
5892 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5893 FP_REGISTER_DOUBLE);
5894 fprintf_unfiltered (file,
5895 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5896 mips_stack_argsize (tdep));
5897 fprintf_unfiltered (file, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM);
5898 fprintf_unfiltered (file,
5899 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
5900 XSTRING (ADDR_BITS_REMOVE (ADDR)));
5901 fprintf_unfiltered (file,
5902 "mips_dump_tdep: ATTACH_DETACH # %s\n",
5903 XSTRING (ATTACH_DETACH));
5904 fprintf_unfiltered (file,
5905 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
5906 XSTRING (DWARF_REG_TO_REGNUM (REGNUM)));
5907 fprintf_unfiltered (file,
5908 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
5909 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM)));
5910 fprintf_unfiltered (file,
5911 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
5912 FIRST_EMBED_REGNUM);
5913 fprintf_unfiltered (file,
5914 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
5915 XSTRING (IGNORE_HELPER_CALL (PC)));
5916 fprintf_unfiltered (file,
5917 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
5918 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME)));
5919 fprintf_unfiltered (file,
5920 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
5921 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME)));
5922 fprintf_unfiltered (file,
5923 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
5925 #ifdef MACHINE_CPROC_FP_OFFSET
5926 fprintf_unfiltered (file,
5927 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
5928 MACHINE_CPROC_FP_OFFSET);
5930 #ifdef MACHINE_CPROC_PC_OFFSET
5931 fprintf_unfiltered (file,
5932 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
5933 MACHINE_CPROC_PC_OFFSET);
5935 #ifdef MACHINE_CPROC_SP_OFFSET
5936 fprintf_unfiltered (file,
5937 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
5938 MACHINE_CPROC_SP_OFFSET);
5940 fprintf_unfiltered (file,
5941 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
5943 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
5944 fprintf_unfiltered (file,
5945 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
5946 fprintf_unfiltered (file,
5947 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN);
5948 fprintf_unfiltered (file,
5949 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
5950 MIPS_LAST_ARG_REGNUM,
5951 MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1);
5952 fprintf_unfiltered (file,
5953 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS);
5954 fprintf_unfiltered (file,
5955 "mips_dump_tdep: mips_saved_regsize() = %d\n",
5956 mips_saved_regsize (tdep));
5957 fprintf_unfiltered (file,
5958 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM);
5959 fprintf_unfiltered (file,
5960 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
5961 fprintf_unfiltered (file,
5962 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
5963 fprintf_unfiltered (file,
5964 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
5965 fprintf_unfiltered (file, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
5966 fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
5967 fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
5968 fprintf_unfiltered (file, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
5969 fprintf_unfiltered (file, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
5970 fprintf_unfiltered (file, "mips_dump_tdep: PROC_PC_REG = function?\n");
5971 fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_MASK = function?\n");
5972 fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
5973 fprintf_unfiltered (file, "mips_dump_tdep: PROC_SYMBOL = function?\n");
5974 fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM);
5975 fprintf_unfiltered (file, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM);
5977 fprintf_unfiltered (file,
5978 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES);
5981 fprintf_unfiltered (file, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP);
5984 fprintf_unfiltered (file, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC);
5986 fprintf_unfiltered (file,
5987 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
5988 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS)));
5989 fprintf_unfiltered (file,
5990 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
5991 fprintf_unfiltered (file,
5992 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
5993 XSTRING (SKIP_TRAMPOLINE_CODE (PC)));
5994 fprintf_unfiltered (file,
5995 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
5996 XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P)));
5997 fprintf_unfiltered (file,
5998 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
5999 SOFTWARE_SINGLE_STEP_P ());
6000 fprintf_unfiltered (file,
6001 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6002 XSTRING (STAB_REG_TO_REGNUM (REGNUM)));
6003 #ifdef STACK_END_ADDR
6004 fprintf_unfiltered (file,
6005 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6008 fprintf_unfiltered (file,
6009 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6010 XSTRING (STEP_SKIPS_DELAY (PC)));
6011 fprintf_unfiltered (file,
6012 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6013 STEP_SKIPS_DELAY_P);
6014 fprintf_unfiltered (file,
6015 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6016 XSTRING (STOPPED_BY_WATCHPOINT (WS)));
6017 fprintf_unfiltered (file, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM);
6018 fprintf_unfiltered (file,
6019 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6020 fprintf_unfiltered (file,
6021 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6022 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6023 (TYPE, CNT, OTHERTYPE)));
6024 fprintf_unfiltered (file,
6025 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6026 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
6028 fprintf_unfiltered (file,
6029 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6030 XSTRING (TRACE_CLEAR (THREAD, STATE)));
6033 fprintf_unfiltered (file,
6034 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR);
6036 #ifdef TRACE_FLAVOR_SIZE
6037 fprintf_unfiltered (file,
6038 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6042 fprintf_unfiltered (file,
6043 "mips_dump_tdep: TRACE_SET # %s\n",
6044 XSTRING (TRACE_SET (X, STATE)));
6046 #ifdef UNUSED_REGNUM
6047 fprintf_unfiltered (file,
6048 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM);
6050 fprintf_unfiltered (file, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM);
6051 fprintf_unfiltered (file,
6052 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6053 (long) VM_MIN_ADDRESS);
6054 fprintf_unfiltered (file,
6055 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM);
6056 fprintf_unfiltered (file,
6057 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_);
6060 extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
6063 _initialize_mips_tdep (void)
6065 static struct cmd_list_element *mipsfpulist = NULL;
6066 struct cmd_list_element *c;
6068 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
6069 if (MIPS_ABI_LAST + 1
6070 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
6071 internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync");
6073 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
6075 mips_pdr_data = register_objfile_data ();
6077 /* Add root prefix command for all "set mips"/"show mips" commands */
6078 add_prefix_cmd ("mips", no_class, set_mips_command,
6079 "Various MIPS specific commands.",
6080 &setmipscmdlist, "set mips ", 0, &setlist);
6082 add_prefix_cmd ("mips", no_class, show_mips_command,
6083 "Various MIPS specific commands.",
6084 &showmipscmdlist, "show mips ", 0, &showlist);
6086 /* Allow the user to override the saved register size. */
6087 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6090 &mips_saved_regsize_string, "\
6091 Set size of general purpose registers saved on the stack.\n\
6092 This option can be set to one of:\n\
6093 32 - Force GDB to treat saved GP registers as 32-bit\n\
6094 64 - Force GDB to treat saved GP registers as 64-bit\n\
6095 auto - Allow GDB to use the target's default setting or autodetect the\n\
6096 saved GP register size from information contained in the executable.\n\
6097 (default: auto)", &setmipscmdlist), &showmipscmdlist);
6099 /* Allow the user to override the argument stack size. */
6100 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6103 &mips_stack_argsize_string, "\
6104 Set the amount of stack space reserved for each argument.\n\
6105 This option can be set to one of:\n\
6106 32 - Force GDB to allocate 32-bit chunks per argument\n\
6107 64 - Force GDB to allocate 64-bit chunks per argument\n\
6108 auto - Allow GDB to determine the correct setting from the current\n\
6109 target and executable (default)", &setmipscmdlist), &showmipscmdlist);
6111 /* Allow the user to override the ABI. */
6112 c = add_set_enum_cmd
6113 ("abi", class_obscure, mips_abi_strings, &mips_abi_string,
6114 "Set the ABI used by this program.\n"
6115 "This option can be set to one of:\n"
6116 " auto - the default ABI associated with the current binary\n"
6118 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist);
6119 set_cmd_sfunc (c, mips_abi_update);
6120 add_cmd ("abi", class_obscure, show_mips_abi,
6121 "Show ABI in use by MIPS target", &showmipscmdlist);
6123 /* Let the user turn off floating point and set the fence post for
6124 heuristic_proc_start. */
6126 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
6127 "Set use of MIPS floating-point coprocessor.",
6128 &mipsfpulist, "set mipsfpu ", 0, &setlist);
6129 add_cmd ("single", class_support, set_mipsfpu_single_command,
6130 "Select single-precision MIPS floating-point coprocessor.",
6132 add_cmd ("double", class_support, set_mipsfpu_double_command,
6133 "Select double-precision MIPS floating-point coprocessor.",
6135 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
6136 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
6137 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
6138 add_cmd ("none", class_support, set_mipsfpu_none_command,
6139 "Select no MIPS floating-point coprocessor.", &mipsfpulist);
6140 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
6141 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
6142 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
6143 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
6144 "Select MIPS floating-point coprocessor automatically.",
6146 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
6147 "Show current use of MIPS floating-point coprocessor target.",
6150 /* We really would like to have both "0" and "unlimited" work, but
6151 command.c doesn't deal with that. So make it a var_zinteger
6152 because the user can always use "999999" or some such for unlimited. */
6153 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
6154 (char *) &heuristic_fence_post, "\
6155 Set the distance searched for the start of a function.\n\
6156 If you are debugging a stripped executable, GDB needs to search through the\n\
6157 program for the start of a function. This command sets the distance of the\n\
6158 search. The only need to set it is when debugging a stripped executable.", &setlist);
6159 /* We need to throw away the frame cache when we set this, since it
6160 might change our ability to get backtraces. */
6161 set_cmd_sfunc (c, reinit_frame_cache_sfunc);
6162 add_show_from_set (c, &showlist);
6164 /* Allow the user to control whether the upper bits of 64-bit
6165 addresses should be zeroed. */
6166 add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\
6167 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6168 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6169 allow GDB to determine the correct value.\n", "\
6170 Show zeroing of upper 32 bits of 64-bit addresses.",
6171 NULL, show_mask_address, &setmipscmdlist, &showmipscmdlist);
6173 /* Allow the user to control the size of 32 bit registers within the
6174 raw remote packet. */
6175 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
6176 var_boolean, &mips64_transfers_32bit_regs_p, "\
6177 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6178 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6179 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6180 64 bits for others. Use \"off\" to disable compatibility mode", "\
6181 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6182 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6183 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6184 64 bits for others. Use \"off\" to disable compatibility mode", set_mips64_transfers_32bit_regs, NULL, &setlist, &showlist);
6186 /* Debug this files internals. */
6187 add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
6188 &mips_debug, "Set mips debugging.\n\
6189 When non-zero, mips specific debugging is enabled.", &setdebuglist), &showdebuglist);