2 * Copyright (c) 1991 The Regents of the University of California.
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6 * modification, are permitted provided that the following conditions
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14 * may be used to endorse or promote products derived from this software
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17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
33 #ifndef _MACHINE_SPECIALREG_H_
34 #define _MACHINE_SPECIALREG_H_
37 * Bits in 386 special registers:
39 #define CR0_PE 0x00000001 /* Protected mode Enable */
40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
43 #define CR0_PG 0x80000000 /* PaGing enable */
46 * Bits in 486 special registers:
48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
52 #define CR0_NW 0x20000000 /* Not Write-through */
53 #define CR0_CD 0x40000000 /* Cache Disable */
56 * Bits in PPro special registers
58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
60 #define CR4_TSD 0x00000004 /* Time stamp disable */
61 #define CR4_DE 0x00000008 /* Debugging extensions */
62 #define CR4_PSE 0x00000010 /* Page size extensions */
63 #define CR4_PAE 0x00000020 /* Physical address extension */
64 #define CR4_MCE 0x00000040 /* Machine check enable */
65 #define CR4_PGE 0x00000080 /* Page global enable */
66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
68 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
71 * Bits in AMD64 special registers. EFER is 64 bits wide.
73 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
74 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */
75 #define EFER_LMA 0x000000400 /* Long mode active (R) */
76 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
79 * CPUID instruction features register
81 #define CPUID_FPU 0x00000001
82 #define CPUID_VME 0x00000002
83 #define CPUID_DE 0x00000004
84 #define CPUID_PSE 0x00000008
85 #define CPUID_TSC 0x00000010
86 #define CPUID_MSR 0x00000020
87 #define CPUID_PAE 0x00000040
88 #define CPUID_MCE 0x00000080
89 #define CPUID_CX8 0x00000100
90 #define CPUID_APIC 0x00000200
91 #define CPUID_B10 0x00000400
92 #define CPUID_SEP 0x00000800
93 #define CPUID_MTRR 0x00001000
94 #define CPUID_PGE 0x00002000
95 #define CPUID_MCA 0x00004000
96 #define CPUID_CMOV 0x00008000
97 #define CPUID_PAT 0x00010000
98 #define CPUID_PSE36 0x00020000
99 #define CPUID_PSN 0x00040000
100 #define CPUID_CLFSH 0x00080000
101 #define CPUID_B20 0x00100000
102 #define CPUID_DS 0x00200000
103 #define CPUID_ACPI 0x00400000
104 #define CPUID_MMX 0x00800000
105 #define CPUID_FXSR 0x01000000
106 #define CPUID_SSE 0x02000000
107 #define CPUID_XMM 0x02000000
108 #define CPUID_SSE2 0x04000000
109 #define CPUID_SS 0x08000000
110 #define CPUID_HTT 0x10000000
111 #define CPUID_TM 0x20000000
112 #define CPUID_IA64 0x40000000
113 #define CPUID_PBE 0x80000000
115 #define CPUID2_SSE3 0x00000001
116 #define CPUID2_MON 0x00000008
117 #define CPUID2_DS_CPL 0x00000010
118 #define CPUID2_VMX 0x00000020
119 #define CPUID2_SMX 0x00000040
120 #define CPUID2_EST 0x00000080
121 #define CPUID2_TM2 0x00000100
122 #define CPUID2_SSSE3 0x00000200
123 #define CPUID2_CNXTID 0x00000400
124 #define CPUID2_CX16 0x00002000
125 #define CPUID2_XTPR 0x00004000
126 #define CPUID2_PDCM 0x00008000
127 #define CPUID2_DCA 0x00040000
130 * Important bits in the AMD extended cpuid flags
132 #define AMDID_SYSCALL 0x00000800
133 #define AMDID_MP 0x00080000
134 #define AMDID_NX 0x00100000
135 #define AMDID_EXT_MMX 0x00400000
136 #define AMDID_FFXSR 0x01000000
137 #define AMDID_PAGE1GB 0x04000000
138 #define AMDID_RDTSCP 0x08000000
139 #define AMDID_LM 0x20000000
140 #define AMDID_EXT_3DNOW 0x40000000
141 #define AMDID_3DNOW 0x80000000
143 #define AMDID2_LAHF 0x00000001
144 #define AMDID2_CMP 0x00000002
145 #define AMDID2_SVM 0x00000004
146 #define AMDID2_EXT_APIC 0x00000008
147 #define AMDID2_CR8 0x00000010
148 #define AMDID2_PREFETCH 0x00000100
151 * CPUID instruction 1 eax info
153 #define CPUID_STEPPING 0x0000000f
154 #define CPUID_MODEL 0x000000f0
155 #define CPUID_FAMILY 0x00000f00
156 #define CPUID_EXT_MODEL 0x000f0000
157 #define CPUID_EXT_FAMILY 0x0ff00000
158 #define AMD64_CPU_MODEL(id) \
159 ((((id) & CPUID_MODEL) >> 4) | \
160 (((id) & CPUID_EXT_MODEL) >> 12))
161 #define AMD64_CPU_FAMILY(id) \
162 ((((id) & CPUID_FAMILY) >> 8) + \
163 (((id) & CPUID_EXT_FAMILY) >> 20))
166 * CPUID instruction 1 ebx info
168 #define CPUID_BRAND_INDEX 0x000000ff
169 #define CPUID_CLFUSH_SIZE 0x0000ff00
170 #define CPUID_HTT_CORES 0x00ff0000
171 #define CPUID_LOCAL_APIC_ID 0xff000000
174 * AMD extended function 8000_0007h edx info
176 #define AMDPM_TS 0x00000001
177 #define AMDPM_FID 0x00000002
178 #define AMDPM_VID 0x00000004
179 #define AMDPM_TTP 0x00000008
180 #define AMDPM_TM 0x00000010
181 #define AMDPM_STC 0x00000020
182 #define AMDPM_100MHZ_STEPS 0x00000040
183 #define AMDPM_HW_PSTATE 0x00000080
184 #define AMDPM_TSC_INVARIANT 0x00000100
187 * AMD extended function 8000_0008h ecx info
189 #define AMDID_CMP_CORES 0x000000ff
192 * CPUID manufacturers identifiers
194 #define INTEL_VENDOR_ID "GenuineIntel"
195 #define AMD_VENDOR_ID "AuthenticAMD"
198 * Model-specific registers for the i386 family
200 #define MSR_P5_MC_ADDR 0x000
201 #define MSR_P5_MC_TYPE 0x001
202 #define MSR_TSC 0x010
203 #define MSR_P5_CESR 0x011
204 #define MSR_P5_CTR0 0x012
205 #define MSR_P5_CTR1 0x013
206 #define MSR_IA32_PLATFORM_ID 0x017
207 #define MSR_APICBASE 0x01b
208 #define MSR_EBL_CR_POWERON 0x02a
209 #define MSR_TEST_CTL 0x033
210 #define MSR_BIOS_UPDT_TRIG 0x079
211 #define MSR_BBL_CR_D0 0x088
212 #define MSR_BBL_CR_D1 0x089
213 #define MSR_BBL_CR_D2 0x08a
214 #define MSR_BIOS_SIGN 0x08b
215 #define MSR_PERFCTR0 0x0c1
216 #define MSR_PERFCTR1 0x0c2
217 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
218 #define MSR_MTRRcap 0x0fe
219 #define MSR_BBL_CR_ADDR 0x116
220 #define MSR_BBL_CR_DECC 0x118
221 #define MSR_BBL_CR_CTL 0x119
222 #define MSR_BBL_CR_TRIG 0x11a
223 #define MSR_BBL_CR_BUSY 0x11b
224 #define MSR_BBL_CR_CTL3 0x11e
225 #define MSR_SYSENTER_CS_MSR 0x174
226 #define MSR_SYSENTER_ESP_MSR 0x175
227 #define MSR_SYSENTER_EIP_MSR 0x176
228 #define MSR_MCG_CAP 0x179
229 #define MSR_MCG_STATUS 0x17a
230 #define MSR_MCG_CTL 0x17b
231 #define MSR_EVNTSEL0 0x186
232 #define MSR_EVNTSEL1 0x187
233 #define MSR_THERM_CONTROL 0x19a
234 #define MSR_THERM_INTERRUPT 0x19b
235 #define MSR_THERM_STATUS 0x19c
236 #define MSR_IA32_MISC_ENABLE 0x1a0
237 #define MSR_DEBUGCTLMSR 0x1d9
238 #define MSR_LASTBRANCHFROMIP 0x1db
239 #define MSR_LASTBRANCHTOIP 0x1dc
240 #define MSR_LASTINTFROMIP 0x1dd
241 #define MSR_LASTINTTOIP 0x1de
242 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
243 #define MSR_MTRRVarBase 0x200
244 #define MSR_MTRR64kBase 0x250
245 #define MSR_MTRR16kBase 0x258
246 #define MSR_MTRR4kBase 0x268
247 #define MSR_PAT 0x277
248 #define MSR_MTRRdefType 0x2ff
249 #define MSR_MC0_CTL 0x400
250 #define MSR_MC0_STATUS 0x401
251 #define MSR_MC0_ADDR 0x402
252 #define MSR_MC0_MISC 0x403
253 #define MSR_MC1_CTL 0x404
254 #define MSR_MC1_STATUS 0x405
255 #define MSR_MC1_ADDR 0x406
256 #define MSR_MC1_MISC 0x407
257 #define MSR_MC2_CTL 0x408
258 #define MSR_MC2_STATUS 0x409
259 #define MSR_MC2_ADDR 0x40a
260 #define MSR_MC2_MISC 0x40b
261 #define MSR_MC3_CTL 0x40c
262 #define MSR_MC3_STATUS 0x40d
263 #define MSR_MC3_ADDR 0x40e
264 #define MSR_MC3_MISC 0x40f
265 #define MSR_MC4_CTL 0x410
266 #define MSR_MC4_STATUS 0x411
267 #define MSR_MC4_ADDR 0x412
268 #define MSR_MC4_MISC 0x413
271 * Constants related to MSR's.
273 #define APICBASE_RESERVED 0x000006ff
274 #define APICBASE_BSP 0x00000100
275 #define APICBASE_ENABLED 0x00000800
276 #define APICBASE_ADDRESS 0xfffff000
281 #define PAT_UNCACHEABLE 0x00
282 #define PAT_WRITE_COMBINING 0x01
283 #define PAT_WRITE_THROUGH 0x04
284 #define PAT_WRITE_PROTECTED 0x05
285 #define PAT_WRITE_BACK 0x06
286 #define PAT_UNCACHED 0x07
287 #define PAT_VALUE(i, m) ((long)(m) << (8 * (i)))
288 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
291 * Constants related to MTRRs
293 #define MTRR_UNCACHEABLE 0x00
294 #define MTRR_WRITE_COMBINING 0x01
295 #define MTRR_WRITE_THROUGH 0x04
296 #define MTRR_WRITE_PROTECTED 0x05
297 #define MTRR_WRITE_BACK 0x06
298 #define MTRR_N64K 8 /* numbers of fixed-size entries */
301 #define MTRR_CAP_WC 0x0000000000000400UL
302 #define MTRR_CAP_FIXED 0x0000000000000100UL
303 #define MTRR_CAP_VCNT 0x00000000000000ffUL
304 #define MTRR_DEF_ENABLE 0x0000000000000800UL
305 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400UL
306 #define MTRR_DEF_TYPE 0x00000000000000ffUL
307 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000UL
308 #define MTRR_PHYSBASE_TYPE 0x00000000000000ffUL
309 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000UL
310 #define MTRR_PHYSMASK_VALID 0x0000000000000800UL
312 /* Performance Control Register (5x86 only). */
314 #define PCR0_RSTK 0x01 /* Enables return stack */
315 #define PCR0_BTB 0x02 /* Enables branch target buffer */
316 #define PCR0_LOOP 0x04 /* Enables loop */
317 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
319 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
320 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
321 #define PCR0_LSSER 0x80 /* Disable reorder */
323 /* Device Identification Registers */
328 * The following four 3-byte registers control the non-cacheable regions.
329 * These registers must be written as three separate bytes.
331 * NCRx+0: A31-A24 of starting address
332 * NCRx+1: A23-A16 of starting address
333 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
335 * The non-cacheable region's starting address must be aligned to the
336 * size indicated by the NCR_SIZE_xx field.
343 #define NCR_SIZE_0K 0
344 #define NCR_SIZE_4K 1
345 #define NCR_SIZE_8K 2
346 #define NCR_SIZE_16K 3
347 #define NCR_SIZE_32K 4
348 #define NCR_SIZE_64K 5
349 #define NCR_SIZE_128K 6
350 #define NCR_SIZE_256K 7
351 #define NCR_SIZE_512K 8
352 #define NCR_SIZE_1M 9
353 #define NCR_SIZE_2M 10
354 #define NCR_SIZE_4M 11
355 #define NCR_SIZE_8M 12
356 #define NCR_SIZE_16M 13
357 #define NCR_SIZE_32M 14
358 #define NCR_SIZE_4G 15
361 * The address region registers are used to specify the location and
362 * size for the eight address regions.
364 * ARRx + 0: A31-A24 of start address
365 * ARRx + 1: A23-A16 of start address
366 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
377 #define ARR_SIZE_0K 0
378 #define ARR_SIZE_4K 1
379 #define ARR_SIZE_8K 2
380 #define ARR_SIZE_16K 3
381 #define ARR_SIZE_32K 4
382 #define ARR_SIZE_64K 5
383 #define ARR_SIZE_128K 6
384 #define ARR_SIZE_256K 7
385 #define ARR_SIZE_512K 8
386 #define ARR_SIZE_1M 9
387 #define ARR_SIZE_2M 10
388 #define ARR_SIZE_4M 11
389 #define ARR_SIZE_8M 12
390 #define ARR_SIZE_16M 13
391 #define ARR_SIZE_32M 14
392 #define ARR_SIZE_4G 15
395 * The region control registers specify the attributes associated with
396 * the ARRx addres regions.
407 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
408 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
409 #define RCR_WWO 0x02 /* Weak write ordering. */
410 #define RCR_WL 0x04 /* Weak locking. */
411 #define RCR_WG 0x08 /* Write gathering. */
412 #define RCR_WT 0x10 /* Write-through. */
413 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
415 /* AMD Write Allocate Top-Of-Memory and Control Register */
416 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
417 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
418 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
421 #define MSR_EFER 0xc0000080 /* extended features */
422 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
423 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
424 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
425 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
426 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
427 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
428 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
429 #define MSR_PERFEVSEL0 0xc0010000
430 #define MSR_PERFEVSEL1 0xc0010001
431 #define MSR_PERFEVSEL2 0xc0010002
432 #define MSR_PERFEVSEL3 0xc0010003
435 #define MSR_PERFCTR0 0xc0010004
436 #define MSR_PERFCTR1 0xc0010005
437 #define MSR_PERFCTR2 0xc0010006
438 #define MSR_PERFCTR3 0xc0010007
439 #define MSR_SYSCFG 0xc0010010
440 #define MSR_IORRBASE0 0xc0010016
441 #define MSR_IORRMASK0 0xc0010017
442 #define MSR_IORRBASE1 0xc0010018
443 #define MSR_IORRMASK1 0xc0010019
444 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
445 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
446 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
448 #endif /* !_MACHINE_SPECIALREG_H_ */