2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_auto_eoi.h"
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/interrupt.h>
44 #include <sys/kernel.h>
46 #include <sys/module.h>
47 #include <sys/mutex.h>
49 #include <machine/cpufunc.h>
50 #include <machine/frame.h>
51 #include <machine/intr_machdep.h>
52 #include <machine/md_var.h>
53 #include <machine/resource.h>
54 #include <machine/segments.h>
56 #include <dev/ic/i8259.h>
57 #include <amd64/isa/icu.h>
58 #include <amd64/isa/isa.h>
60 #include <isa/isavar.h>
66 * PC-AT machines wire the slave PIC to pin 2 on the master PIC.
71 * Determine the base master and slave modes not including auto EOI support.
72 * All machines that FreeBSD supports use 8086 mode.
74 #define BASE_MASTER_MODE ICW4_8086
75 #define BASE_SLAVE_MODE ICW4_8086
77 /* Enable automatic EOI if requested. */
79 #define MASTER_MODE (BASE_MASTER_MODE | ICW4_AEOI)
81 #define MASTER_MODE BASE_MASTER_MODE
84 #define SLAVE_MODE (BASE_SLAVE_MODE | ICW4_AEOI)
86 #define SLAVE_MODE BASE_SLAVE_MODE
89 #define IRQ_MASK(irq) (1 << (irq))
90 #define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq))
92 #define NUM_ISA_IRQS 16
94 static void atpic_init(void *dummy);
96 unsigned int imen; /* XXX */
99 IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
100 IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
101 IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
102 IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
103 IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
104 IDTVEC(atpic_intr15);
106 #define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
108 #define ATPIC(io, base, eoi, imenptr) \
109 { { atpic_enable_source, atpic_disable_source, (eoi), \
110 atpic_enable_intr, atpic_disable_intr, atpic_vector, \
111 atpic_source_pending, NULL, atpic_resume, atpic_config_intr,\
112 atpic_assign_cpu }, (io), (base), IDT_IO_INTS + (base), \
115 #define INTSRC(irq) \
116 { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
127 struct atpic_intsrc {
128 struct intsrc at_intsrc;
130 int at_irq; /* Relative to PIC base. */
131 enum intr_trigger at_trigger;
133 u_long at_straycount;
136 static void atpic_enable_source(struct intsrc *isrc);
137 static void atpic_disable_source(struct intsrc *isrc, int eoi);
138 static void atpic_eoi_master(struct intsrc *isrc);
139 static void atpic_eoi_slave(struct intsrc *isrc);
140 static void atpic_enable_intr(struct intsrc *isrc);
141 static void atpic_disable_intr(struct intsrc *isrc);
142 static int atpic_vector(struct intsrc *isrc);
143 static void atpic_resume(struct pic *pic);
144 static int atpic_source_pending(struct intsrc *isrc);
145 static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
146 enum intr_polarity pol);
147 static void atpic_assign_cpu(struct intsrc *isrc, u_int apic_id);
148 static void i8259_init(struct atpic *pic, int slave);
150 static struct atpic atpics[] = {
151 ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen),
152 ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1)
155 static struct atpic_intsrc atintrs[] = {
174 CTASSERT(sizeof(atintrs) / sizeof(atintrs[0]) == NUM_ISA_IRQS);
177 _atpic_eoi_master(struct intsrc *isrc)
180 KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
181 ("%s: mismatched pic", __func__));
183 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
188 * The data sheet says no auto-EOI on slave, but it sometimes works.
189 * So, if AUTO_EOI_2 is enabled, we use it.
192 _atpic_eoi_slave(struct intsrc *isrc)
195 KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
196 ("%s: mismatched pic", __func__));
198 outb(atpics[SLAVE].at_ioaddr, OCW2_EOI);
200 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
206 atpic_enable_source(struct intsrc *isrc)
208 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
209 struct atpic *ap = (struct atpic *)isrc->is_pic;
211 mtx_lock_spin(&icu_lock);
212 if (*ap->at_imen & IMEN_MASK(ai)) {
213 *ap->at_imen &= ~IMEN_MASK(ai);
214 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
216 mtx_unlock_spin(&icu_lock);
220 atpic_disable_source(struct intsrc *isrc, int eoi)
222 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
223 struct atpic *ap = (struct atpic *)isrc->is_pic;
225 mtx_lock_spin(&icu_lock);
226 if (ai->at_trigger != INTR_TRIGGER_EDGE) {
227 *ap->at_imen |= IMEN_MASK(ai);
228 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
232 * Take care to call these functions directly instead of through
233 * a function pointer. All of the referenced variables should
234 * still be hot in the cache.
236 if (eoi == PIC_EOI) {
237 if (isrc->is_pic == &atpics[MASTER].at_pic)
238 _atpic_eoi_master(isrc);
240 _atpic_eoi_slave(isrc);
243 mtx_unlock_spin(&icu_lock);
247 atpic_eoi_master(struct intsrc *isrc)
250 mtx_lock_spin(&icu_lock);
251 _atpic_eoi_master(isrc);
252 mtx_unlock_spin(&icu_lock);
257 atpic_eoi_slave(struct intsrc *isrc)
260 mtx_lock_spin(&icu_lock);
261 _atpic_eoi_slave(isrc);
262 mtx_unlock_spin(&icu_lock);
267 atpic_enable_intr(struct intsrc *isrc)
272 atpic_disable_intr(struct intsrc *isrc)
278 atpic_vector(struct intsrc *isrc)
280 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
281 struct atpic *ap = (struct atpic *)isrc->is_pic;
283 return (IRQ(ap, ai));
287 atpic_source_pending(struct intsrc *isrc)
289 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
290 struct atpic *ap = (struct atpic *)isrc->is_pic;
292 return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
296 atpic_resume(struct pic *pic)
298 struct atpic *ap = (struct atpic *)pic;
300 i8259_init(ap, ap == &atpics[SLAVE]);
301 if (ap == &atpics[SLAVE] && elcr_found)
306 atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
307 enum intr_polarity pol)
309 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
312 /* Map conforming values to edge/hi and sanity check the values. */
313 if (trig == INTR_TRIGGER_CONFORM)
314 trig = INTR_TRIGGER_EDGE;
315 if (pol == INTR_POLARITY_CONFORM)
316 pol = INTR_POLARITY_HIGH;
317 vector = atpic_vector(isrc);
318 if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) ||
319 (trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) {
321 "atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n",
322 vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level",
323 pol == INTR_POLARITY_HIGH ? "high" : "low");
327 /* If there is no change, just return. */
328 if (ai->at_trigger == trig)
332 * Certain IRQs can never be level/lo, so don't try to set them
333 * that way if asked. At least some ELCR registers ignore setting
334 * these bits as well.
336 if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) &&
337 trig == INTR_TRIGGER_LEVEL) {
340 "atpic: Ignoring invalid level/low configuration for IRQ%u\n",
346 printf("atpic: No ELCR to configure IRQ%u as %s\n",
347 vector, trig == INTR_TRIGGER_EDGE ? "edge/high" :
352 printf("atpic: Programming IRQ%u as %s\n", vector,
353 trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low");
354 mtx_lock_spin(&icu_lock);
355 elcr_write_trigger(atpic_vector(isrc), trig);
356 ai->at_trigger = trig;
357 mtx_unlock_spin(&icu_lock);
362 atpic_assign_cpu(struct intsrc *isrc, u_int apic_id)
366 * 8259A's are only used in UP in which case all interrupts always
367 * go to the sole CPU and this function shouldn't even be called.
369 panic("%s: bad cookie", __func__);
373 i8259_init(struct atpic *pic, int slave)
377 /* Reset the PIC and program with next four bytes. */
378 mtx_lock_spin(&icu_lock);
379 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4);
380 imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
383 outb(imr_addr, pic->at_intbase);
386 * Setup slave links. For the master pic, indicate what line
387 * the slave is configured on. For the slave indicate
388 * which line on the master we are connected to.
391 outb(imr_addr, ICU_SLAVEID);
393 outb(imr_addr, IRQ_MASK(ICU_SLAVEID));
397 outb(imr_addr, SLAVE_MODE);
399 outb(imr_addr, MASTER_MODE);
401 /* Set interrupt enable mask. */
402 outb(imr_addr, *pic->at_imen);
404 /* Reset is finished, default to IRR on read. */
405 outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR);
407 /* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */
409 outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1);
410 mtx_unlock_spin(&icu_lock);
416 struct atpic_intsrc *ai;
419 /* Start off with all interrupts disabled. */
421 i8259_init(&atpics[MASTER], 0);
422 i8259_init(&atpics[SLAVE], 1);
423 atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
425 /* Install low-level interrupt handlers for all of our IRQs. */
426 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
427 if (i == ICU_SLAVEID)
429 ai->at_intsrc.is_count = &ai->at_count;
430 ai->at_intsrc.is_straycount = &ai->at_straycount;
431 setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
432 ai->at_irq, ai->at_intr, SDT_SYSIGT, SEL_KPL, 0);
436 * Look for an ELCR. If we find one, update the trigger modes.
437 * If we don't find one, assume that IRQs 0, 1, 2, and 13 are
438 * edge triggered and that everything else is level triggered.
439 * We only use the trigger information to reprogram the ELCR if
440 * we have one and as an optimization to avoid masking edge
441 * triggered interrupts. For the case that we don't have an ELCR,
442 * it doesn't hurt to mask an edge triggered interrupt, so we
443 * assume level trigger for any interrupt that we aren't sure is
447 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
448 ai->at_trigger = elcr_read_trigger(i);
450 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
457 ai->at_trigger = INTR_TRIGGER_EDGE;
460 ai->at_trigger = INTR_TRIGGER_LEVEL;
467 atpic_init(void *dummy __unused)
469 struct atpic_intsrc *ai;
473 * Register our PICs, even if we aren't going to use any of their
474 * pins so that they are suspended and resumed.
476 if (intr_register_pic(&atpics[0].at_pic) != 0 ||
477 intr_register_pic(&atpics[1].at_pic) != 0)
478 panic("Unable to register ATPICs");
481 * If any of the ISA IRQs have an interrupt source already, then
482 * assume that the APICs are being used and don't register any
483 * of our interrupt sources. This makes sure we don't accidentally
484 * use mixed mode. The "accidental" use could otherwise occur on
485 * machines that route the ACPI SCI interrupt to a different ISA
486 * IRQ (at least one machines routes it to IRQ 13) thus disabling
487 * that APIC ISA routing and allowing the ATPIC source for that IRQ
488 * to leak through. We used to depend on this feature for routing
489 * IRQ0 via mixed mode, but now we don't use mixed mode at all.
491 for (i = 0; i < NUM_ISA_IRQS; i++)
492 if (intr_lookup_source(i) != NULL)
495 /* Loop through all interrupt sources and add them. */
496 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
497 if (i == ICU_SLAVEID)
499 intr_register_source(&ai->at_intsrc);
502 SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_SECOND + 1, atpic_init, NULL);
505 atpic_handle_intr(u_int vector, struct trapframe *frame)
509 KASSERT(vector < NUM_ISA_IRQS, ("unknown int %u\n", vector));
510 isrc = &atintrs[vector].at_intsrc;
513 * If we don't have an event, see if this is a spurious
516 if (isrc->is_event == NULL && (vector == 7 || vector == 15)) {
520 * Read the ISR register to see if IRQ 7/15 is really
521 * pending. Reset read register back to IRR when done.
523 port = ((struct atpic *)isrc->is_pic)->at_ioaddr;
524 mtx_lock_spin(&icu_lock);
525 outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS);
527 outb(port, OCW3_SEL | OCW3_RR);
528 mtx_unlock_spin(&icu_lock);
529 if ((isr & IRQ_MASK(7)) == 0)
532 intr_execute_handlers(isrc, frame);
537 * Bus attachment for the ISA PIC.
539 static struct isa_pnp_id atpic_ids[] = {
540 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
545 atpic_probe(device_t dev)
549 result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
556 * We might be granted IRQ 2, as this is typically consumed by chaining
557 * between the two PIC components. If we're using the APIC, however,
558 * this may not be the case, and as such we should free the resource.
561 * The generic ISA attachment code will handle allocating any other resources
562 * that we don't explicitly claim here.
565 atpic_attach(device_t dev)
567 struct resource *res;
570 /* Try to allocate our IRQ and then free it. */
572 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
574 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
578 static device_method_t atpic_methods[] = {
579 /* Device interface */
580 DEVMETHOD(device_probe, atpic_probe),
581 DEVMETHOD(device_attach, atpic_attach),
582 DEVMETHOD(device_detach, bus_generic_detach),
583 DEVMETHOD(device_shutdown, bus_generic_shutdown),
584 DEVMETHOD(device_suspend, bus_generic_suspend),
585 DEVMETHOD(device_resume, bus_generic_resume),
589 static driver_t atpic_driver = {
595 static devclass_t atpic_devclass;
597 DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
598 DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
601 * Return a bitmap of the current interrupt requests. This is 8259-specific
602 * and is only suitable for use at probe time.
605 isa_irq_pending(void)
612 return ((irr2 << 8) | irr1);