2 * Copyright (c) 2005 Olivier Houchard. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD$");
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
31 #include <sys/module.h>
34 #include <sys/resource.h>
36 #include <sys/timetc.h>
37 #include <sys/watchdog.h>
39 #include <machine/bus.h>
40 #include <machine/cpu.h>
41 #include <machine/cpufunc.h>
42 #include <machine/resource.h>
43 #include <machine/frame.h>
44 #include <machine/intr.h>
45 #include <arm/at91/at91rm92reg.h>
46 #include <arm/at91/at91var.h>
47 #include <arm/at91/at91_streg.h>
49 static struct at91st_softc {
50 bus_space_tag_t sc_st;
51 bus_space_handle_t sc_sh;
53 eventhandler_tag sc_wet; /* watchdog event handler tag */
57 bus_space_read_4(timer_softc->sc_st, timer_softc->sc_sh, (off))
58 #define WR4(off, val) \
59 bus_space_write_4(timer_softc->sc_st, timer_softc->sc_sh, (off), (val))
61 static void at91st_watchdog(void *, u_int, int *);
70 } while (cur1 != cur2);
74 static unsigned at91st_get_timecount(struct timecounter *tc);
76 static struct timecounter at91st_timecounter = {
77 at91st_get_timecount, /* get_timecount */
78 NULL, /* no poll_pps */
79 #ifdef SKYEYE_WORKAROUNDS
80 0xffffffffu, /* counter_mask */
82 0xfffffu, /* counter_mask */
84 32768, /* frequency */
85 "AT91RM9200 timer", /* name */
90 at91st_probe(device_t dev)
93 device_set_desc(dev, "ST");
98 at91st_attach(device_t dev)
100 struct at91_softc *sc = device_get_softc(device_get_parent(dev));
102 timer_softc = device_get_softc(dev);
103 timer_softc->sc_st = sc->sc_st;
104 timer_softc->sc_dev = dev;
105 if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_ST_BASE,
106 AT91RM92_ST_SIZE, &timer_softc->sc_sh) != 0)
107 panic("couldn't subregion timer registers");
109 * Real time counter increments every clock cycle, need to set before
110 * initializing clocks so that DELAY works.
113 /* Disable all interrupts */
114 WR4(ST_IDR, 0xffffffff);
115 /* disable watchdog timer */
118 timer_softc->sc_wet = EVENTHANDLER_REGISTER(watchdog_list,
119 at91st_watchdog, dev, 0);
121 "watchdog registered, timeout intervall max. 64 sec\n");
125 static device_method_t at91st_methods[] = {
126 DEVMETHOD(device_probe, at91st_probe),
127 DEVMETHOD(device_attach, at91st_attach),
131 static driver_t at91st_driver = {
134 sizeof(struct at91st_softc),
136 static devclass_t at91st_devclass;
138 DRIVER_MODULE(at91_st, atmelarm, at91st_driver, at91st_devclass, 0, 0);
140 #ifdef SKYEYE_WORKAROUNDS
141 static unsigned long tot_count = 0;
145 at91st_get_timecount(struct timecounter *tc)
147 #ifdef SKYEYE_WORKAROUNDS
155 * t below is in a weird unit. The watchdog is set to 2^t
156 * nanoseconds. Since our watchdog timer can't really do that too
157 * well, we approximate it by assuming that the timeout interval for
158 * the lsb is 2^22 ns, which is 4.194ms. This is an overestimation of
159 * the actual time (3.906ms), but close enough for watchdogging.
160 * These approximations, though a violation of the spec, improve the
161 * performance of the application which typically specifies things as
162 * WD_TO_32SEC. In that last case, we'd wait 32s before the wdog
163 * reset. The spec says we should wait closer to 34s, but given how
164 * it is likely to be used, and the extremely coarse nature time
165 * interval, I think this is the best solution.
168 at91st_watchdog(void *argp, u_int cmd, int *error)
173 t = cmd & WD_INTERVAL;
174 if (t >= 22 && t <= 37) {
175 wdog = (1 << (t - 22)) | ST_WDMR_RSTEN;
181 WR4(ST_CR, ST_CR_WDRST);
185 clock_intr(void *arg)
187 struct trapframe *fp = arg;
189 /* The interrupt is shared, so we have to make sure it's for us. */
190 if (RD4(ST_SR) & ST_SR_PITS) {
191 #ifdef SKYEYE_WORKAROUNDS
192 tot_count += 32768 / hz;
194 hardclock(TRAPF_USERMODE(fp), TRAPF_PC(fp));
195 return (FILTER_HANDLED);
197 return (FILTER_STRAY);
204 struct resource *irq;
207 device_t dev = timer_softc->sc_dev;
209 rel_value = 32768 / hz;
213 printf("Cannot get %d Hz clock; using %dHz\n", hz, 32768 / rel_value);
214 hz = 32768 / rel_value;
217 /* Disable all interrupts. */
218 WR4(ST_IDR, 0xffffffff);
219 /* The system timer shares the system irq (1) */
220 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 1, 1, 1,
221 RF_ACTIVE | RF_SHAREABLE);
223 panic("Unable to allocate irq for the system timer");
225 bus_setup_intr(dev, irq, INTR_TYPE_CLK,
226 clock_intr, NULL, NULL, &ih);
228 WR4(ST_PIMR, rel_value);
230 /* Enable PITS interrupts. */
231 WR4(ST_IER, ST_SR_PITS);
232 tc_init(&at91st_timecounter);
238 uint32_t start, end, cur;
241 n = (n * 1000) / 32768;
244 end = (start + n) & ST_CRTR_MASK;
247 while (cur >= start || cur < end)
259 * Reset the CPU by programmig the watchdog timer to reset the
260 * CPU after 128 'slow' clocks, or about ~4ms. Loop until
261 * the reset happens for safety.
263 WR4(ST_WDMR, ST_WDMR_RSTEN | 2);
264 WR4(ST_CR, ST_CR_WDRST);
270 cpu_startprofclock(void)
275 cpu_stopprofclock(void)