2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
40 #include <sys/module.h>
42 #include <sys/queue.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_llc.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
58 #include <netinet/in.h>
59 #include <netinet/in_systm.h>
60 #include <netinet/ip.h>
61 #include <netinet/tcp.h>
63 #include <dev/mii/mii.h>
64 #include <dev/mii/miivar.h>
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
69 #include <machine/atomic.h>
70 #include <machine/bus.h>
71 #include <machine/in_cksum.h>
73 #include <dev/ale/if_alereg.h>
74 #include <dev/ale/if_alevar.h>
76 /* "device miibus" required. See GENERIC if you get errors here. */
77 #include "miibus_if.h"
79 /* For more information about Tx checksum offload issues see ale_encap(). */
80 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
81 #ifndef IFCAP_VLAN_HWTSO
82 #define IFCAP_VLAN_HWTSO 0
85 MODULE_DEPEND(ale, pci, 1, 1, 1);
86 MODULE_DEPEND(ale, ether, 1, 1, 1);
87 MODULE_DEPEND(ale, miibus, 1, 1, 1);
90 static int msi_disable = 0;
91 static int msix_disable = 0;
92 TUNABLE_INT("hw.ale.msi_disable", &msi_disable);
93 TUNABLE_INT("hw.ale.msix_disable", &msix_disable);
96 * Devices supported by this driver.
98 static struct ale_dev {
99 uint16_t ale_vendorid;
100 uint16_t ale_deviceid;
101 const char *ale_name;
103 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX,
104 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" },
107 static int ale_attach(device_t);
108 static int ale_check_boundary(struct ale_softc *);
109 static int ale_detach(device_t);
110 static int ale_dma_alloc(struct ale_softc *);
111 static void ale_dma_free(struct ale_softc *);
112 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int);
113 static int ale_encap(struct ale_softc *, struct mbuf **);
114 static void ale_get_macaddr(struct ale_softc *);
115 static void ale_init(void *);
116 static void ale_init_locked(struct ale_softc *);
117 static void ale_init_rx_pages(struct ale_softc *);
118 static void ale_init_tx_ring(struct ale_softc *);
119 static void ale_int_task(void *, int);
120 static int ale_intr(void *);
121 static int ale_ioctl(struct ifnet *, u_long, caddr_t);
122 static void ale_link_task(void *, int);
123 static void ale_mac_config(struct ale_softc *);
124 static int ale_miibus_readreg(device_t, int, int);
125 static void ale_miibus_statchg(device_t);
126 static int ale_miibus_writereg(device_t, int, int, int);
127 static int ale_mediachange(struct ifnet *);
128 static void ale_mediastatus(struct ifnet *, struct ifmediareq *);
129 static void ale_phy_reset(struct ale_softc *);
130 static int ale_probe(device_t);
131 static void ale_reset(struct ale_softc *);
132 static int ale_resume(device_t);
133 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
134 uint32_t, uint32_t *);
135 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
136 static int ale_rxeof(struct ale_softc *sc, int);
137 static void ale_rxfilter(struct ale_softc *);
138 static void ale_rxvlan(struct ale_softc *);
139 static void ale_setlinkspeed(struct ale_softc *);
140 static void ale_setwol(struct ale_softc *);
141 static int ale_shutdown(device_t);
142 static void ale_start(struct ifnet *);
143 static void ale_stats_clear(struct ale_softc *);
144 static void ale_stats_update(struct ale_softc *);
145 static void ale_stop(struct ale_softc *);
146 static void ale_stop_mac(struct ale_softc *);
147 static int ale_suspend(device_t);
148 static void ale_sysctl_node(struct ale_softc *);
149 static void ale_tick(void *);
150 static void ale_tx_task(void *, int);
151 static void ale_txeof(struct ale_softc *);
152 static void ale_watchdog(struct ale_softc *);
153 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
154 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS);
155 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS);
157 static device_method_t ale_methods[] = {
158 /* Device interface. */
159 DEVMETHOD(device_probe, ale_probe),
160 DEVMETHOD(device_attach, ale_attach),
161 DEVMETHOD(device_detach, ale_detach),
162 DEVMETHOD(device_shutdown, ale_shutdown),
163 DEVMETHOD(device_suspend, ale_suspend),
164 DEVMETHOD(device_resume, ale_resume),
167 DEVMETHOD(miibus_readreg, ale_miibus_readreg),
168 DEVMETHOD(miibus_writereg, ale_miibus_writereg),
169 DEVMETHOD(miibus_statchg, ale_miibus_statchg),
174 static driver_t ale_driver = {
177 sizeof(struct ale_softc)
180 static devclass_t ale_devclass;
182 DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, 0, 0);
183 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, 0, 0);
185 static struct resource_spec ale_res_spec_mem[] = {
186 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
190 static struct resource_spec ale_irq_spec_legacy[] = {
191 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
195 static struct resource_spec ale_irq_spec_msi[] = {
196 { SYS_RES_IRQ, 1, RF_ACTIVE },
200 static struct resource_spec ale_irq_spec_msix[] = {
201 { SYS_RES_IRQ, 1, RF_ACTIVE },
206 ale_miibus_readreg(device_t dev, int phy, int reg)
208 struct ale_softc *sc;
212 sc = device_get_softc(dev);
214 if (phy != sc->ale_phyaddr)
217 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
218 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
219 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
221 v = CSR_READ_4(sc, ALE_MDIO);
222 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
227 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
231 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
235 ale_miibus_writereg(device_t dev, int phy, int reg, int val)
237 struct ale_softc *sc;
241 sc = device_get_softc(dev);
243 if (phy != sc->ale_phyaddr)
246 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
247 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
248 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
249 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
251 v = CSR_READ_4(sc, ALE_MDIO);
252 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
257 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
263 ale_miibus_statchg(device_t dev)
265 struct ale_softc *sc;
267 sc = device_get_softc(dev);
269 taskqueue_enqueue(taskqueue_swi, &sc->ale_link_task);
273 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
275 struct ale_softc *sc;
276 struct mii_data *mii;
280 mii = device_get_softc(sc->ale_miibus);
284 ifmr->ifm_status = mii->mii_media_status;
285 ifmr->ifm_active = mii->mii_media_active;
289 ale_mediachange(struct ifnet *ifp)
291 struct ale_softc *sc;
292 struct mii_data *mii;
293 struct mii_softc *miisc;
298 mii = device_get_softc(sc->ale_miibus);
299 if (mii->mii_instance != 0) {
300 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
301 mii_phy_reset(miisc);
303 error = mii_mediachg(mii);
310 ale_probe(device_t dev)
314 uint16_t vendor, devid;
316 vendor = pci_get_vendor(dev);
317 devid = pci_get_device(dev);
319 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) {
320 if (vendor == sp->ale_vendorid &&
321 devid == sp->ale_deviceid) {
322 device_set_desc(dev, sp->ale_name);
323 return (BUS_PROBE_DEFAULT);
332 ale_get_macaddr(struct ale_softc *sc)
337 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
338 if ((reg & SPI_VPD_ENB) != 0) {
340 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
343 if (pci_find_extcap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) {
345 * PCI VPD capability found, let TWSI reload EEPROM.
346 * This will set ethernet address of controller.
348 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
349 TWSI_CTRL_SW_LD_START);
350 for (i = 100; i > 0; i--) {
352 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
353 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
357 device_printf(sc->ale_dev,
358 "reloading EEPROM timeout!\n");
361 device_printf(sc->ale_dev,
362 "PCI VPD capability not found!\n");
365 ea[0] = CSR_READ_4(sc, ALE_PAR0);
366 ea[1] = CSR_READ_4(sc, ALE_PAR1);
367 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
368 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
369 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
370 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
371 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
372 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
376 ale_phy_reset(struct ale_softc *sc)
379 /* Reset magic from Linux. */
380 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
381 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
382 GPHY_CTRL_PHY_PLL_ON);
384 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
385 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
386 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
389 #define ATPHY_DBG_ADDR 0x1D
390 #define ATPHY_DBG_DATA 0x1E
392 /* Enable hibernation mode. */
393 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
394 ATPHY_DBG_ADDR, 0x0B);
395 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
396 ATPHY_DBG_DATA, 0xBC00);
397 /* Set Class A/B for all modes. */
398 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
399 ATPHY_DBG_ADDR, 0x00);
400 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
401 ATPHY_DBG_DATA, 0x02EF);
402 /* Enable 10BT power saving. */
403 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
404 ATPHY_DBG_ADDR, 0x12);
405 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
406 ATPHY_DBG_DATA, 0x4C04);
407 /* Adjust 1000T power. */
408 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
409 ATPHY_DBG_ADDR, 0x04);
410 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
411 ATPHY_DBG_ADDR, 0x8BBB);
412 /* 10BT center tap voltage. */
413 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
414 ATPHY_DBG_ADDR, 0x05);
415 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
416 ATPHY_DBG_ADDR, 0x2C46);
418 #undef ATPHY_DBG_ADDR
419 #undef ATPHY_DBG_DATA
424 ale_attach(device_t dev)
426 struct ale_softc *sc;
429 int error, i, msic, msixc, pmc;
430 uint32_t rxf_len, txf_len;
433 sc = device_get_softc(dev);
436 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
438 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0);
439 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc);
440 TASK_INIT(&sc->ale_link_task, 0, ale_link_task, sc);
442 /* Map the device. */
443 pci_enable_busmaster(dev);
444 sc->ale_res_spec = ale_res_spec_mem;
445 sc->ale_irq_spec = ale_irq_spec_legacy;
446 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res);
448 device_printf(dev, "cannot allocate memory resources.\n");
452 /* Set PHY address. */
453 sc->ale_phyaddr = ALE_PHY_ADDR;
458 /* Reset the ethernet controller. */
461 /* Get PCI and chip id/revision. */
462 sc->ale_rev = pci_get_revid(dev);
463 if (sc->ale_rev >= 0xF0) {
464 /* L2E Rev. B. AR8114 */
465 sc->ale_flags |= ALE_FLAG_FASTETHER;
467 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
469 sc->ale_flags |= ALE_FLAG_JUMBO;
471 /* L2E Rev. A. AR8113 */
472 sc->ale_flags |= ALE_FLAG_FASTETHER;
476 * All known controllers seems to require 4 bytes alignment
477 * of Tx buffers to make Tx checksum offload with custom
478 * checksum generation method work.
480 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
482 * All known controllers seems to have issues on Rx checksum
483 * offload for fragmented IP datagrams.
485 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
487 * Don't use Tx CMB. It is known to cause RRS update failure
488 * under certain circumstances. Typical phenomenon of the
489 * issue would be unexpected sequence number encountered in
492 sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
493 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
494 MASTER_CHIP_REV_SHIFT;
496 device_printf(dev, "PCI device revision : 0x%04x\n",
498 device_printf(dev, "Chip id/revision : 0x%04x\n",
501 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
502 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
504 * Uninitialized hardware returns an invalid chip id/revision
505 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
507 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
508 rxf_len == 0xFFFFFFF) {
509 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO "
510 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev,
515 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len);
517 /* Allocate IRQ resources. */
518 msixc = pci_msix_count(dev);
519 msic = pci_msi_count(dev);
521 device_printf(dev, "MSIX count : %d\n", msixc);
522 device_printf(dev, "MSI count : %d\n", msic);
525 /* Prefer MSIX over MSI. */
526 if (msix_disable == 0 || msi_disable == 0) {
527 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES &&
528 pci_alloc_msix(dev, &msixc) == 0) {
529 if (msic == ALE_MSIX_MESSAGES) {
530 device_printf(dev, "Using %d MSIX messages.\n",
532 sc->ale_flags |= ALE_FLAG_MSIX;
533 sc->ale_irq_spec = ale_irq_spec_msix;
535 pci_release_msi(dev);
537 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 &&
538 msic == ALE_MSI_MESSAGES &&
539 pci_alloc_msi(dev, &msic) == 0) {
540 if (msic == ALE_MSI_MESSAGES) {
541 device_printf(dev, "Using %d MSI messages.\n",
543 sc->ale_flags |= ALE_FLAG_MSI;
544 sc->ale_irq_spec = ale_irq_spec_msi;
546 pci_release_msi(dev);
550 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq);
552 device_printf(dev, "cannot allocate IRQ resources.\n");
556 /* Get DMA parameters from PCIe device control register. */
557 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
558 sc->ale_flags |= ALE_FLAG_PCIE;
559 burst = pci_read_config(dev, i + 0x08, 2);
560 /* Max read request size. */
561 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) <<
562 DMA_CFG_RD_BURST_SHIFT;
563 /* Max payload size. */
564 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) <<
565 DMA_CFG_WR_BURST_SHIFT;
567 device_printf(dev, "Read request size : %d bytes.\n",
568 128 << ((burst >> 12) & 0x07));
569 device_printf(dev, "TLP payload size : %d bytes.\n",
570 128 << ((burst >> 5) & 0x07));
573 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
574 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
577 /* Create device sysctl node. */
580 if ((error = ale_dma_alloc(sc) != 0))
583 /* Load station address. */
586 ifp = sc->ale_ifp = if_alloc(IFT_ETHER);
588 device_printf(dev, "cannot allocate ifnet structure.\n");
594 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
595 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
596 ifp->if_ioctl = ale_ioctl;
597 ifp->if_start = ale_start;
598 ifp->if_init = ale_init;
599 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1;
600 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
601 IFQ_SET_READY(&ifp->if_snd);
602 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4;
603 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO;
604 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
605 sc->ale_flags |= ALE_FLAG_PMCAP;
606 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
608 ifp->if_capenable = ifp->if_capabilities;
610 /* Set up MII bus. */
611 if ((error = mii_phy_probe(dev, &sc->ale_miibus, ale_mediachange,
612 ale_mediastatus)) != 0) {
613 device_printf(dev, "no PHY found!\n");
617 ether_ifattach(ifp, sc->ale_eaddr);
619 /* VLAN capability setup. */
620 ifp->if_capabilities |= IFCAP_VLAN_MTU;
621 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM;
622 ifp->if_capenable = ifp->if_capabilities;
624 /* Tell the upper layer(s) we support long frames. */
625 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
627 /* Create local taskq. */
628 TASK_INIT(&sc->ale_tx_task, 1, ale_tx_task, ifp);
629 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK,
630 taskqueue_thread_enqueue, &sc->ale_tq);
631 if (sc->ale_tq == NULL) {
632 device_printf(dev, "could not create taskqueue.\n");
637 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq",
638 device_get_nameunit(sc->ale_dev));
640 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
641 msic = ALE_MSIX_MESSAGES;
642 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
643 msic = ALE_MSI_MESSAGES;
646 for (i = 0; i < msic; i++) {
647 error = bus_setup_intr(dev, sc->ale_irq[i],
648 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc,
649 &sc->ale_intrhand[i]);
654 device_printf(dev, "could not set up interrupt handler.\n");
655 taskqueue_free(sc->ale_tq);
669 ale_detach(device_t dev)
671 struct ale_softc *sc;
675 sc = device_get_softc(dev);
678 if (device_is_attached(dev)) {
680 sc->ale_flags |= ALE_FLAG_DETACH;
683 callout_drain(&sc->ale_tick_ch);
684 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
685 taskqueue_drain(sc->ale_tq, &sc->ale_tx_task);
686 taskqueue_drain(taskqueue_swi, &sc->ale_link_task);
690 if (sc->ale_tq != NULL) {
691 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
692 taskqueue_free(sc->ale_tq);
696 if (sc->ale_miibus != NULL) {
697 device_delete_child(dev, sc->ale_miibus);
698 sc->ale_miibus = NULL;
700 bus_generic_detach(dev);
708 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
709 msic = ALE_MSIX_MESSAGES;
710 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
711 msic = ALE_MSI_MESSAGES;
714 for (i = 0; i < msic; i++) {
715 if (sc->ale_intrhand[i] != NULL) {
716 bus_teardown_intr(dev, sc->ale_irq[i],
717 sc->ale_intrhand[i]);
718 sc->ale_intrhand[i] = NULL;
722 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq);
723 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0)
724 pci_release_msi(dev);
725 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res);
726 mtx_destroy(&sc->ale_mtx);
731 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
732 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
734 #if __FreeBSD_version > 800000
735 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
736 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
738 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
739 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
743 ale_sysctl_node(struct ale_softc *sc)
745 struct sysctl_ctx_list *ctx;
746 struct sysctl_oid_list *child, *parent;
747 struct sysctl_oid *tree;
748 struct ale_hw_stats *stats;
751 stats = &sc->ale_stats;
752 ctx = device_get_sysctl_ctx(sc->ale_dev);
753 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev));
755 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
756 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0,
757 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation");
758 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
759 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0,
760 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation");
761 /* Pull in device tunables. */
762 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
763 error = resource_int_value(device_get_name(sc->ale_dev),
764 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod);
766 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN ||
767 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) {
768 device_printf(sc->ale_dev, "int_rx_mod value out of "
769 "range; using default: %d\n",
770 ALE_IM_RX_TIMER_DEFAULT);
771 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
774 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
775 error = resource_int_value(device_get_name(sc->ale_dev),
776 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod);
778 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN ||
779 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) {
780 device_printf(sc->ale_dev, "int_tx_mod value out of "
781 "range; using default: %d\n",
782 ALE_IM_TX_TIMER_DEFAULT);
783 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
786 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
787 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0,
788 sysctl_hw_ale_proc_limit, "I",
789 "max number of Rx events to process");
790 /* Pull in device tunables. */
791 sc->ale_process_limit = ALE_PROC_DEFAULT;
792 error = resource_int_value(device_get_name(sc->ale_dev),
793 device_get_unit(sc->ale_dev), "process_limit",
794 &sc->ale_process_limit);
796 if (sc->ale_process_limit < ALE_PROC_MIN ||
797 sc->ale_process_limit > ALE_PROC_MAX) {
798 device_printf(sc->ale_dev,
799 "process_limit value out of range; "
800 "using default: %d\n", ALE_PROC_DEFAULT);
801 sc->ale_process_limit = ALE_PROC_DEFAULT;
805 /* Misc statistics. */
806 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq",
807 &stats->reset_brk_seq,
808 "Controller resets due to broken Rx sequnce number");
810 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
811 NULL, "ATE statistics");
812 parent = SYSCTL_CHILDREN(tree);
815 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
816 NULL, "Rx MAC statistics");
817 child = SYSCTL_CHILDREN(tree);
818 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
819 &stats->rx_frames, "Good frames");
820 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
821 &stats->rx_bcast_frames, "Good broadcast frames");
822 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
823 &stats->rx_mcast_frames, "Good multicast frames");
824 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
825 &stats->rx_pause_frames, "Pause control frames");
826 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
827 &stats->rx_control_frames, "Control frames");
828 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
829 &stats->rx_crcerrs, "CRC errors");
830 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
831 &stats->rx_lenerrs, "Frames with length mismatched");
832 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
833 &stats->rx_bytes, "Good octets");
834 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
835 &stats->rx_bcast_bytes, "Good broadcast octets");
836 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
837 &stats->rx_mcast_bytes, "Good multicast octets");
838 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts",
839 &stats->rx_runts, "Too short frames");
840 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments",
841 &stats->rx_fragments, "Fragmented frames");
842 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
843 &stats->rx_pkts_64, "64 bytes frames");
844 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
845 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
846 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
847 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
848 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
849 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
850 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
851 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
852 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
853 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
854 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
855 &stats->rx_pkts_1519_max, "1519 to max frames");
856 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
857 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
858 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
859 &stats->rx_fifo_oflows, "FIFO overflows");
860 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
861 &stats->rx_rrs_errs, "Return status write-back errors");
862 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
863 &stats->rx_alignerrs, "Alignment errors");
864 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered",
865 &stats->rx_pkts_filtered,
866 "Frames dropped due to address filtering");
869 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
870 NULL, "Tx MAC statistics");
871 child = SYSCTL_CHILDREN(tree);
872 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
873 &stats->tx_frames, "Good frames");
874 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
875 &stats->tx_bcast_frames, "Good broadcast frames");
876 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
877 &stats->tx_mcast_frames, "Good multicast frames");
878 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
879 &stats->tx_pause_frames, "Pause control frames");
880 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
881 &stats->tx_control_frames, "Control frames");
882 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
883 &stats->tx_excess_defer, "Frames with excessive derferrals");
884 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers",
885 &stats->tx_excess_defer, "Frames with derferrals");
886 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
887 &stats->tx_bytes, "Good octets");
888 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
889 &stats->tx_bcast_bytes, "Good broadcast octets");
890 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
891 &stats->tx_mcast_bytes, "Good multicast octets");
892 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
893 &stats->tx_pkts_64, "64 bytes frames");
894 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
895 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
896 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
897 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
898 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
899 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
900 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
901 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
902 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
903 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
904 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
905 &stats->tx_pkts_1519_max, "1519 to max frames");
906 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
907 &stats->tx_single_colls, "Single collisions");
908 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
909 &stats->tx_multi_colls, "Multiple collisions");
910 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
911 &stats->tx_late_colls, "Late collisions");
912 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
913 &stats->tx_excess_colls, "Excessive collisions");
914 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort",
915 &stats->tx_abort, "Aborted frames due to Excessive collisions");
916 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
917 &stats->tx_underrun, "FIFO underruns");
918 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
919 &stats->tx_desc_underrun, "Descriptor write-back errors");
920 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
921 &stats->tx_lenerrs, "Frames with length mismatched");
922 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
923 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
926 #undef ALE_SYSCTL_STAT_ADD32
927 #undef ALE_SYSCTL_STAT_ADD64
929 struct ale_dmamap_arg {
930 bus_addr_t ale_busaddr;
934 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
936 struct ale_dmamap_arg *ctx;
941 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
943 ctx = (struct ale_dmamap_arg *)arg;
944 ctx->ale_busaddr = segs[0].ds_addr;
948 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register
949 * which specifies high address region of DMA blocks. Therefore these
950 * blocks should have the same high address of given 4GB address
951 * space(i.e. crossing 4GB boundary is not allowed).
954 ale_check_boundary(struct ale_softc *sc)
956 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end;
957 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end;
959 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr +
961 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr +
963 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ;
964 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ;
965 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ;
966 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ;
968 if ((ALE_ADDR_HI(tx_ring_end) !=
969 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) ||
970 (ALE_ADDR_HI(rx_page_end[0]) !=
971 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) ||
972 (ALE_ADDR_HI(rx_page_end[1]) !=
973 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) ||
974 (ALE_ADDR_HI(tx_cmb_end) !=
975 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) ||
976 (ALE_ADDR_HI(rx_cmb_end[0]) !=
977 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) ||
978 (ALE_ADDR_HI(rx_cmb_end[1]) !=
979 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr)))
982 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) ||
983 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) ||
984 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) ||
985 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) ||
986 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end)))
993 ale_dma_alloc(struct ale_softc *sc)
995 struct ale_txdesc *txd;
997 struct ale_dmamap_arg ctx;
998 int error, guard_size, i;
1000 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
1001 guard_size = ALE_JUMBO_FRAMELEN;
1003 guard_size = ALE_MAX_FRAMELEN;
1004 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
1006 lowaddr = BUS_SPACE_MAXADDR;
1008 /* Create parent DMA tag. */
1009 error = bus_dma_tag_create(
1010 bus_get_dma_tag(sc->ale_dev), /* parent */
1011 1, 0, /* alignment, boundary */
1012 lowaddr, /* lowaddr */
1013 BUS_SPACE_MAXADDR, /* highaddr */
1014 NULL, NULL, /* filter, filterarg */
1015 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1017 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1019 NULL, NULL, /* lockfunc, lockarg */
1020 &sc->ale_cdata.ale_parent_tag);
1022 device_printf(sc->ale_dev,
1023 "could not create parent DMA tag.\n");
1027 /* Create DMA tag for Tx descriptor ring. */
1028 error = bus_dma_tag_create(
1029 sc->ale_cdata.ale_parent_tag, /* parent */
1030 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */
1031 BUS_SPACE_MAXADDR, /* lowaddr */
1032 BUS_SPACE_MAXADDR, /* highaddr */
1033 NULL, NULL, /* filter, filterarg */
1034 ALE_TX_RING_SZ, /* maxsize */
1036 ALE_TX_RING_SZ, /* maxsegsize */
1038 NULL, NULL, /* lockfunc, lockarg */
1039 &sc->ale_cdata.ale_tx_ring_tag);
1041 device_printf(sc->ale_dev,
1042 "could not create Tx ring DMA tag.\n");
1046 /* Create DMA tag for Rx pages. */
1047 for (i = 0; i < ALE_RX_PAGES; i++) {
1048 error = bus_dma_tag_create(
1049 sc->ale_cdata.ale_parent_tag, /* parent */
1050 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */
1051 BUS_SPACE_MAXADDR, /* lowaddr */
1052 BUS_SPACE_MAXADDR, /* highaddr */
1053 NULL, NULL, /* filter, filterarg */
1054 sc->ale_pagesize, /* maxsize */
1056 sc->ale_pagesize, /* maxsegsize */
1058 NULL, NULL, /* lockfunc, lockarg */
1059 &sc->ale_cdata.ale_rx_page[i].page_tag);
1061 device_printf(sc->ale_dev,
1062 "could not create Rx page %d DMA tag.\n", i);
1067 /* Create DMA tag for Tx coalescing message block. */
1068 error = bus_dma_tag_create(
1069 sc->ale_cdata.ale_parent_tag, /* parent */
1070 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1071 BUS_SPACE_MAXADDR, /* lowaddr */
1072 BUS_SPACE_MAXADDR, /* highaddr */
1073 NULL, NULL, /* filter, filterarg */
1074 ALE_TX_CMB_SZ, /* maxsize */
1076 ALE_TX_CMB_SZ, /* maxsegsize */
1078 NULL, NULL, /* lockfunc, lockarg */
1079 &sc->ale_cdata.ale_tx_cmb_tag);
1081 device_printf(sc->ale_dev,
1082 "could not create Tx CMB DMA tag.\n");
1086 /* Create DMA tag for Rx coalescing message block. */
1087 for (i = 0; i < ALE_RX_PAGES; i++) {
1088 error = bus_dma_tag_create(
1089 sc->ale_cdata.ale_parent_tag, /* parent */
1090 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1091 BUS_SPACE_MAXADDR, /* lowaddr */
1092 BUS_SPACE_MAXADDR, /* highaddr */
1093 NULL, NULL, /* filter, filterarg */
1094 ALE_RX_CMB_SZ, /* maxsize */
1096 ALE_RX_CMB_SZ, /* maxsegsize */
1098 NULL, NULL, /* lockfunc, lockarg */
1099 &sc->ale_cdata.ale_rx_page[i].cmb_tag);
1101 device_printf(sc->ale_dev,
1102 "could not create Rx page %d CMB DMA tag.\n", i);
1107 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1108 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag,
1109 (void **)&sc->ale_cdata.ale_tx_ring,
1110 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1111 &sc->ale_cdata.ale_tx_ring_map);
1113 device_printf(sc->ale_dev,
1114 "could not allocate DMA'able memory for Tx ring.\n");
1117 ctx.ale_busaddr = 0;
1118 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag,
1119 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring,
1120 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0);
1121 if (error != 0 || ctx.ale_busaddr == 0) {
1122 device_printf(sc->ale_dev,
1123 "could not load DMA'able memory for Tx ring.\n");
1126 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr;
1129 for (i = 0; i < ALE_RX_PAGES; i++) {
1130 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag,
1131 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr,
1132 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1133 &sc->ale_cdata.ale_rx_page[i].page_map);
1135 device_printf(sc->ale_dev,
1136 "could not allocate DMA'able memory for "
1137 "Rx page %d.\n", i);
1140 ctx.ale_busaddr = 0;
1141 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag,
1142 sc->ale_cdata.ale_rx_page[i].page_map,
1143 sc->ale_cdata.ale_rx_page[i].page_addr,
1144 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0);
1145 if (error != 0 || ctx.ale_busaddr == 0) {
1146 device_printf(sc->ale_dev,
1147 "could not load DMA'able memory for "
1148 "Rx page %d.\n", i);
1151 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr;
1155 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag,
1156 (void **)&sc->ale_cdata.ale_tx_cmb,
1157 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1158 &sc->ale_cdata.ale_tx_cmb_map);
1160 device_printf(sc->ale_dev,
1161 "could not allocate DMA'able memory for Tx CMB.\n");
1164 ctx.ale_busaddr = 0;
1165 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag,
1166 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb,
1167 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1168 if (error != 0 || ctx.ale_busaddr == 0) {
1169 device_printf(sc->ale_dev,
1170 "could not load DMA'able memory for Tx CMB.\n");
1173 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr;
1176 for (i = 0; i < ALE_RX_PAGES; i++) {
1177 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1178 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
1179 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1180 &sc->ale_cdata.ale_rx_page[i].cmb_map);
1182 device_printf(sc->ale_dev, "could not allocate "
1183 "DMA'able memory for Rx page %d CMB.\n", i);
1186 ctx.ale_busaddr = 0;
1187 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1188 sc->ale_cdata.ale_rx_page[i].cmb_map,
1189 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1190 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1191 if (error != 0 || ctx.ale_busaddr == 0) {
1192 device_printf(sc->ale_dev, "could not load DMA'able "
1193 "memory for Rx page %d CMB.\n", i);
1196 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr;
1200 * Tx descriptors/RXF0/CMB DMA blocks share the same
1201 * high address region of 64bit DMA address space.
1203 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1204 (error = ale_check_boundary(sc)) != 0) {
1205 device_printf(sc->ale_dev, "4GB boundary crossed, "
1206 "switching to 32bit DMA addressing mode.\n");
1209 * Limit max allowable DMA address space to 32bit
1212 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1217 * Create Tx buffer parent tag.
1218 * AR81xx allows 64bit DMA addressing of Tx buffers so it
1219 * needs separate parent DMA tag as parent DMA address space
1220 * could be restricted to be within 32bit address space by
1221 * 4GB boundary crossing.
1223 error = bus_dma_tag_create(
1224 bus_get_dma_tag(sc->ale_dev), /* parent */
1225 1, 0, /* alignment, boundary */
1226 BUS_SPACE_MAXADDR, /* lowaddr */
1227 BUS_SPACE_MAXADDR, /* highaddr */
1228 NULL, NULL, /* filter, filterarg */
1229 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1231 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1233 NULL, NULL, /* lockfunc, lockarg */
1234 &sc->ale_cdata.ale_buffer_tag);
1236 device_printf(sc->ale_dev,
1237 "could not create parent buffer DMA tag.\n");
1241 /* Create DMA tag for Tx buffers. */
1242 error = bus_dma_tag_create(
1243 sc->ale_cdata.ale_buffer_tag, /* parent */
1244 1, 0, /* alignment, boundary */
1245 BUS_SPACE_MAXADDR, /* lowaddr */
1246 BUS_SPACE_MAXADDR, /* highaddr */
1247 NULL, NULL, /* filter, filterarg */
1248 ALE_TSO_MAXSIZE, /* maxsize */
1249 ALE_MAXTXSEGS, /* nsegments */
1250 ALE_TSO_MAXSEGSIZE, /* maxsegsize */
1252 NULL, NULL, /* lockfunc, lockarg */
1253 &sc->ale_cdata.ale_tx_tag);
1255 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n");
1259 /* Create DMA maps for Tx buffers. */
1260 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1261 txd = &sc->ale_cdata.ale_txdesc[i];
1263 txd->tx_dmamap = NULL;
1264 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0,
1267 device_printf(sc->ale_dev,
1268 "could not create Tx dmamap.\n");
1278 ale_dma_free(struct ale_softc *sc)
1280 struct ale_txdesc *txd;
1284 if (sc->ale_cdata.ale_tx_tag != NULL) {
1285 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1286 txd = &sc->ale_cdata.ale_txdesc[i];
1287 if (txd->tx_dmamap != NULL) {
1288 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag,
1290 txd->tx_dmamap = NULL;
1293 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag);
1294 sc->ale_cdata.ale_tx_tag = NULL;
1296 /* Tx descriptor ring. */
1297 if (sc->ale_cdata.ale_tx_ring_tag != NULL) {
1298 if (sc->ale_cdata.ale_tx_ring_map != NULL)
1299 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag,
1300 sc->ale_cdata.ale_tx_ring_map);
1301 if (sc->ale_cdata.ale_tx_ring_map != NULL &&
1302 sc->ale_cdata.ale_tx_ring != NULL)
1303 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag,
1304 sc->ale_cdata.ale_tx_ring,
1305 sc->ale_cdata.ale_tx_ring_map);
1306 sc->ale_cdata.ale_tx_ring = NULL;
1307 sc->ale_cdata.ale_tx_ring_map = NULL;
1308 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag);
1309 sc->ale_cdata.ale_tx_ring_tag = NULL;
1311 /* Rx page block. */
1312 for (i = 0; i < ALE_RX_PAGES; i++) {
1313 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) {
1314 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL)
1316 sc->ale_cdata.ale_rx_page[i].page_tag,
1317 sc->ale_cdata.ale_rx_page[i].page_map);
1318 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL &&
1319 sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
1321 sc->ale_cdata.ale_rx_page[i].page_tag,
1322 sc->ale_cdata.ale_rx_page[i].page_addr,
1323 sc->ale_cdata.ale_rx_page[i].page_map);
1324 sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
1325 sc->ale_cdata.ale_rx_page[i].page_map = NULL;
1326 bus_dma_tag_destroy(
1327 sc->ale_cdata.ale_rx_page[i].page_tag);
1328 sc->ale_cdata.ale_rx_page[i].page_tag = NULL;
1332 for (i = 0; i < ALE_RX_PAGES; i++) {
1333 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) {
1334 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL)
1336 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1337 sc->ale_cdata.ale_rx_page[i].cmb_map);
1338 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL &&
1339 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
1341 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1342 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1343 sc->ale_cdata.ale_rx_page[i].cmb_map);
1344 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
1345 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL;
1346 bus_dma_tag_destroy(
1347 sc->ale_cdata.ale_rx_page[i].cmb_tag);
1348 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL;
1352 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) {
1353 if (sc->ale_cdata.ale_tx_cmb_map != NULL)
1354 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag,
1355 sc->ale_cdata.ale_tx_cmb_map);
1356 if (sc->ale_cdata.ale_tx_cmb_map != NULL &&
1357 sc->ale_cdata.ale_tx_cmb != NULL)
1358 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag,
1359 sc->ale_cdata.ale_tx_cmb,
1360 sc->ale_cdata.ale_tx_cmb_map);
1361 sc->ale_cdata.ale_tx_cmb = NULL;
1362 sc->ale_cdata.ale_tx_cmb_map = NULL;
1363 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag);
1364 sc->ale_cdata.ale_tx_cmb_tag = NULL;
1366 if (sc->ale_cdata.ale_buffer_tag != NULL) {
1367 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag);
1368 sc->ale_cdata.ale_buffer_tag = NULL;
1370 if (sc->ale_cdata.ale_parent_tag != NULL) {
1371 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag);
1372 sc->ale_cdata.ale_parent_tag = NULL;
1377 ale_shutdown(device_t dev)
1380 return (ale_suspend(dev));
1384 * Note, this driver resets the link speed to 10/100Mbps by
1385 * restarting auto-negotiation in suspend/shutdown phase but we
1386 * don't know whether that auto-negotiation would succeed or not
1387 * as driver has no control after powering off/suspend operation.
1388 * If the renegotiation fail WOL may not work. Running at 1Gbps
1389 * will draw more power than 375mA at 3.3V which is specified in
1390 * PCI specification and that would result in complete
1391 * shutdowning power to ethernet controller.
1394 * Save current negotiated media speed/duplex/flow-control to
1395 * softc and restore the same link again after resuming. PHY
1396 * handling such as power down/resetting to 100Mbps may be better
1397 * handled in suspend method in phy driver.
1400 ale_setlinkspeed(struct ale_softc *sc)
1402 struct mii_data *mii;
1405 mii = device_get_softc(sc->ale_miibus);
1408 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1409 (IFM_ACTIVE | IFM_AVALID)) {
1410 switch IFM_SUBTYPE(mii->mii_media_active) {
1421 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0);
1422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1423 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1425 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1429 * Poll link state until ale(4) get a 10/100Mbps link.
1431 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1433 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1434 == (IFM_ACTIVE | IFM_AVALID)) {
1435 switch (IFM_SUBTYPE(
1436 mii->mii_media_active)) {
1446 pause("alelnk", hz);
1449 if (i == MII_ANEGTICKS_GIGE)
1450 device_printf(sc->ale_dev,
1451 "establishing a link failed, WOL may not work!");
1454 * No link, force MAC to have 100Mbps, full-duplex link.
1455 * This is the last resort and may/may not work.
1457 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1458 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1463 ale_setwol(struct ale_softc *sc)
1470 ALE_LOCK_ASSERT(sc);
1472 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1474 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1475 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1476 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1477 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1478 /* Force PHY power down. */
1479 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1480 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1481 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON |
1482 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ |
1483 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW);
1488 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1489 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
1490 ale_setlinkspeed(sc);
1494 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1495 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1496 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1497 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1498 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1500 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1501 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1502 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1503 reg |= MAC_CFG_RX_ENB;
1504 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1506 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1507 /* WOL disabled, PHY power down. */
1508 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1509 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1510 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1511 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1512 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1513 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
1514 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS |
1515 GPHY_CTRL_PWDOWN_HW);
1518 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2);
1519 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1520 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1521 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1522 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1526 ale_suspend(device_t dev)
1528 struct ale_softc *sc;
1530 sc = device_get_softc(dev);
1541 ale_resume(device_t dev)
1543 struct ale_softc *sc;
1546 uint16_t cmd, pmstat;
1548 sc = device_get_softc(dev);
1552 * Clear INTx emulation disable for hardwares that
1553 * is set in resume event. From Linux.
1555 cmd = pci_read_config(sc->ale_dev, PCIR_COMMAND, 2);
1556 if ((cmd & 0x0400) != 0) {
1558 pci_write_config(sc->ale_dev, PCIR_COMMAND, cmd, 2);
1560 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1561 /* Disable PME and clear PME status. */
1562 pmstat = pci_read_config(sc->ale_dev,
1563 pmc + PCIR_POWER_STATUS, 2);
1564 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1565 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1566 pci_write_config(sc->ale_dev,
1567 pmc + PCIR_POWER_STATUS, pmstat, 2);
1573 if ((ifp->if_flags & IFF_UP) != 0) {
1574 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1575 ale_init_locked(sc);
1583 ale_encap(struct ale_softc *sc, struct mbuf **m_head)
1585 struct ale_txdesc *txd, *txd_last;
1586 struct tx_desc *desc;
1590 bus_dma_segment_t txsegs[ALE_MAXTXSEGS];
1592 uint32_t cflags, ip_off, poff, vtag;
1593 int error, i, nsegs, prod, si;
1595 ALE_LOCK_ASSERT(sc);
1597 M_ASSERTPKTHDR((*m_head));
1604 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1606 * AR81xx requires offset of TCP/UDP payload in its Tx
1607 * descriptor to perform hardware Tx checksum offload.
1608 * Additionally, TSO requires IP/TCP header size and
1609 * modification of IP/TCP header in order to make TSO
1610 * engine work. This kind of operation takes many CPU
1611 * cycles on FreeBSD so fast host CPU is required to
1612 * get smooth TSO performance.
1614 struct ether_header *eh;
1616 if (M_WRITABLE(m) == 0) {
1617 /* Get a writable copy. */
1618 m = m_dup(*m_head, M_DONTWAIT);
1619 /* Release original mbufs. */
1629 * Buggy-controller requires 4 byte aligned Tx buffer
1630 * to make custom checksum offload work.
1632 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 &&
1633 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 &&
1634 (mtod(m, intptr_t) & 3) != 0) {
1635 m = m_defrag(*m_head, M_DONTWAIT);
1643 ip_off = sizeof(struct ether_header);
1644 m = m_pullup(m, ip_off);
1649 eh = mtod(m, struct ether_header *);
1651 * Check if hardware VLAN insertion is off.
1652 * Additional check for LLC/SNAP frame?
1654 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1655 ip_off = sizeof(struct ether_vlan_header);
1656 m = m_pullup(m, ip_off);
1662 m = m_pullup(m, ip_off + sizeof(struct ip));
1667 ip = (struct ip *)(mtod(m, char *) + ip_off);
1668 poff = ip_off + (ip->ip_hl << 2);
1669 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1672 * AR81xx requires the first descriptor should
1673 * not include any TCP playload for TSO case.
1674 * (i.e. ethernet header + IP + TCP header only)
1675 * m_pullup(9) above will ensure this too.
1676 * However it's not correct if the first mbuf
1677 * of the chain does not use cluster.
1679 m = m_pullup(m, poff + sizeof(struct tcphdr));
1684 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1686 * AR81xx requires IP/TCP header size and offset as
1687 * well as TCP pseudo checksum which complicates
1688 * TSO configuration. I guess this comes from the
1689 * adherence to Microsoft NDIS Large Send
1690 * specification which requires insertion of
1691 * pseudo checksum by upper stack. The pseudo
1692 * checksum that NDIS refers to doesn't include
1693 * TCP payload length so ale(4) should recompute
1694 * the pseudo checksum here. Hopefully this wouldn't
1695 * be much burden on modern CPUs.
1696 * Reset IP checksum and recompute TCP pseudo
1697 * checksum as NDIS specification said.
1700 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1701 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1706 si = prod = sc->ale_cdata.ale_tx_prod;
1707 txd = &sc->ale_cdata.ale_txdesc[prod];
1709 map = txd->tx_dmamap;
1711 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1712 *m_head, txsegs, &nsegs, 0);
1713 if (error == EFBIG) {
1714 m = m_collapse(*m_head, M_DONTWAIT, ALE_MAXTXSEGS);
1721 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1722 *m_head, txsegs, &nsegs, 0);
1728 } else if (error != 0)
1736 /* Check descriptor overrun. */
1737 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) {
1738 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map);
1741 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE);
1744 /* Configure Tx checksum offload. */
1745 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
1747 * AR81xx supports Tx custom checksum offload feature
1748 * that offloads single 16bit checksum computation.
1749 * So you can choose one among IP, TCP and UDP.
1750 * Normally driver sets checksum start/insertion
1751 * position from the information of TCP/UDP frame as
1752 * TCP/UDP checksum takes more time than that of IP.
1753 * However it seems that custom checksum offload
1754 * requires 4 bytes aligned Tx buffers due to hardware
1756 * AR81xx also supports explicit Tx checksum computation
1757 * if it is told that the size of IP header and TCP
1758 * header(for UDP, the header size does not matter
1759 * because it's fixed length). However with this scheme
1760 * TSO does not work so you have to choose one either
1761 * TSO or explicit Tx checksum offload. I chosen TSO
1762 * plus custom checksum offload with work-around which
1763 * will cover most common usage for this consumer
1764 * ethernet controller. The work-around takes a lot of
1765 * CPU cycles if Tx buffer is not aligned on 4 bytes
1768 cflags |= ALE_TD_CXSUM;
1769 /* Set checksum start offset. */
1770 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
1771 /* Set checksum insertion position of TCP/UDP. */
1772 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1773 ALE_TD_CSUM_XSUMOFFSET_SHIFT);
1776 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1777 /* Request TSO and set MSS. */
1778 cflags |= ALE_TD_TSO;
1779 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT);
1780 /* Set IP/TCP header size. */
1781 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT;
1782 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT;
1785 /* Configure VLAN hardware tag insertion. */
1786 if ((m->m_flags & M_VLANTAG) != 0) {
1787 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1788 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
1789 cflags |= ALE_TD_INSERT_VLAN_TAG;
1793 for (i = 0; i < nsegs; i++) {
1794 desc = &sc->ale_cdata.ale_tx_ring[prod];
1795 desc->addr = htole64(txsegs[i].ds_addr);
1796 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag);
1797 desc->flags = htole32(cflags);
1798 sc->ale_cdata.ale_tx_cnt++;
1799 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1801 /* Update producer index. */
1802 sc->ale_cdata.ale_tx_prod = prod;
1803 /* Set TSO header on the first descriptor. */
1804 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1805 desc = &sc->ale_cdata.ale_tx_ring[si];
1806 desc->flags |= htole32(ALE_TD_TSO_HDR);
1809 /* Finally set EOP on the last descriptor. */
1810 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
1811 desc = &sc->ale_cdata.ale_tx_ring[prod];
1812 desc->flags |= htole32(ALE_TD_EOP);
1814 /* Swap dmamap of the first and the last. */
1815 txd = &sc->ale_cdata.ale_txdesc[prod];
1816 map = txd_last->tx_dmamap;
1817 txd_last->tx_dmamap = txd->tx_dmamap;
1818 txd->tx_dmamap = map;
1821 /* Sync descriptors. */
1822 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
1823 sc->ale_cdata.ale_tx_ring_map,
1824 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1830 ale_tx_task(void *arg, int pending)
1834 ifp = (struct ifnet *)arg;
1839 ale_start(struct ifnet *ifp)
1841 struct ale_softc *sc;
1842 struct mbuf *m_head;
1849 /* Reclaim transmitted frames. */
1850 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
1853 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1854 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) {
1859 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1860 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1864 * Pack the data into the transmit ring. If we
1865 * don't have room, set the OACTIVE flag and wait
1866 * for the NIC to drain the ring.
1868 if (ale_encap(sc, &m_head)) {
1871 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1872 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1878 * If there's a BPF listener, bounce a copy of this frame
1881 ETHER_BPF_MTAP(ifp, m_head);
1886 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1887 sc->ale_cdata.ale_tx_prod);
1888 /* Set a timeout in case the chip goes out to lunch. */
1889 sc->ale_watchdog_timer = ALE_TX_TIMEOUT;
1896 ale_watchdog(struct ale_softc *sc)
1900 ALE_LOCK_ASSERT(sc);
1902 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer)
1906 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1907 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n");
1909 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1910 ale_init_locked(sc);
1913 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n");
1915 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1916 ale_init_locked(sc);
1917 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1918 taskqueue_enqueue(sc->ale_tq, &sc->ale_tx_task);
1922 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1924 struct ale_softc *sc;
1926 struct mii_data *mii;
1930 ifr = (struct ifreq *)data;
1934 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU ||
1935 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 &&
1936 ifr->ifr_mtu > ETHERMTU))
1938 else if (ifp->if_mtu != ifr->ifr_mtu) {
1940 ifp->if_mtu = ifr->ifr_mtu;
1941 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1942 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1943 ale_init_locked(sc);
1950 if ((ifp->if_flags & IFF_UP) != 0) {
1951 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1952 if (((ifp->if_flags ^ sc->ale_if_flags)
1953 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1956 if ((sc->ale_flags & ALE_FLAG_DETACH) == 0)
1957 ale_init_locked(sc);
1960 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1963 sc->ale_if_flags = ifp->if_flags;
1969 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1975 mii = device_get_softc(sc->ale_miibus);
1976 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1980 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1981 if ((mask & IFCAP_TXCSUM) != 0 &&
1982 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1983 ifp->if_capenable ^= IFCAP_TXCSUM;
1984 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1985 ifp->if_hwassist |= ALE_CSUM_FEATURES;
1987 ifp->if_hwassist &= ~ALE_CSUM_FEATURES;
1989 if ((mask & IFCAP_RXCSUM) != 0 &&
1990 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
1991 ifp->if_capenable ^= IFCAP_RXCSUM;
1992 if ((mask & IFCAP_TSO4) != 0 &&
1993 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
1994 ifp->if_capenable ^= IFCAP_TSO4;
1995 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
1996 ifp->if_hwassist |= CSUM_TSO;
1998 ifp->if_hwassist &= ~CSUM_TSO;
2001 if ((mask & IFCAP_WOL_MCAST) != 0 &&
2002 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
2003 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2004 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2005 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2006 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2008 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2009 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2010 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2013 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2014 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2015 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2016 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2017 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2018 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2020 * VLAN hardware tagging is required to do checksum
2021 * offload or TSO on VLAN interface. Checksum offload
2022 * on VLAN interface also requires hardware checksum
2023 * offload of parent interface.
2025 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0)
2026 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM;
2027 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2028 ifp->if_capenable &=
2029 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
2031 VLAN_CAPABILITIES(ifp);
2034 error = ether_ioctl(ifp, cmd, data);
2042 ale_mac_config(struct ale_softc *sc)
2044 struct mii_data *mii;
2047 ALE_LOCK_ASSERT(sc);
2049 mii = device_get_softc(sc->ale_miibus);
2050 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2051 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2052 MAC_CFG_SPEED_MASK);
2053 /* Reprogram MAC with resolved speed/duplex. */
2054 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2057 reg |= MAC_CFG_SPEED_10_100;
2060 reg |= MAC_CFG_SPEED_1000;
2063 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2064 reg |= MAC_CFG_FULL_DUPLEX;
2066 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2067 reg |= MAC_CFG_TX_FC;
2068 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2069 reg |= MAC_CFG_RX_FC;
2072 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2076 ale_link_task(void *arg, int pending)
2078 struct ale_softc *sc;
2079 struct mii_data *mii;
2083 sc = (struct ale_softc *)arg;
2086 mii = device_get_softc(sc->ale_miibus);
2088 if (mii == NULL || ifp == NULL ||
2089 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2094 sc->ale_flags &= ~ALE_FLAG_LINK;
2095 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2096 (IFM_ACTIVE | IFM_AVALID)) {
2097 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2100 sc->ale_flags |= ALE_FLAG_LINK;
2103 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
2104 sc->ale_flags |= ALE_FLAG_LINK;
2111 /* Stop Rx/Tx MACs. */
2114 /* Program MACs with resolved speed/duplex/flow-control. */
2115 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
2117 /* Reenable Tx/Rx MACs. */
2118 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2119 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2120 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2127 ale_stats_clear(struct ale_softc *sc)
2133 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2134 CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2135 i += sizeof(uint32_t);
2137 /* Read Tx statistics. */
2138 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2139 CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2140 i += sizeof(uint32_t);
2145 ale_stats_update(struct ale_softc *sc)
2147 struct ale_hw_stats *stat;
2148 struct smb sb, *smb;
2153 ALE_LOCK_ASSERT(sc);
2156 stat = &sc->ale_stats;
2159 /* Read Rx statistics. */
2160 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2161 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2162 i += sizeof(uint32_t);
2164 /* Read Tx statistics. */
2165 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2166 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2167 i += sizeof(uint32_t);
2171 stat->rx_frames += smb->rx_frames;
2172 stat->rx_bcast_frames += smb->rx_bcast_frames;
2173 stat->rx_mcast_frames += smb->rx_mcast_frames;
2174 stat->rx_pause_frames += smb->rx_pause_frames;
2175 stat->rx_control_frames += smb->rx_control_frames;
2176 stat->rx_crcerrs += smb->rx_crcerrs;
2177 stat->rx_lenerrs += smb->rx_lenerrs;
2178 stat->rx_bytes += smb->rx_bytes;
2179 stat->rx_runts += smb->rx_runts;
2180 stat->rx_fragments += smb->rx_fragments;
2181 stat->rx_pkts_64 += smb->rx_pkts_64;
2182 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2183 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2184 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2185 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2186 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2187 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2188 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2189 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2190 stat->rx_rrs_errs += smb->rx_rrs_errs;
2191 stat->rx_alignerrs += smb->rx_alignerrs;
2192 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2193 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2194 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2197 stat->tx_frames += smb->tx_frames;
2198 stat->tx_bcast_frames += smb->tx_bcast_frames;
2199 stat->tx_mcast_frames += smb->tx_mcast_frames;
2200 stat->tx_pause_frames += smb->tx_pause_frames;
2201 stat->tx_excess_defer += smb->tx_excess_defer;
2202 stat->tx_control_frames += smb->tx_control_frames;
2203 stat->tx_deferred += smb->tx_deferred;
2204 stat->tx_bytes += smb->tx_bytes;
2205 stat->tx_pkts_64 += smb->tx_pkts_64;
2206 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2207 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2208 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2209 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2210 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2211 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2212 stat->tx_single_colls += smb->tx_single_colls;
2213 stat->tx_multi_colls += smb->tx_multi_colls;
2214 stat->tx_late_colls += smb->tx_late_colls;
2215 stat->tx_excess_colls += smb->tx_excess_colls;
2216 stat->tx_abort += smb->tx_abort;
2217 stat->tx_underrun += smb->tx_underrun;
2218 stat->tx_desc_underrun += smb->tx_desc_underrun;
2219 stat->tx_lenerrs += smb->tx_lenerrs;
2220 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2221 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2222 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2224 /* Update counters in ifnet. */
2225 ifp->if_opackets += smb->tx_frames;
2227 ifp->if_collisions += smb->tx_single_colls +
2228 smb->tx_multi_colls * 2 + smb->tx_late_colls +
2229 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
2233 * tx_pkts_truncated counter looks suspicious. It constantly
2234 * increments with no sign of Tx errors. This may indicate
2235 * the counter name is not correct one so I've removed the
2236 * counter in output errors.
2238 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
2241 ifp->if_ipackets += smb->rx_frames;
2243 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
2244 smb->rx_runts + smb->rx_pkts_truncated +
2245 smb->rx_fifo_oflows + smb->rx_rrs_errs +
2252 struct ale_softc *sc;
2255 sc = (struct ale_softc *)arg;
2257 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2258 if ((status & ALE_INTRS) == 0)
2259 return (FILTER_STRAY);
2260 /* Disable interrupts. */
2261 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT);
2262 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2264 return (FILTER_HANDLED);
2268 ale_int_task(void *arg, int pending)
2270 struct ale_softc *sc;
2275 sc = (struct ale_softc *)arg;
2277 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2278 more = atomic_readandclear_int(&sc->ale_morework);
2280 status |= INTR_RX_PKT;
2281 if ((status & ALE_INTRS) == 0)
2284 /* Acknowledge interrupts but still disable interrupts. */
2285 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
2289 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2290 more = ale_rxeof(sc, sc->ale_process_limit);
2292 atomic_set_int(&sc->ale_morework, 1);
2293 else if (more == EIO) {
2295 sc->ale_stats.reset_brk_seq++;
2296 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2297 ale_init_locked(sc);
2302 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2303 if ((status & INTR_DMA_RD_TO_RST) != 0)
2304 device_printf(sc->ale_dev,
2305 "DMA read error! -- resetting\n");
2306 if ((status & INTR_DMA_WR_TO_RST) != 0)
2307 device_printf(sc->ale_dev,
2308 "DMA write error! -- resetting\n");
2310 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2311 ale_init_locked(sc);
2315 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2316 taskqueue_enqueue(sc->ale_tq, &sc->ale_tx_task);
2319 if (more == EAGAIN ||
2320 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) {
2321 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2326 /* Re-enable interrupts. */
2327 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2331 ale_txeof(struct ale_softc *sc)
2334 struct ale_txdesc *txd;
2335 uint32_t cons, prod;
2338 ALE_LOCK_ASSERT(sc);
2342 if (sc->ale_cdata.ale_tx_cnt == 0)
2345 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2346 sc->ale_cdata.ale_tx_ring_map,
2347 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2348 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
2349 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2350 sc->ale_cdata.ale_tx_cmb_map,
2351 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2352 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
2354 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
2355 cons = sc->ale_cdata.ale_tx_cons;
2357 * Go through our Tx list and free mbufs for those
2358 * frames which have been transmitted.
2360 for (prog = 0; cons != prod; prog++,
2361 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
2362 if (sc->ale_cdata.ale_tx_cnt <= 0)
2365 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2366 sc->ale_cdata.ale_tx_cnt--;
2367 txd = &sc->ale_cdata.ale_txdesc[cons];
2368 if (txd->tx_m != NULL) {
2369 /* Reclaim transmitted mbufs. */
2370 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2371 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2372 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2380 sc->ale_cdata.ale_tx_cons = cons;
2382 * Unarm watchdog timer only when there is no pending
2383 * Tx descriptors in queue.
2385 if (sc->ale_cdata.ale_tx_cnt == 0)
2386 sc->ale_watchdog_timer = 0;
2391 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
2392 uint32_t length, uint32_t *prod)
2394 struct ale_rx_page *rx_page;
2397 /* Update consumer position. */
2398 rx_page->cons += roundup(length + sizeof(struct rx_rs),
2400 if (rx_page->cons >= ALE_RX_PAGE_SZ) {
2402 * End of Rx page reached, let hardware reuse
2406 *rx_page->cmb_addr = 0;
2407 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2408 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2409 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
2411 /* Switch to alternate Rx page. */
2412 sc->ale_cdata.ale_rx_curp ^= 1;
2414 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2415 /* Page flipped, sync CMB and Rx page. */
2416 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2417 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2418 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2419 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2420 /* Sync completed, cache updated producer index. */
2421 *prod = *rx_page->cmb_addr;
2427 * It seems that AR81xx controller can compute partial checksum.
2428 * The partial checksum value can be used to accelerate checksum
2429 * computation for fragmented TCP/UDP packets. Upper network stack
2430 * already takes advantage of the partial checksum value in IP
2431 * reassembly stage. But I'm not sure the correctness of the
2432 * partial hardware checksum assistance due to lack of data sheet.
2433 * In addition, the Rx feature of controller that requires copying
2434 * for every frames effectively nullifies one of most nice offload
2435 * capability of controller.
2438 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
2445 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2446 if ((status & ALE_RD_IPCSUM_NOK) == 0)
2447 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2449 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
2450 if (((status & ALE_RD_IPV4_FRAG) == 0) &&
2451 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
2452 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
2453 m->m_pkthdr.csum_flags |=
2454 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2455 m->m_pkthdr.csum_data = 0xffff;
2458 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
2459 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
2460 p = mtod(m, char *);
2462 if ((status & ALE_RD_802_3) != 0)
2463 p += LLC_SNAPFRAMELEN;
2464 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 &&
2465 (status & ALE_RD_VLAN) != 0)
2466 p += ETHER_VLAN_ENCAP_LEN;
2467 ip = (struct ip *)p;
2468 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
2470 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2472 m->m_pkthdr.csum_data = 0xffff;
2476 * Don't mark bad checksum for TCP/UDP frames
2477 * as fragmented frames may always have set
2478 * bad checksummed bit of frame status.
2482 /* Process received frames. */
2484 ale_rxeof(struct ale_softc *sc, int count)
2486 struct ale_rx_page *rx_page;
2490 uint32_t length, prod, seqno, status, vtags;
2494 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2495 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2496 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2497 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2498 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2500 * Don't directly access producer index as hardware may
2501 * update it while Rx handler is in progress. It would
2502 * be even better if there is a way to let hardware
2503 * know how far driver processed its received frames.
2504 * Alternatively, hardware could provide a way to disable
2505 * CMB updates until driver acknowledges the end of CMB
2508 prod = *rx_page->cmb_addr;
2509 for (prog = 0; prog < count; prog++) {
2510 if (rx_page->cons >= prod)
2512 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
2513 seqno = ALE_RX_SEQNO(le32toh(rs->seqno));
2514 if (sc->ale_cdata.ale_rx_seqno != seqno) {
2516 * Normally I believe this should not happen unless
2517 * severe driver bug or corrupted memory. However
2518 * it seems to happen under certain conditions which
2519 * is triggered by abrupt Rx events such as initiation
2520 * of bulk transfer of remote host. It's not easy to
2521 * reproduce this and I doubt it could be related
2522 * with FIFO overflow of hardware or activity of Tx
2523 * CMB updates. I also remember similar behaviour
2524 * seen on RealTek 8139 which uses resembling Rx
2528 device_printf(sc->ale_dev,
2529 "garbled seq: %u, expected: %u -- "
2530 "resetting!\n", seqno,
2531 sc->ale_cdata.ale_rx_seqno);
2534 /* Frame received. */
2535 sc->ale_cdata.ale_rx_seqno++;
2536 length = ALE_RX_BYTES(le32toh(rs->length));
2537 status = le32toh(rs->flags);
2538 if ((status & ALE_RD_ERROR) != 0) {
2540 * We want to pass the following frames to upper
2541 * layer regardless of error status of Rx return
2544 * o IP/TCP/UDP checksum is bad.
2545 * o frame length and protocol specific length
2548 if ((status & (ALE_RD_CRC | ALE_RD_CODE |
2549 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
2550 ALE_RD_TRUNC)) != 0) {
2551 ale_rx_update_page(sc, &rx_page, length, &prod);
2556 * m_devget(9) is major bottle-neck of ale(4)(It comes
2557 * from hardware limitation). For jumbo frames we could
2558 * get a slightly better performance if driver use
2559 * m_getjcl(9) with proper buffer size argument. However
2560 * that would make code more complicated and I don't
2561 * think users would expect good Rx performance numbers
2562 * on these low-end consumer ethernet controller.
2564 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN,
2565 ETHER_ALIGN, ifp, NULL);
2568 ale_rx_update_page(sc, &rx_page, length, &prod);
2571 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2572 (status & ALE_RD_IPV4) != 0)
2573 ale_rxcsum(sc, m, status);
2574 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2575 (status & ALE_RD_VLAN) != 0) {
2576 vtags = ALE_RX_VLAN(le32toh(rs->vtags));
2577 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags);
2578 m->m_flags |= M_VLANTAG;
2581 /* Pass it to upper layer. */
2582 (*ifp->if_input)(ifp, m);
2584 ale_rx_update_page(sc, &rx_page, length, &prod);
2587 return (count > 0 ? 0 : EAGAIN);
2593 struct ale_softc *sc;
2594 struct mii_data *mii;
2596 sc = (struct ale_softc *)arg;
2598 ALE_LOCK_ASSERT(sc);
2600 mii = device_get_softc(sc->ale_miibus);
2602 ale_stats_update(sc);
2604 * Reclaim Tx buffers that have been transferred. It's not
2605 * needed here but it would release allocated mbuf chains
2606 * faster and limit the maximum delay to a hz.
2610 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2614 ale_reset(struct ale_softc *sc)
2619 /* Initialize PCIe module. From Linux. */
2620 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2622 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2623 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2625 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
2629 device_printf(sc->ale_dev, "master reset timeout!\n");
2631 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2632 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2638 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2644 struct ale_softc *sc;
2646 sc = (struct ale_softc *)xsc;
2648 ale_init_locked(sc);
2653 ale_init_locked(struct ale_softc *sc)
2656 struct mii_data *mii;
2657 uint8_t eaddr[ETHER_ADDR_LEN];
2659 uint32_t reg, rxf_hi, rxf_lo;
2661 ALE_LOCK_ASSERT(sc);
2664 mii = device_get_softc(sc->ale_miibus);
2666 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2669 * Cancel any pending I/O.
2673 * Reset the chip to a known state.
2676 /* Initialize Tx descriptors, DMA memory blocks. */
2677 ale_init_rx_pages(sc);
2678 ale_init_tx_ring(sc);
2680 /* Reprogram the station address. */
2681 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2682 CSR_WRITE_4(sc, ALE_PAR0,
2683 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2684 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2686 * Clear WOL status and disable all WOL feature as WOL
2687 * would interfere Rx operation under normal environments.
2689 CSR_READ_4(sc, ALE_WOL_CFG);
2690 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2692 * Set Tx descriptor/RXF0/CMB base addresses. They share
2693 * the same high address part of DMAable region.
2695 paddr = sc->ale_cdata.ale_tx_ring_paddr;
2696 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2697 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2698 CSR_WRITE_4(sc, ALE_TPD_CNT,
2699 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
2700 /* Set Rx page base address, note we use single queue. */
2701 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
2702 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2703 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
2704 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2705 /* Set Tx/Rx CMB addresses. */
2706 paddr = sc->ale_cdata.ale_tx_cmb_paddr;
2707 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2708 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
2709 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2710 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
2711 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2712 /* Mark RXF0 is valid. */
2713 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
2714 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
2716 * No need to initialize RFX1/RXF2/RXF3. We don't use
2720 /* Set Rx page size, excluding guard frame size. */
2721 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2722 /* Tell hardware that we're ready to load DMA blocks. */
2723 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2725 /* Set Rx/Tx interrupt trigger threshold. */
2726 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2727 (4 << INT_TRIG_TX_THRESH_SHIFT));
2730 * Set interrupt trigger timer, its purpose and relation
2731 * with interrupt moderation mechanism is not clear yet.
2733 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2734 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
2735 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
2737 /* Configure interrupt moderation timer. */
2738 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2739 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2740 CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2741 reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2742 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2743 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2744 if (ALE_USECS(sc->ale_int_rx_mod) != 0)
2745 reg |= MASTER_IM_RX_TIMER_ENB;
2746 if (ALE_USECS(sc->ale_int_tx_mod) != 0)
2747 reg |= MASTER_IM_TX_TIMER_ENB;
2748 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2749 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
2751 /* Set Maximum frame size of controller. */
2752 if (ifp->if_mtu < ETHERMTU)
2753 sc->ale_max_frame_size = ETHERMTU;
2755 sc->ale_max_frame_size = ifp->if_mtu;
2756 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2758 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2759 /* Configure IPG/IFG parameters. */
2760 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2761 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
2762 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2763 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2764 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
2765 /* Set parameters for half-duplex media. */
2766 CSR_WRITE_4(sc, ALE_HDPX_CFG,
2767 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2768 HDPX_CFG_LCOL_MASK) |
2769 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2770 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2771 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2772 HDPX_CFG_ABEBT_MASK) |
2773 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2774 HDPX_CFG_JAMIPG_MASK));
2776 /* Configure Tx jumbo frame parameters. */
2777 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2778 if (ifp->if_mtu < ETHERMTU)
2779 reg = sc->ale_max_frame_size;
2780 else if (ifp->if_mtu < 6 * 1024)
2781 reg = (sc->ale_max_frame_size * 2) / 3;
2783 reg = sc->ale_max_frame_size / 2;
2784 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2785 roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2786 TX_JUMBO_THRESH_UNIT_SHIFT);
2788 /* Configure TxQ. */
2789 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2790 << TXQ_CFG_TX_FIFO_BURST_SHIFT;
2791 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2792 TXQ_CFG_TPD_BURST_MASK;
2793 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2795 /* Configure Rx jumbo frame & flow control parameters. */
2796 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2797 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2798 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2799 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2800 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
2801 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
2802 RX_JUMBO_LKAH_MASK));
2803 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2804 rxf_hi = (reg * 7) / 10;
2805 rxf_lo = (reg * 3)/ 10;
2806 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2807 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
2808 RX_FIFO_PAUSE_THRESH_LO_MASK) |
2809 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
2810 RX_FIFO_PAUSE_THRESH_HI_MASK));
2814 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2815 CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2817 /* Configure RxQ. */
2818 CSR_WRITE_4(sc, ALE_RXQ_CFG,
2819 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2821 /* Configure DMA parameters. */
2823 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
2824 reg |= DMA_CFG_TXCMB_ENB;
2825 CSR_WRITE_4(sc, ALE_DMA_CFG,
2826 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
2827 sc->ale_dma_rd_burst | reg |
2828 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
2829 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
2830 DMA_CFG_RD_DELAY_CNT_MASK) |
2831 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
2832 DMA_CFG_WR_DELAY_CNT_MASK));
2835 * Hardware can be configured to issue SMB interrupt based
2836 * on programmed interval. Since there is a callout that is
2837 * invoked for every hz in driver we use that instead of
2838 * relying on periodic SMB interrupt.
2840 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2841 /* Clear MAC statistics. */
2842 ale_stats_clear(sc);
2845 * Configure Tx/Rx MACs.
2846 * - Auto-padding for short frames.
2847 * - Enable CRC generation.
2848 * Actual reconfiguration of MAC for resolved speed/duplex
2849 * is followed after detection of link establishment.
2850 * AR81xx always does checksum computation regardless of
2851 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
2852 * cause Rx handling issue for fragmented IP datagrams due
2855 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2856 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2857 MAC_CFG_PREAMBLE_MASK);
2858 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
2859 reg |= MAC_CFG_SPEED_10_100;
2861 reg |= MAC_CFG_SPEED_1000;
2862 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2864 /* Set up the receive filter. */
2868 /* Acknowledge all pending interrupts and clear it. */
2869 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2870 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2871 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2873 sc->ale_flags &= ~ALE_FLAG_LINK;
2874 /* Switch to the current media. */
2877 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2879 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2880 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2884 ale_stop(struct ale_softc *sc)
2887 struct ale_txdesc *txd;
2891 ALE_LOCK_ASSERT(sc);
2893 * Mark the interface down and cancel the watchdog timer.
2896 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2897 sc->ale_flags &= ~ALE_FLAG_LINK;
2898 callout_stop(&sc->ale_tick_ch);
2899 sc->ale_watchdog_timer = 0;
2900 ale_stats_update(sc);
2901 /* Disable interrupts. */
2902 CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2903 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2904 /* Disable queue processing and DMA. */
2905 reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2906 reg &= ~TXQ_CFG_ENB;
2907 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2908 reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2909 reg &= ~RXQ_CFG_ENB;
2910 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2911 reg = CSR_READ_4(sc, ALE_DMA_CFG);
2912 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2913 CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2915 /* Stop Rx/Tx MACs. */
2917 /* Disable interrupts which might be touched in taskq handler. */
2918 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2921 * Free TX mbufs still in the queues.
2923 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2924 txd = &sc->ale_cdata.ale_txdesc[i];
2925 if (txd->tx_m != NULL) {
2926 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2927 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2928 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2937 ale_stop_mac(struct ale_softc *sc)
2942 ALE_LOCK_ASSERT(sc);
2944 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2945 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2946 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2947 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2950 for (i = ALE_TIMEOUT; i > 0; i--) {
2951 reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2957 device_printf(sc->ale_dev,
2958 "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2962 ale_init_tx_ring(struct ale_softc *sc)
2964 struct ale_txdesc *txd;
2967 ALE_LOCK_ASSERT(sc);
2969 sc->ale_cdata.ale_tx_prod = 0;
2970 sc->ale_cdata.ale_tx_cons = 0;
2971 sc->ale_cdata.ale_tx_cnt = 0;
2973 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
2974 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
2975 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2976 txd = &sc->ale_cdata.ale_txdesc[i];
2979 *sc->ale_cdata.ale_tx_cmb = 0;
2980 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2981 sc->ale_cdata.ale_tx_cmb_map,
2982 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2983 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2984 sc->ale_cdata.ale_tx_ring_map,
2985 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2989 ale_init_rx_pages(struct ale_softc *sc)
2991 struct ale_rx_page *rx_page;
2994 ALE_LOCK_ASSERT(sc);
2996 atomic_set_int(&sc->ale_morework, 0);
2997 sc->ale_cdata.ale_rx_seqno = 0;
2998 sc->ale_cdata.ale_rx_curp = 0;
3000 for (i = 0; i < ALE_RX_PAGES; i++) {
3001 rx_page = &sc->ale_cdata.ale_rx_page[i];
3002 bzero(rx_page->page_addr, sc->ale_pagesize);
3003 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
3005 *rx_page->cmb_addr = 0;
3006 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
3007 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3008 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
3009 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3014 ale_rxvlan(struct ale_softc *sc)
3019 ALE_LOCK_ASSERT(sc);
3022 reg = CSR_READ_4(sc, ALE_MAC_CFG);
3023 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3024 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3025 reg |= MAC_CFG_VLAN_TAG_STRIP;
3026 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
3030 ale_rxfilter(struct ale_softc *sc)
3033 struct ifmultiaddr *ifma;
3038 ALE_LOCK_ASSERT(sc);
3042 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
3043 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3044 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3045 rxcfg |= MAC_CFG_BCAST;
3046 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3047 if ((ifp->if_flags & IFF_PROMISC) != 0)
3048 rxcfg |= MAC_CFG_PROMISC;
3049 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3050 rxcfg |= MAC_CFG_ALLMULTI;
3051 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
3052 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
3053 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3057 /* Program new filter. */
3058 bzero(mchash, sizeof(mchash));
3061 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) {
3062 if (ifma->ifma_addr->sa_family != AF_LINK)
3064 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
3065 ifma->ifma_addr), ETHER_ADDR_LEN);
3066 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3068 IF_ADDR_UNLOCK(ifp);
3070 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
3071 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
3072 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3076 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3082 value = *(int *)arg1;
3083 error = sysctl_handle_int(oidp, &value, 0, req);
3084 if (error || req->newptr == NULL)
3086 if (value < low || value > high)
3088 *(int *)arg1 = value;
3094 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS)
3096 return (sysctl_int_range(oidp, arg1, arg2, req,
3097 ALE_PROC_MIN, ALE_PROC_MAX));
3101 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)
3104 return (sysctl_int_range(oidp, arg1, arg2, req,
3105 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX));