2 * Copyright (c) 1995 - 2001 John Hay. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Neither the name of the author nor the names of any co-contributors
13 * may be used to endorse or promote products derived from this software
14 * without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 * Programming assumptions and other issues.
35 * The descriptors of a DMA channel will fit in a 16K memory window.
37 * The buffers of a transmit DMA channel will fit in a 16K memory window.
39 * Only the ISA bus cards with X.21 and V.35 is tested.
41 * When interface is going up, handshaking is set and it is only cleared
42 * when the interface is down'ed.
44 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
45 * internal/external clock, etc.....
48 #include "opt_netgraph.h"
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/malloc.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/module.h>
59 #include <machine/bus.h>
60 #include <machine/resource.h>
65 #include <netgraph/ng_message.h>
66 #include <netgraph/netgraph.h>
67 #include <sys/syslog.h>
68 #include <dev/ar/if_ar.h>
70 #include <net/if_sppp.h>
71 #include <net/if_types.h>
75 #include <machine/md_var.h>
77 #include <dev/ic/hd64570.h>
78 #include <dev/ar/if_arregs.h>
88 #define PPP_HEADER_LEN 4
90 devclass_t ar_devclass;
96 int unit; /* With regards to all ar devices */
97 int subunit; /* With regards to this card */
101 u_int txdesc; /* On card address */
102 u_int txstart; /* On card address */
103 u_int txend; /* On card address */
104 u_int txtail; /* Index of first unused buffer */
105 u_int txmax; /* number of usable buffers/descriptors */
106 u_int txeda; /* Error descriptor addresses */
107 }block[AR_TX_BLOCKS];
109 char xmit_busy; /* Transmitter is busy */
110 char txb_inuse; /* Number of tx blocks currently in use */
111 u_char txb_new; /* Index to where new buffer will be added */
112 u_char txb_next_tx; /* Index to next block ready to tx */
114 u_int rxdesc; /* On card address */
115 u_int rxstart; /* On card address */
116 u_int rxend; /* On card address */
117 u_int rxhind; /* Index to the head of the rx buffers. */
118 u_int rxmax; /* number of usable buffers/descriptors */
124 int running; /* something is attached so we are running */
125 int dcd; /* do we have dcd? */
126 /* ---netgraph bits --- */
127 char nodename[NG_NODESIZ]; /* store our node name */
128 int datahooks; /* number of data hooks attached */
129 node_p node; /* netgraph node */
130 hook_p hook; /* data hook */
132 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */
133 struct ifqueue xmitq; /* transmit queue */
134 int flags; /* state */
135 #define SCF_RUNNING 0x01 /* board is active */
136 #define SCF_OACTIVE 0x02 /* output is active */
137 int out_dog; /* watchdog cycles output count-down */
138 struct callout_handle handle; /* timeout(9) handle */
139 u_long inbytes, outbytes; /* stats */
140 u_long lastinbytes, lastoutbytes; /* a second ago */
141 u_long inrate, outrate; /* highest rate seen */
142 u_long inlast; /* last input N secs ago */
143 u_long out_deficit; /* output since last input */
144 u_long oerrors, ierrors[6];
145 u_long opackets, ipackets;
146 #endif /* NETGRAPH */
148 #define SC2IFP(sc) (sc)->ifp
150 static int next_ar_unit = 0;
153 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */
154 #define QUITE_A_WHILE 300 /* 5 MINUTES */
155 #define LOTS_OF_PACKETS 100
156 #endif /* NETGRAPH */
159 * This translate from irq numbers to
160 * the value that the arnet card needs
161 * in the lower part of the AR_INT_SEL
164 static int irqtable[16] = {
184 MODULE_DEPEND(if_ar, sppp, 1, 1, 1);
187 static void arintr(void *arg);
188 static void ar_xmit(struct ar_softc *sc);
190 static void arstart(struct ifnet *ifp);
191 static int arioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
192 static void arwatchdog(struct ifnet *ifp);
194 static void arstart(struct ar_softc *sc);
195 static void arwatchdog(struct ar_softc *sc);
196 #endif /* NETGRAPH */
197 static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat);
198 static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len);
199 static void ar_eat_packet(struct ar_softc *sc, int single);
200 static void ar_get_packets(struct ar_softc *sc);
202 static int ar_read_pim_iface(volatile struct ar_hardc *hc, int channel);
203 static void ar_up(struct ar_softc *sc);
204 static void ar_down(struct ar_softc *sc);
205 static void arc_init(struct ar_hardc *hc);
206 static void ar_init_sca(struct ar_hardc *hc, int scano);
207 static void ar_init_msci(struct ar_softc *sc);
208 static void ar_init_rx_dmac(struct ar_softc *sc);
209 static void ar_init_tx_dmac(struct ar_softc *sc);
210 static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr);
211 static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr);
212 static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr);
215 static void ngar_watchdog_frame(void * arg);
217 static ng_constructor_t ngar_constructor;
218 static ng_rcvmsg_t ngar_rcvmsg;
219 static ng_shutdown_t ngar_shutdown;
220 static ng_newhook_t ngar_newhook;
221 /*static ng_findhook_t ngar_findhook; */
222 static ng_connect_t ngar_connect;
223 static ng_rcvdata_t ngar_rcvdata;
224 static ng_disconnect_t ngar_disconnect;
226 static struct ng_type typestruct = {
227 .version = NG_ABI_VERSION,
228 .name = NG_AR_NODE_TYPE,
229 .constructor = ngar_constructor,
230 .rcvmsg = ngar_rcvmsg,
231 .shutdown = ngar_shutdown,
232 .newhook = ngar_newhook,
233 .connect = ngar_connect,
234 .rcvdata = ngar_rcvdata,
235 .disconnect = ngar_disconnect,
237 NETGRAPH_INIT_ORDERED(sync_ar, &typestruct, SI_SUB_DRIVERS, SI_ORDER_FIRST);
238 #endif /* NETGRAPH */
241 ar_attach(device_t device)
248 #endif /* NETGRAPH */
251 hc = (struct ar_hardc *)device_get_softc(device);
253 printf("arc%d: %uK RAM, %u ports, rev %u.\n",
261 if(bus_setup_intr(device, hc->res_irq,
262 INTR_TYPE_NET, NULL, arintr, hc, &hc->intr_cookie) != 0)
267 for(unit=0;unit<hc->numports;unit+=NCHAN)
268 ar_init_sca(hc, unit / NCHAN);
271 * Now configure each port on the card.
273 for(unit=0;unit<hc->numports;sc++,unit++) {
276 sc->unit = next_ar_unit;
278 sc->scano = unit / NCHAN;
279 sc->scachan = unit%NCHAN;
286 ifp = SC2IFP(sc) = if_alloc(IFT_PPP);
288 if (bus_teardown_intr(device,
289 hc->res_irq, hc->intr_cookie) != 0) {
290 printf("intr teardown failed.. continuing\n");
296 if_initname(ifp, device_get_name(device),
297 device_get_unit(device));
298 ifp->if_mtu = PP_MTU;
299 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST |
301 ifp->if_ioctl = arioctl;
302 ifp->if_start = arstart;
303 ifp->if_watchdog = arwatchdog;
305 IFP2SP(sc->ifp)->pp_flags = PP_KEEPALIVE;
307 switch(hc->interface[unit]) {
308 default: iface = "UNKNOWN"; break;
309 case AR_IFACE_EIA_232: iface = "EIA-232"; break;
310 case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break;
311 case AR_IFACE_EIA_530: iface = "EIA-530"; break;
312 case AR_IFACE_X_21: iface = "X.21"; break;
313 case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break;
316 printf("ar%d: Adapter %d, port %d, interface %s.\n",
322 sppp_attach(SC2IFP(sc));
325 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
327 if (ng_make_node_common(&typestruct, &sc->node) != 0)
329 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
330 if (ng_name_node(sc->node, sc->nodename)) {
331 NG_NODE_UNREF(sc->node); /* drop it again */
334 NG_NODE_SET_PRIVATE(sc->node, sc);
335 callout_handle_init(&sc->handle);
336 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
337 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
338 mtx_init(&sc->xmitq.ifq_mtx, "ar_xmitq", NULL, MTX_DEF);
339 mtx_init(&sc->xmitq_hipri.ifq_mtx, "ar_xmitq_hipri", NULL,
342 #endif /* NETGRAPH */
345 if(hc->bustype == AR_BUS_ISA)
352 ar_detach(device_t device)
354 struct ar_hardc *hc = device_get_softc(device);
356 if (hc->intr_cookie != NULL) {
357 if (bus_teardown_intr(device,
358 hc->res_irq, hc->intr_cookie) != 0) {
359 printf("intr teardown failed.. continuing\n");
361 hc->intr_cookie = NULL;
365 * deallocate any system resources we may have
366 * allocated on behalf of this driver.
368 FREE(hc->sc, M_DEVBUF);
370 hc->mem_start = NULL;
371 return (ar_deallocate_resources(device));
375 ar_allocate_ioport(device_t device, int rid, u_long size)
377 struct ar_hardc *hc = device_get_softc(device);
379 hc->rid_ioport = rid;
380 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
381 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
382 if (hc->res_ioport == NULL) {
385 hc->bt = rman_get_bustag(hc->res_ioport);
386 hc->bh = rman_get_bushandle(hc->res_ioport);
391 ar_deallocate_resources(device);
396 ar_allocate_irq(device_t device, int rid, u_long size)
398 struct ar_hardc *hc = device_get_softc(device);
401 hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ,
402 &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE);
403 if (hc->res_irq == NULL) {
409 ar_deallocate_resources(device);
414 ar_allocate_memory(device_t device, int rid, u_long size)
416 struct ar_hardc *hc = device_get_softc(device);
418 hc->rid_memory = rid;
419 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
420 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
421 if (hc->res_memory == NULL) {
427 ar_deallocate_resources(device);
432 ar_allocate_plx_memory(device_t device, int rid, u_long size)
434 struct ar_hardc *hc = device_get_softc(device);
436 hc->rid_plx_memory = rid;
437 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
438 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
439 if (hc->res_plx_memory == NULL) {
445 ar_deallocate_resources(device);
450 ar_deallocate_resources(device_t device)
452 struct ar_hardc *hc = device_get_softc(device);
454 if (hc->res_irq != 0) {
455 bus_release_resource(device, SYS_RES_IRQ,
456 hc->rid_irq, hc->res_irq);
459 if (hc->res_ioport != 0) {
460 bus_release_resource(device, SYS_RES_IOPORT,
461 hc->rid_ioport, hc->res_ioport);
464 if (hc->res_memory != 0) {
465 bus_release_resource(device, SYS_RES_MEMORY,
466 hc->rid_memory, hc->res_memory);
469 if (hc->res_plx_memory != 0) {
470 bus_release_resource(device, SYS_RES_MEMORY,
471 hc->rid_plx_memory, hc->res_plx_memory);
472 hc->res_plx_memory = 0;
478 * First figure out which SCA gave the interrupt.
480 * See if there is other interrupts pending.
481 * Repeat until there is no more interrupts.
486 struct ar_hardc *hc = (struct ar_hardc *)arg;
488 u_char isr0, isr1, isr2, arisr;
491 /* XXX Use the PCI interrupt score board register later */
492 if(hc->bustype == AR_BUS_PCI)
493 arisr = hc->orbase[AR_ISTAT * 4];
495 arisr = ar_inb(hc, AR_ISTAT);
497 while(arisr & AR_BD_INT) {
498 TRC(printf("arisr = %x\n", arisr));
501 else if(arisr & AR_INT_1)
504 /* XXX Oops this shouldn't happen. */
505 printf("arc%d: Interrupted with no interrupt.\n",
509 sca = hc->sca[scano];
511 if(hc->bustype == AR_BUS_ISA)
512 ARC_SET_SCA(hc, scano);
518 TRC(printf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n",
524 ar_msci_intr(hc, scano, isr0);
527 ar_dmac_intr(hc, scano, isr1);
530 ar_timer_intr(hc, scano, isr2);
533 * Proccess the second sca's interrupt if available.
534 * Else see if there are any new interrupts.
536 if((arisr & AR_INT_0) && (arisr & AR_INT_1))
539 if(hc->bustype == AR_BUS_PCI)
540 arisr = hc->orbase[AR_ISTAT * 4];
542 arisr = ar_inb(hc, AR_ISTAT);
546 if(hc->bustype == AR_BUS_ISA)
552 * This will only start the transmitter. It is assumed that the data
553 * is already there. It is normally called from arstart() or ar_dmac_intr().
557 ar_xmit(struct ar_softc *sc)
561 #endif /* NETGRAPH */
566 #endif /* NETGRAPH */
567 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
569 if(sc->hc->bustype == AR_BUS_ISA)
570 ARC_SET_SCA(sc->hc, sc->scano);
571 dmac->cda = (u_short)(sc->block[sc->txb_next_tx].txdesc & 0xffff);
573 dmac->eda = (u_short)(sc->block[sc->txb_next_tx].txeda & 0xffff);
574 dmac->dsr = SCA_DSR_DE;
579 if(sc->txb_next_tx == AR_TX_BLOCKS)
583 ifp->if_timer = 2; /* Value in seconds. */
585 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/
586 #endif /* NETGRAPH */
587 if(sc->hc->bustype == AR_BUS_ISA)
592 * This function will be called from the upper level when a user add a
593 * packet to be send, and from the interrupt handler after a finished
596 * NOTE: it should run at spl_imp().
598 * This function only place the data in the oncard buffers. It does not
599 * start the transmition. ar_xmit() does that.
601 * Transmitter idle state is indicated by the IFF_DRV_OACTIVE flag. The
602 * function that clears that should ensure that the transmitter and its
603 * DMA is in a "good" idle state.
607 arstart(struct ifnet *ifp)
609 struct ar_softc *sc = ifp->if_softc;
612 arstart(struct ar_softc *sc)
614 #endif /* NETGRAPH */
618 sca_descriptor *txdesc;
619 struct buf_block *blkp;
622 if(!(ifp->if_drv_flags & IFF_DRV_RUNNING))
626 #endif /* NETGRAPH */
631 * See if we have space for more packets.
633 if(sc->txb_inuse == AR_TX_BLOCKS) {
635 ifp->if_drv_flags |= IFF_DRV_OACTIVE; /* yes, mark active */
637 /*XXX*/ /*ifp->if_drv_flags |= IFF_DRV_OACTIVE;*/ /* yes, mark active */
638 #endif /* NETGRAPH */
643 mtx = sppp_dequeue(ifp);
645 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
647 IF_DEQUEUE(&sc->xmitq, mtx);
649 #endif /* NETGRAPH */
654 * It is OK to set the memory window outside the loop because
655 * all tx buffers and descriptors are assumed to be in the same
658 if(sc->hc->bustype == AR_BUS_ISA)
659 ARC_SET_MEM(sc->hc, sc->block[0].txdesc);
662 * We stay in this loop until there is nothing in the
663 * TX queue left or the tx buffer is full.
666 blkp = &sc->block[sc->txb_new];
667 txdesc = (sca_descriptor *)
668 (sc->hc->mem_start + (blkp->txdesc & sc->hc->winmsk));
669 txdata = (u_char *)(sc->hc->mem_start + (blkp->txstart & sc->hc->winmsk));
671 len = mtx->m_pkthdr.len;
673 TRC(printf("ar%d: ARstart len %u\n", sc->unit, len));
676 * We can do this because the tx buffers don't wrap.
678 m_copydata(mtx, 0, len, txdata);
680 while(tlen > AR_BUF_SIZ) {
682 txdesc->len = AR_BUF_SIZ;
685 txdata += AR_BUF_SIZ;
688 /* XXX Move into the loop? */
689 txdesc->stat = SCA_DESC_EOM;
692 txdata += AR_BUF_SIZ;
698 ++SC2IFP(sc)->if_opackets;
703 #endif /* NETGRAPH */
706 * Check if we have space for another mbuf.
707 * XXX This is hardcoded. A packet won't be larger
708 * than 3 buffers (3 x 512).
710 if((i + 3) >= blkp->txmax)
714 mtx = sppp_dequeue(ifp);
716 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
718 IF_DEQUEUE(&sc->xmitq, mtx);
720 #endif /* NETGRAPH */
728 * Mark the last descriptor, so that the SCA know where
732 txdesc->stat |= SCA_DESC_EOT;
734 txdesc = (sca_descriptor *)blkp->txdesc;
735 blkp->txeda = (u_short)((u_int)&txdesc[i]);
738 printf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp);
739 printf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp);
740 printf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb);
741 printf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len);
742 printf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat);
747 if(sc->txb_new == AR_TX_BLOCKS)
750 if(sc->xmit_busy == 0)
753 if(sc->hc->bustype == AR_BUS_ISA)
761 arioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
764 int was_up, should_be_up;
765 struct ar_softc *sc = ifp->if_softc;
767 TRC(if_printf(ifp, "arioctl.\n");)
769 was_up = ifp->if_drv_flags & IFF_DRV_RUNNING;
771 error = sppp_ioctl(ifp, cmd, data);
772 TRC(if_printf(ifp, "ioctl: ifsppp.pp_flags = %x, if_flags %x.\n",
773 ((struct sppp *)ifp)->pp_flags, ifp->if_flags);)
777 if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR))
780 TRC(if_printf(ifp, "arioctl %s.\n",
781 (cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");)
784 should_be_up = ifp->if_drv_flags & IFF_DRV_RUNNING;
786 if(!was_up && should_be_up) {
787 /* Interface should be up -- start it. */
790 /* XXX Maybe clear the IFF_UP flag so that the link
791 * will only go up after sppp lcp and ipcp negotiation.
793 } else if(was_up && !should_be_up) {
794 /* Interface should be down -- stop it. */
801 #endif /* NETGRAPH */
804 * This is to catch lost tx interrupts.
808 arwatchdog(struct ifnet *ifp)
810 struct ar_softc *sc = ifp->if_softc;
812 arwatchdog(struct ar_softc *sc)
814 #endif /* NETGRAPH */
815 msci_channel *msci = &sc->sca->msci[sc->scachan];
818 if(!(ifp->if_drv_flags & IFF_DRV_RUNNING))
820 #endif /* NETGRAPH */
822 if(sc->hc->bustype == AR_BUS_ISA)
823 ARC_SET_SCA(sc->hc, sc->scano);
825 /* XXX if(SC2IFP(sc)->if_flags & IFF_DEBUG) */
826 printf("ar%d: transmit failed, "
827 "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n",
832 sc->sca->dmac[DMAC_TXCH(sc->scachan)].dsr);
834 if(msci->st1 & SCA_ST1_UDRN) {
835 msci->cmd = SCA_CMD_TXABORT;
836 msci->cmd = SCA_CMD_TXENABLE;
837 msci->st1 = SCA_ST1_UDRN;
842 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
844 /* XXX ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; */
845 #endif /* NETGRAPH */
847 if(sc->txb_inuse && --sc->txb_inuse)
854 #endif /* NETGRAPH */
858 ar_up(struct ar_softc *sc)
864 msci = &sca->msci[sc->scachan];
866 TRC(printf("ar%d: sca %p, msci %p, ch %d\n",
867 sc->unit, sca, msci, sc->scachan));
870 * Enable transmitter and receiver.
874 if(sc->hc->bustype == AR_BUS_ISA)
875 ARC_SET_SCA(sc->hc, sc->scano);
878 * What about using AUTO mode in msci->md0 ???
879 * And what about CTS/DCD etc... ?
881 if(sc->hc->handshake & AR_SHSK_RTS)
882 msci->ctl &= ~SCA_CTL_RTS;
883 if(sc->hc->handshake & AR_SHSK_DTR) {
884 sc->hc->txc_dtr[sc->scano] &= sc->scachan ?
885 ~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0;
886 if(sc->hc->bustype == AR_BUS_PCI)
887 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
888 sc->hc->txc_dtr[sc->scano];
890 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano],
891 sc->hc->txc_dtr[sc->scano]);
894 if(sc->scachan == 0) {
902 msci->cmd = SCA_CMD_RXENABLE;
903 if(sc->hc->bustype == AR_BUS_ISA)
904 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */
905 msci->cmd = SCA_CMD_TXENABLE;
907 if(sc->hc->bustype == AR_BUS_ISA)
910 untimeout(ngar_watchdog_frame, sc, sc->handle);
911 sc->handle = timeout(ngar_watchdog_frame, sc, hz);
913 #endif /* NETGRAPH */
917 ar_down(struct ar_softc *sc)
923 msci = &sca->msci[sc->scachan];
926 untimeout(ngar_watchdog_frame, sc, sc->handle);
928 #endif /* NETGRAPH */
930 * Disable transmitter and receiver.
932 * Disable interrupts.
934 if(sc->hc->bustype == AR_BUS_ISA)
935 ARC_SET_SCA(sc->hc, sc->scano);
936 msci->cmd = SCA_CMD_RXDISABLE;
937 if(sc->hc->bustype == AR_BUS_ISA)
938 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */
939 msci->cmd = SCA_CMD_TXDISABLE;
941 if(sc->hc->handshake & AR_SHSK_RTS)
942 msci->ctl |= SCA_CTL_RTS;
943 if(sc->hc->handshake & AR_SHSK_DTR) {
944 sc->hc->txc_dtr[sc->scano] |= sc->scachan ?
945 AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0;
946 if(sc->hc->bustype == AR_BUS_PCI)
947 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
948 sc->hc->txc_dtr[sc->scano];
950 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano],
951 sc->hc->txc_dtr[sc->scano]);
954 if(sc->scachan == 0) {
962 if(sc->hc->bustype == AR_BUS_ISA)
967 ar_read_pim_iface(volatile struct ar_hardc *hc, int channel)
969 int ctype, i, val, x;
970 volatile u_char *pimctrl;
975 pimctrl = hc->orbase + AR_PIMCTRL;
979 *pimctrl = AR_PIM_STROBE;
981 /* Check if there is a PIM */
983 *pimctrl = AR_PIM_READ;
985 TRC(printf("x = %x", x));
986 if(x & AR_PIM_DATA) {
987 printf("No PIM installed\n");
988 return (AR_IFACE_UNKNOWN);
994 /* Now read the next 15 bits */
995 for(i = 1; i < 16; i++) {
996 *pimctrl = AR_PIM_READ;
997 *pimctrl = AR_PIM_READ | AR_PIM_STROBE;
999 TRC(printf(" %x ", x));
1000 x = (x >> 1) & 0x01;
1002 if(i == 8 && (val & 0x000f) == 0x0004) {
1006 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1007 *pimctrl = AR_PIM_A2D_DOUT;
1010 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1011 *pimctrl = AR_PIM_A2D_DOUT;
1014 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1015 *pimctrl = AR_PIM_A2D_DOUT;
1017 /* Select channel */
1018 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 2) << 2);
1019 *pimctrl = ((channel & 2) << 2);
1020 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 1) << 3);
1021 *pimctrl = ((channel & 1) << 3);
1023 *pimctrl = AR_PIM_A2D_STROBE;
1027 printf("\nOops A2D start bit not zero (%X)\n", x);
1029 for(ii = 7; ii >= 0; ii--) {
1031 *pimctrl = AR_PIM_A2D_STROBE;
1038 TRC(printf("\nPIM val %x, ctype %x, %d\n", val, ctype, ctype));
1039 *pimctrl = AR_PIM_MODEG;
1040 *pimctrl = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1042 return (AR_IFACE_UNKNOWN);
1044 return (AR_IFACE_V_35);
1046 return (AR_IFACE_EIA_232);
1048 return (AR_IFACE_X_21);
1050 return (AR_IFACE_EIA_530);
1052 return (AR_IFACE_UNKNOWN);
1054 return (AR_IFACE_LOOPBACK);
1055 return (AR_IFACE_UNKNOWN);
1059 * Initialize the card, allocate memory for the ar_softc structures
1060 * and fill in the pointers.
1063 arc_init(struct ar_hardc *hc)
1065 struct ar_softc *sc;
1074 MALLOC(sc, struct ar_softc *, hc->numports * sizeof(struct ar_softc),
1075 M_DEVBUF, M_WAITOK | M_ZERO);
1080 hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET |
1081 AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1082 hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1083 hc->txc_dtr_off[0] = AR_TXC_DTR0;
1084 hc->txc_dtr_off[1] = AR_TXC_DTR2;
1085 if(hc->bustype == AR_BUS_PCI) {
1086 hc->txc_dtr_off[0] *= 4;
1087 hc->txc_dtr_off[1] *= 4;
1091 * reset the card and wait at least 1uS.
1093 if(hc->bustype == AR_BUS_PCI)
1094 hc->orbase[AR_TXC_DTR0 * 4] = ~AR_TXC_DTR_NOTRESET &
1097 ar_outb(hc, AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET &
1100 if(hc->bustype == AR_BUS_PCI)
1101 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1103 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]);
1105 if(hc->bustype == AR_BUS_ISA) {
1107 * Configure the card.
1110 memst = rman_get_start(hc->res_memory);
1112 isr = irqtable[hc->isa_irq] << 1;
1114 printf("ar%d: Warning illegal interrupt %d\n",
1115 hc->cunit, hc->isa_irq);
1116 isr = isr | ((memst & 0xc000) >> 10);
1118 hc->sca[0] = (sca_regs *)hc->mem_start;
1119 hc->sca[1] = (sca_regs *)hc->mem_start;
1121 ar_outb(hc, AR_MEM_SEL, mar);
1122 ar_outb(hc, AR_INT_SEL, isr | AR_INTS_CEN);
1125 if(hc->bustype == AR_BUS_PCI && hc->interface[0] == AR_IFACE_PIM)
1126 for(x = 0; x < hc->numports; x++)
1127 hc->interface[x] = ar_read_pim_iface(hc, x);
1130 * Set the TX clock direction and enable TX.
1132 for(x=0;x<hc->numports;x++) {
1133 switch(hc->interface[x]) {
1135 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1136 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1137 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1138 AR_TXC_DTR_TXCS0 : AR_TXC_DTR_TXCS1;
1140 case AR_IFACE_EIA_530:
1141 case AR_IFACE_COMBO:
1143 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1144 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1149 if(hc->bustype == AR_BUS_PCI)
1150 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1152 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]);
1153 if(hc->numports > NCHAN) {
1154 if(hc->bustype == AR_BUS_PCI)
1155 hc->orbase[AR_TXC_DTR2 * 4] = hc->txc_dtr[1];
1157 ar_outb(hc, AR_TXC_DTR2, hc->txc_dtr[1]);
1160 chanmem = hc->memsize / hc->numports;
1163 for(x=0;x<hc->numports;x++, sc++) {
1166 sc->sca = hc->sca[x / NCHAN];
1168 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1169 sc->block[blk].txdesc = next;
1170 bufmem = (16 * 1024) / AR_TX_BLOCKS;
1171 descneeded = bufmem / AR_BUF_SIZ;
1172 sc->block[blk].txstart = sc->block[blk].txdesc +
1173 ((((descneeded * sizeof(sca_descriptor)) /
1174 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1175 sc->block[blk].txend = next + bufmem;
1176 sc->block[blk].txmax =
1177 (sc->block[blk].txend - sc->block[blk].txstart)
1181 TRC(printf("ar%d: blk %d: txdesc %x, txstart %x, "
1182 "txend %x, txmax %d\n",
1185 sc->block[blk].txdesc,
1186 sc->block[blk].txstart,
1187 sc->block[blk].txend,
1188 sc->block[blk].txmax));
1192 bufmem = chanmem - (bufmem * AR_TX_BLOCKS);
1193 descneeded = bufmem / AR_BUF_SIZ;
1194 sc->rxstart = sc->rxdesc +
1195 ((((descneeded * sizeof(sca_descriptor)) /
1196 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1197 sc->rxend = next + bufmem;
1198 sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ;
1200 TRC(printf("ar%d: rxdesc %x, rxstart %x, "
1201 "rxend %x, rxmax %d\n",
1202 x, sc->rxdesc, sc->rxstart, sc->rxend, sc->rxmax));
1205 if(hc->bustype == AR_BUS_PCI)
1206 hc->orbase[AR_PIMCTRL] = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1211 * The things done here are channel independent.
1213 * Configure the sca waitstates.
1214 * Configure the global interrupt registers.
1215 * Enable master dma enable.
1218 ar_init_sca(struct ar_hardc *hc, int scano)
1222 sca = hc->sca[scano];
1223 if(hc->bustype == AR_BUS_ISA)
1224 ARC_SET_SCA(hc, scano);
1227 * Do the wait registers.
1228 * Set everything to 0 wait states.
1237 * Configure the interrupt registers.
1238 * Most are cleared until the interface is configured.
1240 sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */
1241 sca->ier1 = 0x00; /* DMAC interrupts */
1242 sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */
1243 sca->itcr = 0x00; /* Use ivr and no intr ack */
1244 sca->ivr = 0x40; /* Fill in the interrupt vector. */
1248 * Configure the timers.
1254 * Set the DMA channel priority to rotate between
1255 * all four channels.
1257 * Enable all dma channels.
1259 if(hc->bustype == AR_BUS_PCI) {
1263 * Stupid problem with the PCI interface chip that break
1268 t[AR_PCI_SCA_PCR] = SCA_PCR_PR2;
1269 t[AR_PCI_SCA_DMER] = SCA_DMER_EN;
1271 sca->pcr = SCA_PCR_PR2;
1272 sca->dmer = SCA_DMER_EN;
1278 * Configure the msci
1280 * NOTE: The serial port configuration is hardcoded at the moment.
1283 ar_init_msci(struct ar_softc *sc)
1287 msci = &sc->sca->msci[sc->scachan];
1289 if(sc->hc->bustype == AR_BUS_ISA)
1290 ARC_SET_SCA(sc->hc, sc->scano);
1292 msci->cmd = SCA_CMD_RESET;
1294 msci->md0 = SCA_MD0_CRC_1 |
1296 SCA_MD0_CRC_ENABLE |
1298 msci->md1 = SCA_MD1_NOADDRCHK;
1299 msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ;
1302 * Acording to the manual I should give a reset after changing the
1305 msci->cmd = SCA_CMD_RXRESET;
1306 msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS;
1309 * For now all interfaces are programmed to use the RX clock for
1312 switch(sc->hc->interface[sc->subunit]) {
1314 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1315 msci->txs = SCA_TXS_CLK_TXC | SCA_TXS_DIV1;
1318 case AR_IFACE_EIA_530:
1319 case AR_IFACE_COMBO:
1320 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1321 msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1;
1324 msci->tmc = 153; /* This give 64k for loopback */
1327 * Disable all interrupts for now. I think if you are using
1328 * the dmac you don't use these interrupts.
1331 msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */
1338 msci->idl = 0x7E; /* XXX This is what cisco does. */
1341 * This is what the ARNET diags use.
1349 * Configure the rx dma controller.
1352 ar_init_rx_dmac(struct ar_softc *sc)
1355 sca_descriptor *rxd;
1361 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1363 if(sc->hc->bustype == AR_BUS_ISA)
1364 ARC_SET_MEM(sc->hc, sc->rxdesc);
1366 rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&sc->hc->winmsk));
1367 rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~sc->hc->winmsk);
1369 for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) {
1370 rxda = (u_int)&rxd[1] - rxda_d;
1371 rxd->cp = (u_short)(rxda & 0xfffful);
1375 TRC(printf("Descrp %p, data pt %x, data %x, ",
1378 rxd->bp = (u_short)(rxbuf & 0xfffful);
1379 rxd->bpb = (u_char)((rxbuf >> 16) & 0xff);
1381 rxd->stat = 0xff; /* The sca write here when it is finished. */
1384 TRC(printf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp));
1387 rxd->cp = (u_short)(sc->rxdesc & 0xfffful);
1391 if(sc->hc->bustype == AR_BUS_ISA)
1392 ARC_SET_SCA(sc->hc, sc->scano);
1394 dmac->dsr = 0; /* Disable DMA transfer */
1395 dmac->dcr = SCA_DCR_ABRT;
1397 /* XXX maybe also SCA_DMR_CNTE */
1398 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1399 dmac->bfl = AR_BUF_SIZ;
1401 dmac->cda = (u_short)(sc->rxdesc & 0xffff);
1402 dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff);
1404 rxd = (sca_descriptor *)sc->rxstart;
1405 dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff);
1409 dmac->dsr = SCA_DSR_DE;
1413 * Configure the TX DMA descriptors.
1414 * Initialize the needed values and chain the descriptors.
1417 ar_init_tx_dmac(struct ar_softc *sc)
1420 struct buf_block *blkp;
1422 sca_descriptor *txd;
1427 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
1429 if(sc->hc->bustype == AR_BUS_ISA)
1430 ARC_SET_MEM(sc->hc, sc->block[0].txdesc);
1432 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1433 blkp = &sc->block[blk];
1434 txd = (sca_descriptor *)(sc->hc->mem_start +
1435 (blkp->txdesc&sc->hc->winmsk));
1436 txda_d = (u_int)sc->hc->mem_start -
1437 (blkp->txdesc & ~sc->hc->winmsk);
1439 txbuf=blkp->txstart;
1440 for(;txbuf<blkp->txend;txbuf += AR_BUF_SIZ, txd++) {
1441 txda = (u_int)&txd[1] - txda_d;
1442 txd->cp = (u_short)(txda & 0xfffful);
1444 txd->bp = (u_short)(txbuf & 0xfffful);
1445 txd->bpb = (u_char)((txbuf >> 16) & 0xff);
1446 TRC(printf("ar%d: txbuf %x, bpb %x, bp %x\n",
1447 sc->unit, txbuf, txd->bpb, txd->bp));
1452 txd->cp = (u_short)(blkp->txdesc & 0xfffful);
1454 blkp->txtail = (u_int)txd - (u_int)sc->hc->mem_start;
1455 TRC(printf("TX Descriptors start %x, end %x.\n",
1460 if(sc->hc->bustype == AR_BUS_ISA)
1461 ARC_SET_SCA(sc->hc, sc->scano);
1463 dmac->dsr = 0; /* Disable DMA */
1464 dmac->dcr = SCA_DCR_ABRT;
1465 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1466 dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF;
1468 dmac->sarb = (u_char)((sc->block[0].txdesc >> 16) & 0xff);
1473 * Look through the descriptors to see if there is a complete packet
1474 * available. Stop if we get to where the sca is busy.
1476 * Return the length and status of the packet.
1477 * Return nonzero if there is a packet available.
1480 * It seems that we get the interrupt a bit early. The updateing of
1481 * descriptor values is not always completed when this is called.
1484 ar_packet_avail(struct ar_softc *sc,
1489 sca_descriptor *rxdesc;
1490 sca_descriptor *endp;
1491 sca_descriptor *cda;
1493 if(sc->hc->bustype == AR_BUS_ISA)
1494 ARC_SET_SCA(sc->hc, sc->scano);
1495 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1496 cda = (sca_descriptor *)(sc->hc->mem_start +
1497 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1499 if(sc->hc->bustype == AR_BUS_ISA)
1500 ARC_SET_MEM(sc->hc, sc->rxdesc);
1501 rxdesc = (sca_descriptor *)
1502 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1504 rxdesc = &rxdesc[sc->rxhind];
1505 endp = &endp[sc->rxmax];
1509 while(rxdesc != cda) {
1510 *len += rxdesc->len;
1512 if(rxdesc->stat & SCA_DESC_EOM) {
1513 *rxstat = rxdesc->stat;
1514 TRC(printf("ar%d: PKT AVAIL len %d, %x.\n",
1515 sc->unit, *len, *rxstat));
1521 rxdesc = (sca_descriptor *)
1522 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1532 * Copy a packet from the on card memory into a provided mbuf.
1533 * Take into account that buffers wrap and that a packet may
1534 * be larger than a buffer.
1537 ar_copy_rxbuf(struct mbuf *m,
1538 struct ar_softc *sc,
1541 sca_descriptor *rxdesc;
1547 rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ);
1548 rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ);
1550 rxdesc = (sca_descriptor *)
1551 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1552 rxdesc = &rxdesc[sc->rxhind];
1555 tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ;
1556 if(sc->hc->bustype == AR_BUS_ISA)
1557 ARC_SET_MEM(sc->hc, rxdata);
1558 bcopy(sc->hc->mem_start + (rxdata & sc->hc->winmsk),
1559 mtod(m, caddr_t) + off,
1565 if(sc->hc->bustype == AR_BUS_ISA)
1566 ARC_SET_MEM(sc->hc, sc->rxdesc);
1568 rxdesc->stat = 0xff;
1570 rxdata += AR_BUF_SIZ;
1572 if(rxdata == rxmax) {
1573 rxdata = sc->rxstart;
1574 rxdesc = (sca_descriptor *)
1575 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1581 * If single is set, just eat a packet. Otherwise eat everything up to
1582 * where cda points. Update pointers to point to the next packet.
1585 ar_eat_packet(struct ar_softc *sc, int single)
1588 sca_descriptor *rxdesc;
1589 sca_descriptor *endp;
1590 sca_descriptor *cda;
1594 if(sc->hc->bustype == AR_BUS_ISA)
1595 ARC_SET_SCA(sc->hc, sc->scano);
1596 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1597 cda = (sca_descriptor *)(sc->hc->mem_start +
1598 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1601 * Loop until desc->stat == (0xff || EOM)
1602 * Clear the status and length in the descriptor.
1603 * Increment the descriptor.
1605 if(sc->hc->bustype == AR_BUS_ISA)
1606 ARC_SET_MEM(sc->hc, sc->rxdesc);
1607 rxdesc = (sca_descriptor *)
1608 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1610 rxdesc = &rxdesc[sc->rxhind];
1611 endp = &endp[sc->rxmax];
1613 while(rxdesc != cda) {
1615 if(loopcnt > sc->rxmax) {
1616 printf("ar%d: eat pkt %d loop, cda %p, "
1617 "rxdesc %p, stat %x.\n",
1626 stat = rxdesc->stat;
1629 rxdesc->stat = 0xff;
1633 if(rxdesc == endp) {
1634 rxdesc = (sca_descriptor *)
1635 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1639 if(single && (stat == SCA_DESC_EOM))
1644 * Update the eda to the previous descriptor.
1646 if(sc->hc->bustype == AR_BUS_ISA)
1647 ARC_SET_SCA(sc->hc, sc->scano);
1649 rxdesc = (sca_descriptor *)sc->rxdesc;
1650 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1652 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1653 (u_short)((u_int)rxdesc & 0xffff);
1658 * While there is packets available in the rx buffer, read them out
1659 * into mbufs and ship them off.
1662 ar_get_packets(struct ar_softc *sc)
1664 sca_descriptor *rxdesc;
1665 struct mbuf *m = NULL;
1673 while(ar_packet_avail(sc, &len, &rxstat)) {
1674 TRC(printf("apa: len %d, rxstat %x\n", len, rxstat));
1675 if(((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
1676 MGETHDR(m, M_DONTWAIT, MT_DATA);
1678 /* eat packet if get mbuf fail!! */
1679 ar_eat_packet(sc, 1);
1683 m->m_pkthdr.rcvif = SC2IFP(sc);
1684 #else /* NETGRAPH */
1685 m->m_pkthdr.rcvif = NULL;
1688 #endif /* NETGRAPH */
1689 m->m_pkthdr.len = m->m_len = len;
1691 MCLGET(m, M_DONTWAIT);
1692 if((m->m_flags & M_EXT) == 0) {
1694 ar_eat_packet(sc, 1);
1698 ar_copy_rxbuf(m, sc, len);
1700 BPF_MTAP(SC2IFP(sc), m);
1701 sppp_input(SC2IFP(sc), m);
1702 SC2IFP(sc)->if_ipackets++;
1703 #else /* NETGRAPH */
1704 NG_SEND_DATA_ONLY(error, sc->hook, m);
1706 #endif /* NETGRAPH */
1709 * Update the eda to the previous descriptor.
1711 i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ;
1712 sc->rxhind = (sc->rxhind + i) % sc->rxmax;
1714 if(sc->hc->bustype == AR_BUS_ISA)
1715 ARC_SET_SCA(sc->hc, sc->scano);
1717 rxdesc = (sca_descriptor *)sc->rxdesc;
1719 &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1721 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1722 (u_short)((u_int)rxdesc & 0xffff);
1726 while((rxstat == 0xff) && --tries)
1727 ar_packet_avail(sc, &len, &rxstat);
1730 * It look like we get an interrupt early
1731 * sometimes and then the status is not
1734 if(tries && (tries != 5))
1737 ar_eat_packet(sc, 1);
1740 SC2IFP(sc)->if_ierrors++;
1741 #else /* NETGRAPH */
1743 #endif /* NETGRAPH */
1745 if(sc->hc->bustype == AR_BUS_ISA)
1746 ARC_SET_SCA(sc->hc, sc->scano);
1748 TRCL(printf("ar%d: Receive error chan %d, "
1749 "stat %x, msci st3 %x,"
1750 "rxhind %d, cda %x, eda %x.\n",
1754 sc->sca->msci[sc->scachan].st3,
1757 DMAC_RXCH(sc->scachan)].cda,
1759 DMAC_RXCH(sc->scachan)].eda));
1766 * All DMA interrupts come here.
1768 * Each channel has two interrupts.
1769 * Interrupt A for errors and Interrupt B for normal stuff like end
1770 * of transmit or receive dmas.
1773 ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1)
1776 u_char dotxstart = isr1;
1778 struct ar_softc *sc;
1782 sca = hc->sca[scano];
1785 * Shortcut if there is no interrupts for dma channel 0 or 1
1787 if((isr1 & 0x0F) == 0) {
1793 sc = &hc->sc[mch + (NCHAN * scano)];
1799 dmac = &sca->dmac[DMAC_TXCH(mch)];
1801 if(hc->bustype == AR_BUS_ISA)
1802 ARC_SET_SCA(hc, scano);
1807 /* Counter overflow */
1808 if(dsr & SCA_DSR_COF) {
1809 printf("ar%d: TX DMA Counter overflow, "
1810 "txpacket no %lu.\n",
1813 SC2IFP(sc)->if_opackets);
1814 SC2IFP(sc)->if_oerrors++;
1815 #else /* NETGRAPH */
1818 #endif /* NETGRAPH */
1821 /* Buffer overflow */
1822 if(dsr & SCA_DSR_BOF) {
1823 printf("ar%d: TX DMA Buffer overflow, "
1824 "txpacket no %lu, dsr %02x, "
1825 "cda %04x, eda %04x.\n",
1828 SC2IFP(sc)->if_opackets,
1829 #else /* NETGRAPH */
1831 #endif /* NETGRAPH */
1836 SC2IFP(sc)->if_oerrors++;
1837 #else /* NETGRAPH */
1839 #endif /* NETGRAPH */
1842 /* End of Transfer */
1843 if(dsr & SCA_DSR_EOT) {
1845 * This should be the most common case.
1847 * Clear the IFF_DRV_OACTIVE flag.
1849 * Call arstart to start a new transmit if
1850 * there is data to transmit.
1854 SC2IFP(sc)->if_drv_flags &= ~IFF_DRV_OACTIVE;
1855 SC2IFP(sc)->if_timer = 0;
1856 #else /* NETGRAPH */
1857 /* XXX SC2IFP(sc)->if_drv_flags &= ~IFF_DRV_OACTIVE; */
1858 sc->out_dog = 0; /* XXX */
1859 #endif /* NETGRAPH */
1861 if(sc->txb_inuse && --sc->txb_inuse)
1870 dmac = &sca->dmac[DMAC_RXCH(mch)];
1872 if(hc->bustype == AR_BUS_ISA)
1873 ARC_SET_SCA(hc, scano);
1878 TRC(printf("AR: RX DSR %x\n", dsr));
1881 if(dsr & SCA_DSR_EOM) {
1882 TRC(int tt = SC2IFP(sc)->if_ipackets;)
1883 TRC(int ind = sc->rxhind;)
1887 #define IPACKETS SC2IFP(sc)->if_ipackets
1888 #else /* NETGRAPH */
1889 #define IPACKETS sc->ipackets
1890 #endif /* NETGRAPH */
1891 TRC(if(tt == IPACKETS) {
1892 sca_descriptor *rxdesc;
1895 if(hc->bustype == AR_BUS_ISA)
1896 ARC_SET_SCA(hc, scano);
1897 printf("AR: RXINTR isr1 %x, dsr %x, "
1898 "no data %d pkts, orxhind %d.\n",
1903 printf("AR: rxdesc %x, rxstart %x, "
1904 "rxend %x, rxhind %d, "
1911 printf("AR: cda %x, eda %x.\n",
1915 if(sc->hc->bustype == AR_BUS_ISA)
1918 rxdesc = (sca_descriptor *)
1919 (sc->hc->mem_start +
1920 (sc->rxdesc & sc->hc->winmsk));
1921 rxdesc = &rxdesc[sc->rxhind];
1922 for(i=0;i<3;i++,rxdesc++)
1923 printf("AR: rxdesc->stat %x, "
1930 /* Counter overflow */
1931 if(dsr & SCA_DSR_COF) {
1932 printf("ar%d: RX DMA Counter overflow, "
1936 SC2IFP(sc)->if_ipackets);
1937 SC2IFP(sc)->if_ierrors++;
1938 #else /* NETGRAPH */
1941 #endif /* NETGRAPH */
1944 /* Buffer overflow */
1945 if(dsr & SCA_DSR_BOF) {
1946 if(hc->bustype == AR_BUS_ISA)
1947 ARC_SET_SCA(hc, scano);
1948 printf("ar%d: RX DMA Buffer overflow, "
1949 "rxpkts %lu, rxind %d, "
1950 "cda %x, eda %x, dsr %x.\n",
1953 SC2IFP(sc)->if_ipackets,
1954 #else /* NETGRAPH */
1956 #endif /* NETGRAPH */
1962 * Make sure we eat as many as possible.
1963 * Then get the system running again.
1965 ar_eat_packet(sc, 0);
1967 SC2IFP(sc)->if_ierrors++;
1968 #else /* NETGRAPH */
1970 #endif /* NETGRAPH */
1971 if(hc->bustype == AR_BUS_ISA)
1972 ARC_SET_SCA(hc, scano);
1973 sca->msci[mch].cmd = SCA_CMD_RXMSGREJ;
1974 dmac->dsr = SCA_DSR_DE;
1976 TRC(printf("ar%d: RX DMA Buffer overflow, "
1977 "rxpkts %lu, rxind %d, "
1978 "cda %x, eda %x, dsr %x. After\n",
1980 SC2IFP(sc)->if_ipackets,
1987 /* End of Transfer */
1988 if(dsr & SCA_DSR_EOT) {
1990 * If this happen, it means that we are
1991 * receiving faster than what the processor
1994 * XXX We should enable the dma again.
1996 printf("ar%d: RX End of transfer, rxpkts %lu.\n",
1999 SC2IFP(sc)->if_ipackets);
2000 SC2IFP(sc)->if_ierrors++;
2001 #else /* NETGRAPH */
2004 #endif /* NETGRAPH */
2011 }while((mch<NCHAN) && isr1);
2014 * Now that we have done all the urgent things, see if we
2015 * can fill the transmit buffers.
2017 for(mch = 0; mch < NCHAN; mch++) {
2018 if(dotxstart & 0x0C) {
2019 sc = &hc->sc[mch + (NCHAN * scano)];
2021 arstart(SC2IFP(sc));
2022 #else /* NETGRAPH */
2024 #endif /* NETGRAPH */
2031 ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0)
2033 printf("arc%d: ARINTR: MSCI\n", hc->cunit);
2037 ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2)
2039 printf("arc%d: ARINTR: TIMER\n", hc->cunit);
2044 /*****************************************
2045 * Device timeout/watchdog routine.
2046 * called once per second.
2047 * checks to see that if activity was expected, that it hapenned.
2048 * At present we only look to see if expected output was completed.
2051 ngar_watchdog_frame(void * arg)
2053 struct ar_softc * sc = arg;
2057 if(sc->running == 0)
2058 return; /* if we are not running let timeouts die */
2060 * calculate the apparent throughputs
2064 speed = sc->inbytes - sc->lastinbytes;
2065 sc->lastinbytes = sc->inbytes;
2066 if ( sc->inrate < speed )
2068 speed = sc->outbytes - sc->lastoutbytes;
2069 sc->lastoutbytes = sc->outbytes;
2070 if ( sc->outrate < speed )
2071 sc->outrate = speed;
2075 if ((sc->inlast > QUITE_A_WHILE)
2076 && (sc->out_deficit > LOTS_OF_PACKETS)) {
2077 log(LOG_ERR, "ar%d: No response from remote end\n", sc->unit);
2081 sc->inlast = sc->out_deficit = 0;
2083 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2084 if (sc->out_dog == 0) {
2085 log(LOG_ERR, "ar%d: Transmit failure.. no clock?\n",
2094 sc->inlast = sc->out_deficit = 0;
2099 sc->handle = timeout(ngar_watchdog_frame, sc, hz);
2102 /***********************************************************************
2103 * This section contains the methods for the Netgraph interface
2104 ***********************************************************************/
2106 * It is not possible or allowable to create a node of this type.
2107 * If the hardware exists, it will already have created it.
2110 ngar_constructor(node_p node)
2116 * give our ok for a hook to be added...
2117 * If we are not running this should kick the device into life.
2118 * The hook's private info points to our stash of info about that
2122 ngar_newhook(node_p node, hook_p hook, const char *name)
2124 struct ar_softc * sc = NG_NODE_PRIVATE(node);
2127 * check if it's our friend the debug hook
2129 if (strcmp(name, NG_AR_HOOK_DEBUG) == 0) {
2130 NG_HOOK_SET_PRIVATE(hook, NULL); /* paranoid */
2131 sc->debug_hook = hook;
2136 * Check for raw mode hook.
2138 if (strcmp(name, NG_AR_HOOK_RAW) != 0) {
2141 NG_HOOK_SET_PRIVATE(hook, sc);
2149 * incoming messages.
2150 * Just respond to the generic TEXT_STATUS message
2153 ngar_rcvmsg(node_p node, item_p item, hook_p lasthook)
2155 struct ar_softc * sc;
2156 struct ng_mesg *resp = NULL;
2158 struct ng_mesg *msg;
2160 NGI_GET_MSG(item, msg);
2161 sc = NG_NODE_PRIVATE(node);
2162 switch (msg->header.typecookie) {
2166 case NGM_GENERIC_COOKIE:
2167 switch(msg->header.cmd) {
2168 case NGM_TEXT_STATUS: {
2172 int resplen = sizeof(struct ng_mesg) + 512;
2173 NG_MKRESPONSE(resp, msg, resplen, M_NOWAIT);
2179 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
2180 "highest rate seen: %ld B/S in, %ld B/S out\n",
2181 sc->inbytes, sc->outbytes,
2182 sc->inrate, sc->outrate);
2183 pos += sprintf(arg + pos,
2184 "%ld output errors\n",
2186 pos += sprintf(arg + pos,
2187 "ierrors = %ld, %ld, %ld, %ld\n",
2193 resp->header.arglen = pos + 1;
2205 /* Take care of synchronous response, if any */
2206 NG_RESPOND_MSG(error, node, item, resp);
2212 * get data from another node and transmit it to the correct channel
2215 ngar_rcvdata(hook_p hook, item_p item)
2219 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
2220 struct ifqueue *xmitq_p;
2222 struct ng_tag_prio *ptag;
2227 * data doesn't come in from just anywhere (e.g control hook)
2229 if ( NG_HOOK_PRIVATE(hook) == NULL) {
2235 * Now queue the data for when it can be sent
2237 if ((ptag = (struct ng_tag_prio *)m_tag_locate(m, NGM_GENERIC_COOKIE,
2238 NG_TAG_PRIO, NULL)) != NULL && (ptag->priority > NG_PRIO_CUTOFF) )
2239 xmitq_p = (&sc->xmitq_hipri);
2241 xmitq_p = (&sc->xmitq);
2245 if (_IF_QFULL(xmitq_p)) {
2252 _IF_ENQUEUE(xmitq_p, m);
2260 * It was an error case.
2261 * check if we need to free the mbuf, and then return the error
2268 * do local shutdown processing..
2269 * this node will refuse to go away, unless the hardware says to..
2270 * don't unref the node, or remove our name. just clear our links up.
2273 ngar_shutdown(node_p node)
2275 struct ar_softc * sc = NG_NODE_PRIVATE(node);
2278 NG_NODE_UNREF(node);
2279 /* XXX need to drain the output queues! */
2281 /* The node is dead, long live the node! */
2282 /* stolen from the attach routine */
2283 if (ng_make_node_common(&typestruct, &sc->node) != 0)
2285 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
2286 if (ng_name_node(sc->node, sc->nodename)) {
2288 printf("node naming failed\n");
2289 NG_NODE_UNREF(sc->node); /* node dissappears */
2292 NG_NODE_SET_PRIVATE(sc->node, sc);
2297 /* already linked */
2299 ngar_connect(hook_p hook)
2301 /* probably not at splnet, force outward queueing */
2302 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook));
2303 /* be really amiable and just say "YUP that's OK by me! " */
2308 * notify on hook disconnection (destruction)
2310 * Invalidate the private data associated with this dlci.
2311 * For this type, removal of the last link resets tries to destroy the node.
2312 * As the device still exists, the shutdown method will not actually
2313 * destroy the node, but reset the device and leave it 'fresh' :)
2315 * The node removal code will remove all references except that owned by the
2319 ngar_disconnect(hook_p hook)
2321 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
2324 * If it's the data hook, then free resources etc.
2326 if (NG_HOOK_PRIVATE(hook)) {
2329 if (sc->datahooks == 0)
2333 sc->debug_hook = NULL;
2337 #endif /* NETGRAPH */
2340 ********************************* END ************************************