1 /**************************************************************************
3 Copyright (c) 2007-2008, Chelsio Inc.
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
30 ***************************************************************************/
31 #ifndef __CHELSIO_COMMON_H
32 #define __CHELSIO_COMMON_H
35 #include <cxgb_osdep.h>
37 #include <dev/cxgb/cxgb_osdep.h>
41 MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */
42 EEPROMSIZE = 8192, /* Serial EEPROM size */
43 SERNUM_LEN = 16, /* Serial # length */
44 ECNUM_LEN = 16, /* EC # length */
45 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
46 TCB_SIZE = 128, /* TCB size */
47 NMTUS = 16, /* size of MTU table */
48 NCCTRL_WIN = 32, /* # of congestion control windows */
49 NTX_SCHED = 8, /* # of HW Tx scheduling queues */
50 PROTO_SRAM_LINES = 128, /* size of protocol sram */
51 EXACT_ADDR_FILTERS = 8, /* # of HW exact match filters */
54 #define MAX_RX_COALESCING_LEN 12288U
59 PAUSE_AUTONEG = 1 << 2
63 SUPPORTED_IRQ = 1 << 24
66 enum { /* adapter interrupt-maintained statistics */
71 IRQ_NUM_STATS /* keep last */
80 #define S_TP_VERSION_MAJOR 16
81 #define M_TP_VERSION_MAJOR 0xFF
82 #define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR)
83 #define G_TP_VERSION_MAJOR(x) \
84 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
86 #define S_TP_VERSION_MINOR 8
87 #define M_TP_VERSION_MINOR 0xFF
88 #define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR)
89 #define G_TP_VERSION_MINOR(x) \
90 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR)
92 #define S_TP_VERSION_MICRO 0
93 #define M_TP_VERSION_MICRO 0xFF
94 #define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO)
95 #define G_TP_VERSION_MICRO(x) \
96 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
100 FW_VERSION_MINOR = 0,
105 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
106 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
107 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
110 enum sge_context_type { /* SGE egress context types */
118 AN_PKT_SIZE = 32, /* async notification packet size */
119 IMMED_PKT_SIZE = 48 /* packet size for immediate data */
122 struct sg_ent { /* SGE scatter/gather entry */
127 #ifndef SGE_NUM_GENBITS
129 # define SGE_NUM_GENBITS 2
132 #define TX_DESC_FLITS 16U
133 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
135 #define MAX_PHYINTRS 4
140 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr,
141 int reg_addr, unsigned int *val);
142 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr,
143 int reg_addr, unsigned int val);
146 struct adapter_info {
147 unsigned char nports0; /* # of ports on channel 0 */
148 unsigned char nports1; /* # of ports on channel 1 */
149 unsigned char phy_base_addr; /* MDIO PHY base address */
150 unsigned char mdien:1;
151 unsigned char mdiinv:1;
152 unsigned int gpio_out; /* GPIO output settings */
153 unsigned char gpio_intr[MAX_PHYINTRS]; /* GPIO PHY IRQ pins */
154 unsigned long caps; /* adapter capabilities */
155 const struct mdio_ops *mdio_ops; /* MDIO operations */
156 const char *desc; /* product description */
160 unsigned long parity_err;
161 unsigned long active_rgn_full;
162 unsigned long nfa_srch_err;
163 unsigned long unknown_cmd;
164 unsigned long reqq_parity_err;
165 unsigned long dispq_parity_err;
166 unsigned long del_act_empty;
170 unsigned long corr_err;
171 unsigned long uncorr_err;
172 unsigned long parity_err;
173 unsigned long addr_err;
177 u64 tx_octets; /* total # of octets in good frames */
178 u64 tx_octets_bad; /* total # of octets in error frames */
179 u64 tx_frames; /* all good frames */
180 u64 tx_mcast_frames; /* good multicast frames */
181 u64 tx_bcast_frames; /* good broadcast frames */
182 u64 tx_pause; /* # of transmitted pause frames */
183 u64 tx_deferred; /* frames with deferred transmissions */
184 u64 tx_late_collisions; /* # of late collisions */
185 u64 tx_total_collisions; /* # of total collisions */
186 u64 tx_excess_collisions; /* frame errors from excessive collissions */
187 u64 tx_underrun; /* # of Tx FIFO underruns */
188 u64 tx_len_errs; /* # of Tx length errors */
189 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */
190 u64 tx_excess_deferral; /* # of frames with excessive deferral */
191 u64 tx_fcs_errs; /* # of frames with bad FCS */
193 u64 tx_frames_64; /* # of Tx frames in a particular range */
194 u64 tx_frames_65_127;
195 u64 tx_frames_128_255;
196 u64 tx_frames_256_511;
197 u64 tx_frames_512_1023;
198 u64 tx_frames_1024_1518;
199 u64 tx_frames_1519_max;
201 u64 rx_octets; /* total # of octets in good frames */
202 u64 rx_octets_bad; /* total # of octets in error frames */
203 u64 rx_frames; /* all good frames */
204 u64 rx_mcast_frames; /* good multicast frames */
205 u64 rx_bcast_frames; /* good broadcast frames */
206 u64 rx_pause; /* # of received pause frames */
207 u64 rx_fcs_errs; /* # of received frames with bad FCS */
208 u64 rx_align_errs; /* alignment errors */
209 u64 rx_symbol_errs; /* symbol errors */
210 u64 rx_data_errs; /* data errors */
211 u64 rx_sequence_errs; /* sequence errors */
212 u64 rx_runt; /* # of runt frames */
213 u64 rx_jabber; /* # of jabber frames */
214 u64 rx_short; /* # of short frames */
215 u64 rx_too_long; /* # of oversized frames */
216 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */
218 u64 rx_frames_64; /* # of Rx frames in a particular range */
219 u64 rx_frames_65_127;
220 u64 rx_frames_128_255;
221 u64 rx_frames_256_511;
222 u64 rx_frames_512_1023;
223 u64 rx_frames_1024_1518;
224 u64 rx_frames_1519_max;
226 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */
228 unsigned long tx_fifo_parity_err;
229 unsigned long rx_fifo_parity_err;
230 unsigned long tx_fifo_urun;
231 unsigned long rx_fifo_ovfl;
232 unsigned long serdes_signal_loss;
233 unsigned long xaui_pcs_ctc_err;
234 unsigned long xaui_pcs_align_change;
236 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
237 unsigned long num_resets; /* # times reset due to stuck TX */
240 struct tp_mib_stats {
243 u32 ipInHdrErrors_hi;
244 u32 ipInHdrErrors_lo;
245 u32 ipInAddrErrors_hi;
246 u32 ipInAddrErrors_lo;
247 u32 ipInUnknownProtos_hi;
248 u32 ipInUnknownProtos_lo;
253 u32 ipOutRequests_hi;
254 u32 ipOutRequests_lo;
255 u32 ipOutDiscards_hi;
256 u32 ipOutDiscards_lo;
257 u32 ipOutNoRoutes_hi;
258 u32 ipOutNoRoutes_lo;
276 u32 tcpRetransSeg_hi;
277 u32 tcpRetransSeg_lo;
285 unsigned int nchan; /* # of channels */
286 unsigned int pmrx_size; /* total PMRX capacity */
287 unsigned int pmtx_size; /* total PMTX capacity */
288 unsigned int cm_size; /* total CM capacity */
289 unsigned int chan_rx_size; /* per channel Rx size */
290 unsigned int chan_tx_size; /* per channel Tx size */
291 unsigned int rx_pg_size; /* Rx page size */
292 unsigned int tx_pg_size; /* Tx page size */
293 unsigned int rx_num_pgs; /* # of Rx pages */
294 unsigned int tx_num_pgs; /* # of Tx pages */
295 unsigned int ntimer_qs; /* # of timer queues */
296 unsigned int tre; /* log2 of core clocks per TP tick */
297 unsigned int dack_re; /* DACK timer resolution */
300 struct qset_params { /* SGE queue set parameters */
301 unsigned int polling; /* polling/interrupt service for rspq */
302 unsigned int lro; /* large receive offload */
303 unsigned int coalesce_usecs; /* irq coalescing timer */
304 unsigned int rspq_size; /* # of entries in response queue */
305 unsigned int fl_size; /* # of entries in regular free list */
306 unsigned int jumbo_size; /* # of entries in jumbo free list */
307 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
308 unsigned int cong_thres; /* FL congestion threshold */
309 unsigned int vector; /* Interrupt (line or vector) number */
313 unsigned int max_pkt_size; /* max offload pkt size */
314 struct qset_params qset[SGE_QSETS];
318 unsigned int mode; /* selects MC5 width */
319 unsigned int nservers; /* size of server region */
320 unsigned int nfilters; /* size of filter region */
321 unsigned int nroutes; /* size of routing region */
324 /* Default MC5 region sizes */
326 DEFAULT_NSERVERS = 512,
327 DEFAULT_NFILTERS = 128
330 /* MC5 modes, these must be non-0 */
332 MC5_MODE_144_BIT = 1,
336 /* MC5 min active region size */
337 enum { MC5_MIN_TIDS = 16 };
344 unsigned int mem_timing;
345 u8 sn[SERNUM_LEN + 1];
346 u8 ec[ECNUM_LEN + 1];
348 u8 port_type[MAX_NPORTS];
349 unsigned short xauicfg[2];
353 unsigned int vpd_cap_addr;
354 unsigned int pcie_cap_addr;
355 unsigned short speed;
357 unsigned char variant;
362 PCI_VARIANT_PCIX_MODE1_PARITY,
363 PCI_VARIANT_PCIX_MODE1_ECC,
364 PCI_VARIANT_PCIX_266_MODE2,
368 struct adapter_params {
369 struct sge_params sge;
370 struct mc5_params mc5;
372 struct vpd_params vpd;
373 struct pci_params pci;
375 const struct adapter_info *info;
377 #ifdef CONFIG_CHELSIO_T3_CORE
378 unsigned short mtus[NMTUS];
379 unsigned short a_wnd[NCCTRL_WIN];
380 unsigned short b_wnd[NCCTRL_WIN];
382 unsigned int nports; /* # of ethernet ports */
383 unsigned int chan_map; /* bitmap of in-use Tx channels */
384 unsigned int stats_update_period; /* MAC stats accumulation period */
385 unsigned int linkpoll_period; /* link poll period in 0.1s */
386 unsigned int rev; /* chip revision */
387 unsigned int offload;
390 enum { /* chip revisions */
397 struct trace_params {
415 unsigned int supported; /* link capabilities */
416 unsigned int advertising; /* advertised capabilities */
417 unsigned short requested_speed; /* speed user has requested */
418 unsigned short speed; /* actual link speed */
419 unsigned char requested_duplex; /* duplex user has requested */
420 unsigned char duplex; /* actual link duplex */
421 unsigned char requested_fc; /* flow control user has requested */
422 unsigned char fc; /* actual link flow control */
423 unsigned char autoneg; /* autonegotiating? */
424 unsigned int link_ok; /* link up? */
427 #define SPEED_INVALID 0xffff
428 #define DUPLEX_INVALID 0xff
432 unsigned int tcam_size;
433 unsigned char part_type;
434 unsigned char parity_enabled;
436 struct mc5_stats stats;
439 static inline unsigned int t3_mc5_size(const struct mc5 *p)
445 adapter_t *adapter; /* backpointer to adapter */
446 unsigned int size; /* memory size in bytes */
447 unsigned int width; /* MC7 interface width */
448 unsigned int offset; /* register address offset for MC7 instance */
449 const char *name; /* name of MC7 instance */
450 struct mc7_stats stats; /* MC7 statistics */
453 static inline unsigned int t3_mc7_size(const struct mc7 *p)
461 unsigned char nucast; /* # of address filters for unicast MACs */
462 unsigned char multiport; /* multiple ports connected to this MAC */
463 unsigned char ext_port; /* external MAC port */
464 unsigned char promisc_map; /* which external ports are promiscuous */
465 unsigned int tx_tcnt;
466 unsigned int tx_xcnt;
468 unsigned int rx_xcnt;
469 unsigned int rx_ocnt;
471 unsigned int toggle_cnt;
474 struct mac_stats stats;
478 MAC_DIRECTION_RX = 1,
479 MAC_DIRECTION_TX = 2,
480 MAC_RXFIFO_SIZE = 32768
483 /* IEEE 802.3 specified MDIO devices */
485 MDIO_DEV_PMA_PMD = 1,
494 /* LASI control and status registers */
496 RX_ALARM_CTRL = 0x9000,
497 TX_ALARM_CTRL = 0x9001,
499 RX_ALARM_STAT = 0x9003,
500 TX_ALARM_STAT = 0x9004,
504 /* PHY loopback direction */
510 /* PHY interrupt types */
512 cphy_cause_link_change = 1,
513 cphy_cause_fifo_error = 2,
514 cphy_cause_module_change = 4,
517 /* PHY module types */
524 phy_modtype_twinax_long,
530 int (*reset)(struct cphy *phy, int wait);
532 int (*intr_enable)(struct cphy *phy);
533 int (*intr_disable)(struct cphy *phy);
534 int (*intr_clear)(struct cphy *phy);
535 int (*intr_handler)(struct cphy *phy);
537 int (*autoneg_enable)(struct cphy *phy);
538 int (*autoneg_restart)(struct cphy *phy);
540 int (*advertise)(struct cphy *phy, unsigned int advertise_map);
541 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
542 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
543 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
544 int *duplex, int *fc);
545 int (*power_down)(struct cphy *phy, int enable);
550 u8 addr; /* PHY address */
551 u8 modtype; /* PHY module type */
552 short priv; /* scratch pad */
553 unsigned int caps; /* PHY capabilities */
554 adapter_t *adapter; /* associated adapter */
555 const char *desc; /* PHY description */
556 unsigned long fifo_errors; /* FIFO over/under-flows */
557 const struct cphy_ops *ops; /* PHY operations */
558 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
559 int reg_addr, unsigned int *val);
560 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr,
561 int reg_addr, unsigned int val);
564 /* Convenience MDIO read/write wrappers */
565 static inline int mdio_read(struct cphy *phy, int mmd, int reg,
568 return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);
571 static inline int mdio_write(struct cphy *phy, int mmd, int reg,
574 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
577 /* Convenience initializer */
578 static inline void cphy_init(struct cphy *phy, adapter_t *adapter,
579 int phy_addr, struct cphy_ops *phy_ops,
580 const struct mdio_ops *mdio_ops, unsigned int caps,
583 phy->addr = (u8)phy_addr;
585 phy->adapter = adapter;
589 phy->mdio_read = mdio_ops->read;
590 phy->mdio_write = mdio_ops->write;
594 /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */
595 #define MAC_STATS_ACCUM_SECS 180
597 /* The external MAC needs accumulation every 30 seconds */
598 #define VSC_STATS_ACCUM_SECS 30
600 #define XGM_REG(reg_addr, idx) \
601 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
603 struct addr_val_pair {
604 unsigned int reg_addr;
608 #ifdef CONFIG_DEFINED
609 #include <cxgb_adapter.h>
611 #include <dev/cxgb/cxgb_adapter.h>
614 #ifndef PCI_VENDOR_ID_CHELSIO
615 # define PCI_VENDOR_ID_CHELSIO 0x1425
618 #define for_each_port(adapter, iter) \
619 for (iter = 0; iter < (adapter)->params.nports; ++iter)
621 #define adapter_info(adap) ((adap)->params.info)
623 static inline int uses_xaui(const adapter_t *adap)
625 return adapter_info(adap)->caps & SUPPORTED_AUI;
628 static inline int is_10G(const adapter_t *adap)
630 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
633 static inline int is_offload(const adapter_t *adap)
635 #if defined(CONFIG_CHELSIO_T3_CORE)
636 return adap->params.offload;
642 static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
644 return adap->params.vpd.cclk / 1000;
647 static inline unsigned int dack_ticks_to_usec(const adapter_t *adap,
650 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
653 static inline unsigned int is_pcie(const adapter_t *adap)
655 return adap->params.pci.variant == PCI_VARIANT_PCIE;
658 void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val);
659 void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n,
660 unsigned int offset);
661 int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity,
662 int attempts, int delay, u32 *valp);
664 static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask,
665 int polarity, int attempts, int delay)
667 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
671 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
673 int t3_phy_reset(struct cphy *phy, int mmd, int wait);
674 int t3_phy_advertise(struct cphy *phy, unsigned int advert);
675 int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert);
676 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
677 int t3_phy_lasi_intr_enable(struct cphy *phy);
678 int t3_phy_lasi_intr_disable(struct cphy *phy);
679 int t3_phy_lasi_intr_clear(struct cphy *phy);
680 int t3_phy_lasi_intr_handler(struct cphy *phy);
682 void t3_intr_enable(adapter_t *adapter);
683 void t3_intr_disable(adapter_t *adapter);
684 void t3_intr_clear(adapter_t *adapter);
685 void t3_port_intr_enable(adapter_t *adapter, int idx);
686 void t3_port_intr_disable(adapter_t *adapter, int idx);
687 void t3_port_intr_clear(adapter_t *adapter, int idx);
688 int t3_slow_intr_handler(adapter_t *adapter);
689 int t3_phy_intr_handler(adapter_t *adapter);
691 void t3_link_changed(adapter_t *adapter, int port_id);
692 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
693 const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
694 int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
695 int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data);
696 int t3_seeprom_wp(adapter_t *adapter, int enable);
697 int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
698 u32 *data, int byte_oriented);
699 int t3_get_tp_version(adapter_t *adapter, u32 *vers);
700 int t3_check_tpsram_version(adapter_t *adapter, int *must_load);
701 int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size);
702 int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size);
703 int t3_get_fw_version(adapter_t *adapter, u32 *vers);
704 int t3_check_fw_version(adapter_t *adapter, int *must_load);
705 int t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size);
706 int t3_init_hw(adapter_t *adapter, u32 fw_params);
707 void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
708 void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
709 int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
710 int t3_reinit_adapter(adapter_t *adap);
711 void t3_led_ready(adapter_t *adapter);
712 void t3_fatal_err(adapter_t *adapter);
713 void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
714 void t3_enable_filters(adapter_t *adap);
715 void t3_tp_set_offload_mode(adapter_t *adap, int enable);
716 void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
718 int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);
719 int t3_set_proto_sram(adapter_t *adap, const u8 *data);
720 int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask);
721 void t3_port_failover(adapter_t *adapter, int port);
722 void t3_failover_done(adapter_t *adapter, int port);
723 void t3_failover_clear(adapter_t *adapter);
724 int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n,
726 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
729 int t3_mac_reset(struct cmac *mac);
730 void t3b_pcs_reset(struct cmac *mac);
731 int t3_mac_enable(struct cmac *mac, int which);
732 int t3_mac_disable(struct cmac *mac, int which);
733 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
734 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm);
735 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
736 int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n);
737 const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
738 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
740 int t3b2_mac_watchdog_task(struct cmac *mac);
742 void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode);
743 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
744 unsigned int nroutes);
745 void t3_mc5_intr_handler(struct mc5 *mc5);
746 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
749 #ifdef CONFIG_CHELSIO_T3_CORE
750 int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh);
751 void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size);
752 void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps);
753 void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS],
754 unsigned short alpha[NCCTRL_WIN],
755 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
756 void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]);
757 void t3_get_cong_cntl_tab(adapter_t *adap,
758 unsigned short incr[NMTUS][NCCTRL_WIN]);
759 void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
760 int filter_index, int invert, int enable);
761 int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched);
762 int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg);
763 void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps,
765 void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]);
766 void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals,
767 unsigned int start, unsigned int n);
770 void t3_sge_prep(adapter_t *adap, struct sge_params *p);
771 void t3_sge_init(adapter_t *adap, struct sge_params *p);
772 int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable,
773 enum sge_context_type type, int respq, u64 base_addr,
774 unsigned int size, unsigned int token, int gen,
776 int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable,
777 u64 base_addr, unsigned int size, unsigned int esize,
778 unsigned int cong_thres, int gen, unsigned int cidx);
779 int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx,
780 u64 base_addr, unsigned int size,
781 unsigned int fl_thres, int gen, unsigned int cidx);
782 int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr,
783 unsigned int size, int rspq, int ovfl_mode,
784 unsigned int credits, unsigned int credit_thres);
785 int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable);
786 int t3_sge_disable_fl(adapter_t *adapter, unsigned int id);
787 int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id);
788 int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id);
789 int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]);
790 int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]);
791 int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]);
792 int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]);
793 int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
794 unsigned int credits);
796 int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n);
797 int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n);
798 int t3_vsc7323_init(adapter_t *adap, int nports);
799 int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port);
800 int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port);
801 int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port);
802 int t3_vsc7323_enable(adapter_t *adap, int port, int which);
803 int t3_vsc7323_disable(adapter_t *adap, int port, int which);
804 const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac);
806 int t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
807 const struct mdio_ops *mdio_ops);
808 int t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
809 const struct mdio_ops *mdio_ops);
810 int t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
811 const struct mdio_ops *mdio_ops);
812 int t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
813 const struct mdio_ops *mdio_ops);
814 int t3_ael2005_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
815 const struct mdio_ops *mdio_ops);
816 int t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
817 const struct mdio_ops *mdio_ops);
818 int t3_tn1010_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
819 const struct mdio_ops *mdio_ops);
820 int t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
821 const struct mdio_ops *mdio_ops);
822 #endif /* __CHELSIO_COMMON_H */