2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN985 (www.admtek.com.tw)
47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985
48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
49 * Accton EN1217 (www.accton.com)
50 * Xircom X3201 (www.xircom.com)
52 * Conexant LANfinity (www.conexant.com)
53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com)
55 * Datasheets for the 21143 are available at developer.intel.com.
56 * Datasheets for the clone parts can be found at their respective sites.
57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
58 * The PNIC II is essentially a Macronix 98715A chip; the only difference
59 * worth noting is that its multicast hash table is only 128 bits wide
62 * Written by Bill Paul <wpaul@ee.columbia.edu>
63 * Electrical Engineering Department
64 * Columbia University, New York City
67 * The Intel 21143 is the successor to the DEC 21140. It is basically
68 * the same as the 21140 but with a few new features. The 21143 supports
69 * three kinds of media attachments:
71 * o MII port, for 10Mbps and 100Mbps support and NWAY
72 * autonegotiation provided by an external PHY.
73 * o SYM port, for symbol mode 100Mbps support.
77 * The 100Mbps SYM port and 10baseT port can be used together in
78 * combination with the internal NWAY support to create a 10/100
79 * autosensing configuration.
81 * Note that not all tulip workalikes are handled in this driver: we only
82 * deal with those which are relatively well behaved. The Winbond is
83 * handled separately due to its different register offsets and the
84 * special handling needed for its various bugs. The PNIC is handled
85 * here, but I'm not thrilled about it.
87 * All of the workalike chips use some form of MII transceiver support
88 * with the exception of the Macronix chips, which also have a SYM port.
89 * The ASIX AX88140A is also documented to have a SYM port, but all
90 * the cards I've seen use an MII transceiver, probably because the
91 * AX88140A doesn't support internal NWAY.
94 #ifdef HAVE_KERNEL_OPTION_HEADERS
95 #include "opt_device_polling.h"
98 #include <sys/param.h>
99 #include <sys/endian.h>
100 #include <sys/systm.h>
101 #include <sys/sockio.h>
102 #include <sys/mbuf.h>
103 #include <sys/malloc.h>
104 #include <sys/kernel.h>
105 #include <sys/module.h>
106 #include <sys/socket.h>
109 #include <net/if_arp.h>
110 #include <net/ethernet.h>
111 #include <net/if_dl.h>
112 #include <net/if_media.h>
113 #include <net/if_types.h>
114 #include <net/if_vlan_var.h>
118 #include <machine/bus.h>
119 #include <machine/resource.h>
121 #include <sys/rman.h>
123 #include <dev/mii/mii.h>
124 #include <dev/mii/miivar.h>
126 #include <dev/pci/pcireg.h>
127 #include <dev/pci/pcivar.h>
129 #define DC_USEIOSPACE
131 #include <dev/dc/if_dcreg.h>
134 #include <dev/ofw/openfirm.h>
135 #include <machine/ofw_machdep.h>
138 MODULE_DEPEND(dc, pci, 1, 1, 1);
139 MODULE_DEPEND(dc, ether, 1, 1, 1);
140 MODULE_DEPEND(dc, miibus, 1, 1, 1);
143 * "device miibus" is required in kernel config. See GENERIC if you get
146 #include "miibus_if.h"
149 * Various supported device vendors/types and their names.
151 static const struct dc_type dc_devs[] = {
152 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0,
153 "Intel 21143 10/100BaseTX" },
154 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0,
155 "Davicom DM9009 10/100BaseTX" },
156 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0,
157 "Davicom DM9100 10/100BaseTX" },
158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A,
159 "Davicom DM9102A 10/100BaseTX" },
160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0,
161 "Davicom DM9102 10/100BaseTX" },
162 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0,
163 "ADMtek AL981 10/100BaseTX" },
164 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0,
165 "ADMtek AN985 10/100BaseTX" },
166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0,
167 "ADMtek ADM9511 10/100BaseTX" },
168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0,
169 "ADMtek ADM9513 10/100BaseTX" },
170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511), 0,
171 "Netgear FA511 10/100BaseTX" },
172 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141,
173 "ASIX AX88141 10/100BaseTX" },
174 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0,
175 "ASIX AX88140A 10/100BaseTX" },
176 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A,
177 "Macronix 98713A 10/100BaseTX" },
178 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0,
179 "Macronix 98713 10/100BaseTX" },
180 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A,
181 "Compex RL100-TX 10/100BaseTX" },
182 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0,
183 "Compex RL100-TX 10/100BaseTX" },
184 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725,
185 "Macronix 98725 10/100BaseTX" },
186 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C,
187 "Macronix 98715AEC-C 10/100BaseTX" },
188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0,
189 "Macronix 98715/98715A 10/100BaseTX" },
190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0,
191 "Macronix 98727/98732 10/100BaseTX" },
192 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0,
193 "LC82C115 PNIC II 10/100BaseTX" },
194 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169,
195 "82c169 PNIC 10/100BaseTX" },
196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0,
197 "82c168 PNIC 10/100BaseTX" },
198 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0,
199 "Accton EN1217 10/100BaseTX" },
200 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0,
201 "Accton EN2242 MiniPCI 10/100BaseTX" },
202 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0,
203 "Xircom X3201 10/100BaseTX" },
204 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0,
205 "Neteasy DRP-32TXD Cardbus 10/100" },
206 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0,
207 "Abocom FE2500 10/100BaseTX" },
208 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0,
209 "Abocom FE2500MX 10/100BaseTX" },
210 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0,
211 "Conexant LANfinity MiniPCI 10/100BaseTX" },
212 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0,
213 "Hawking CB102 CardBus 10/100" },
214 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0,
215 "PlaneX FNW-3602-T CardBus 10/100" },
216 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0,
217 "3Com OfficeConnect 10/100B" },
218 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0,
219 "Microsoft MN-120 CardBus 10/100" },
220 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0,
221 "Microsoft MN-130 10/100" },
222 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0,
223 "Linksys PCMPC200 CardBus 10/100" },
224 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0,
225 "Linksys PCMPC200 CardBus 10/100" },
229 static int dc_probe(device_t);
230 static int dc_attach(device_t);
231 static int dc_detach(device_t);
232 static int dc_suspend(device_t);
233 static int dc_resume(device_t);
234 static const struct dc_type *dc_devtype(device_t);
235 static int dc_newbuf(struct dc_softc *, int, int);
236 static int dc_encap(struct dc_softc *, struct mbuf **);
237 static void dc_pnic_rx_bug_war(struct dc_softc *, int);
238 static int dc_rx_resync(struct dc_softc *);
239 static void dc_rxeof(struct dc_softc *);
240 static void dc_txeof(struct dc_softc *);
241 static void dc_tick(void *);
242 static void dc_tx_underrun(struct dc_softc *);
243 static void dc_intr(void *);
244 static void dc_start(struct ifnet *);
245 static void dc_start_locked(struct ifnet *);
246 static int dc_ioctl(struct ifnet *, u_long, caddr_t);
247 static void dc_init(void *);
248 static void dc_init_locked(struct dc_softc *);
249 static void dc_stop(struct dc_softc *);
250 static void dc_watchdog(void *);
251 static int dc_shutdown(device_t);
252 static int dc_ifmedia_upd(struct ifnet *);
253 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
255 static void dc_delay(struct dc_softc *);
256 static void dc_eeprom_idle(struct dc_softc *);
257 static void dc_eeprom_putbyte(struct dc_softc *, int);
258 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *);
259 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *);
260 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *);
261 static void dc_eeprom_width(struct dc_softc *);
262 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
264 static void dc_mii_writebit(struct dc_softc *, int);
265 static int dc_mii_readbit(struct dc_softc *);
266 static void dc_mii_sync(struct dc_softc *);
267 static void dc_mii_send(struct dc_softc *, u_int32_t, int);
268 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *);
269 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *);
270 static int dc_miibus_readreg(device_t, int, int);
271 static int dc_miibus_writereg(device_t, int, int, int);
272 static void dc_miibus_statchg(device_t);
273 static void dc_miibus_mediainit(device_t);
275 static void dc_setcfg(struct dc_softc *, int);
276 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *);
277 static uint32_t dc_mchash_be(const uint8_t *);
278 static void dc_setfilt_21143(struct dc_softc *);
279 static void dc_setfilt_asix(struct dc_softc *);
280 static void dc_setfilt_admtek(struct dc_softc *);
281 static void dc_setfilt_xircom(struct dc_softc *);
283 static void dc_setfilt(struct dc_softc *);
285 static void dc_reset(struct dc_softc *);
286 static int dc_list_rx_init(struct dc_softc *);
287 static int dc_list_tx_init(struct dc_softc *);
289 static void dc_read_srom(struct dc_softc *, int);
290 static void dc_parse_21143_srom(struct dc_softc *);
291 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
292 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
293 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
294 static void dc_apply_fixup(struct dc_softc *, int);
297 #define DC_RES SYS_RES_IOPORT
298 #define DC_RID DC_PCI_CFBIO
300 #define DC_RES SYS_RES_MEMORY
301 #define DC_RID DC_PCI_CFBMA
304 static device_method_t dc_methods[] = {
305 /* Device interface */
306 DEVMETHOD(device_probe, dc_probe),
307 DEVMETHOD(device_attach, dc_attach),
308 DEVMETHOD(device_detach, dc_detach),
309 DEVMETHOD(device_suspend, dc_suspend),
310 DEVMETHOD(device_resume, dc_resume),
311 DEVMETHOD(device_shutdown, dc_shutdown),
314 DEVMETHOD(bus_print_child, bus_generic_print_child),
315 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
318 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
319 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
320 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
321 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
326 static driver_t dc_driver = {
329 sizeof(struct dc_softc)
332 static devclass_t dc_devclass;
334 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0);
335 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0);
336 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
338 #define DC_SETBIT(sc, reg, x) \
339 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
341 #define DC_CLRBIT(sc, reg, x) \
342 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
344 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
345 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
348 dc_delay(struct dc_softc *sc)
352 for (idx = (300 / 33) + 1; idx > 0; idx--)
353 CSR_READ_4(sc, DC_BUSCTL);
357 dc_eeprom_width(struct dc_softc *sc)
361 /* Force EEPROM to idle state. */
364 /* Enter EEPROM access mode. */
365 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
367 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
369 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
371 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
376 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
378 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
380 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
382 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
386 for (i = 1; i <= 12; i++) {
387 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
389 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
390 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
394 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
398 /* Turn off EEPROM access mode. */
406 /* Enter EEPROM access mode. */
407 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
409 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
411 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
413 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
416 /* Turn off EEPROM access mode. */
421 dc_eeprom_idle(struct dc_softc *sc)
425 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
427 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
429 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
431 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
434 for (i = 0; i < 25; i++) {
435 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
437 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
441 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
443 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
445 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
449 * Send a read command and address to the EEPROM, check for ACK.
452 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
456 d = DC_EECMD_READ >> 6;
459 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
461 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
463 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
465 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
470 * Feed in each bit and strobe the clock.
472 for (i = sc->dc_romwidth; i--;) {
473 if (addr & (1 << i)) {
474 SIO_SET(DC_SIO_EE_DATAIN);
476 SIO_CLR(DC_SIO_EE_DATAIN);
479 SIO_SET(DC_SIO_EE_CLK);
481 SIO_CLR(DC_SIO_EE_CLK);
487 * Read a word of data stored in the EEPROM at address 'addr.'
488 * The PNIC 82c168/82c169 has its own non-standard way to read
492 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
497 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
499 for (i = 0; i < DC_TIMEOUT; i++) {
501 r = CSR_READ_4(sc, DC_SIO);
502 if (!(r & DC_PN_SIOCTL_BUSY)) {
503 *dest = (u_int16_t)(r & 0xFFFF);
510 * Read a word of data stored in the EEPROM at address 'addr.'
511 * The Xircom X3201 has its own non-standard way to read
515 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
518 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
521 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
522 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
524 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
525 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
527 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
531 * Read a word of data stored in the EEPROM at address 'addr.'
534 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
539 /* Force EEPROM to idle state. */
542 /* Enter EEPROM access mode. */
543 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
545 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
547 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
549 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
553 * Send address of word we want to read.
555 dc_eeprom_putbyte(sc, addr);
558 * Start reading bits from EEPROM.
560 for (i = 0x8000; i; i >>= 1) {
561 SIO_SET(DC_SIO_EE_CLK);
563 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
566 SIO_CLR(DC_SIO_EE_CLK);
570 /* Turn off EEPROM access mode. */
577 * Read a sequence of words from the EEPROM.
580 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
583 u_int16_t word = 0, *ptr;
585 for (i = 0; i < cnt; i++) {
587 dc_eeprom_getword_pnic(sc, off + i, &word);
588 else if (DC_IS_XIRCOM(sc))
589 dc_eeprom_getword_xircom(sc, off + i, &word);
591 dc_eeprom_getword(sc, off + i, &word);
592 ptr = (u_int16_t *)(dest + (i * 2));
594 *ptr = be16toh(word);
596 *ptr = le16toh(word);
601 * The following two routines are taken from the Macronix 98713
602 * Application Notes pp.19-21.
605 * Write a bit to the MII bus.
608 dc_mii_writebit(struct dc_softc *sc, int bit)
612 reg = DC_SIO_ROMCTL_WRITE | (bit != 0 ? DC_SIO_MII_DATAOUT : 0);
613 CSR_WRITE_4(sc, DC_SIO, reg);
614 CSR_BARRIER_4(sc, DC_SIO,
615 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
618 CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK);
619 CSR_BARRIER_4(sc, DC_SIO,
620 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
622 CSR_WRITE_4(sc, DC_SIO, reg);
623 CSR_BARRIER_4(sc, DC_SIO,
624 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
629 * Read a bit from the MII bus.
632 dc_mii_readbit(struct dc_softc *sc)
636 reg = DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR;
637 CSR_WRITE_4(sc, DC_SIO, reg);
638 CSR_BARRIER_4(sc, DC_SIO,
639 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
641 (void)CSR_READ_4(sc, DC_SIO);
642 CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK);
643 CSR_BARRIER_4(sc, DC_SIO,
644 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
646 CSR_WRITE_4(sc, DC_SIO, reg);
647 CSR_BARRIER_4(sc, DC_SIO,
648 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
650 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
657 * Sync the PHYs by setting data bit and strobing the clock 32 times.
660 dc_mii_sync(struct dc_softc *sc)
664 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
665 CSR_BARRIER_4(sc, DC_SIO,
666 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
669 for (i = 0; i < 32; i++)
670 dc_mii_writebit(sc, 1);
674 * Clock a series of bits through the MII.
677 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
681 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
682 dc_mii_writebit(sc, bits & i);
686 * Read an PHY register through the MII.
689 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
694 * Set up frame for RX.
696 frame->mii_stdelim = DC_MII_STARTDELIM;
697 frame->mii_opcode = DC_MII_READOP;
705 * Send command/address info.
707 dc_mii_send(sc, frame->mii_stdelim, 2);
708 dc_mii_send(sc, frame->mii_opcode, 2);
709 dc_mii_send(sc, frame->mii_phyaddr, 5);
710 dc_mii_send(sc, frame->mii_regaddr, 5);
713 * Now try reading data bits. If the turnaround failed, we still
714 * need to clock through 16 cycles to keep the PHY(s) in sync.
716 frame->mii_turnaround = dc_mii_readbit(sc);
717 if (frame->mii_turnaround != 0) {
718 for (i = 0; i < 16; i++)
722 for (i = 0x8000; i; i >>= 1) {
723 if (dc_mii_readbit(sc))
724 frame->mii_data |= i;
729 /* Clock the idle bits. */
730 dc_mii_writebit(sc, 0);
731 dc_mii_writebit(sc, 0);
733 if (frame->mii_turnaround != 0)
739 * Write to a PHY register through the MII.
742 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
746 * Set up frame for TX.
748 frame->mii_stdelim = DC_MII_STARTDELIM;
749 frame->mii_opcode = DC_MII_WRITEOP;
750 frame->mii_turnaround = DC_MII_TURNAROUND;
757 dc_mii_send(sc, frame->mii_stdelim, 2);
758 dc_mii_send(sc, frame->mii_opcode, 2);
759 dc_mii_send(sc, frame->mii_phyaddr, 5);
760 dc_mii_send(sc, frame->mii_regaddr, 5);
761 dc_mii_send(sc, frame->mii_turnaround, 2);
762 dc_mii_send(sc, frame->mii_data, 16);
764 /* Clock the idle bits. */
765 dc_mii_writebit(sc, 0);
766 dc_mii_writebit(sc, 0);
772 dc_miibus_readreg(device_t dev, int phy, int reg)
774 struct dc_mii_frame frame;
776 int i, rval, phy_reg = 0;
778 sc = device_get_softc(dev);
779 bzero(&frame, sizeof(frame));
782 * Note: both the AL981 and AN985 have internal PHYs,
783 * however the AL981 provides direct access to the PHY
784 * registers while the AN985 uses a serial MII interface.
785 * The AN985's MII interface is also buggy in that you
786 * can read from any MII address (0 to 31), but only address 1
787 * behaves normally. To deal with both cases, we pretend
788 * that the PHY is at MII address 1.
790 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
794 * Note: the ukphy probes of the RS7112 report a PHY at
795 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
796 * so we only respond to correct one.
798 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
801 if (sc->dc_pmode != DC_PMODE_MII) {
802 if (phy == (MII_NPHY - 1)) {
806 * Fake something to make the probe
807 * code think there's a PHY here.
809 return (BMSR_MEDIAMASK);
813 return (DC_VENDORID_LO);
814 return (DC_VENDORID_DEC);
818 return (DC_DEVICEID_82C168);
819 return (DC_DEVICEID_21143);
829 if (DC_IS_PNIC(sc)) {
830 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
831 (phy << 23) | (reg << 18));
832 for (i = 0; i < DC_TIMEOUT; i++) {
834 rval = CSR_READ_4(sc, DC_PN_MII);
835 if (!(rval & DC_PN_MII_BUSY)) {
837 return (rval == 0xFFFF ? 0 : rval);
843 if (DC_IS_COMET(sc)) {
846 phy_reg = DC_AL_BMCR;
849 phy_reg = DC_AL_BMSR;
852 phy_reg = DC_AL_VENID;
855 phy_reg = DC_AL_DEVID;
858 phy_reg = DC_AL_ANAR;
861 phy_reg = DC_AL_LPAR;
864 phy_reg = DC_AL_ANER;
867 device_printf(dev, "phy_read: bad phy register %x\n",
873 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
880 frame.mii_phyaddr = phy;
881 frame.mii_regaddr = reg;
882 if (sc->dc_type == DC_TYPE_98713) {
883 phy_reg = CSR_READ_4(sc, DC_NETCFG);
884 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
886 dc_mii_readreg(sc, &frame);
887 if (sc->dc_type == DC_TYPE_98713)
888 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
890 return (frame.mii_data);
894 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
897 struct dc_mii_frame frame;
900 sc = device_get_softc(dev);
901 bzero(&frame, sizeof(frame));
903 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
906 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
909 if (DC_IS_PNIC(sc)) {
910 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
911 (phy << 23) | (reg << 10) | data);
912 for (i = 0; i < DC_TIMEOUT; i++) {
913 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
919 if (DC_IS_COMET(sc)) {
922 phy_reg = DC_AL_BMCR;
925 phy_reg = DC_AL_BMSR;
928 phy_reg = DC_AL_VENID;
931 phy_reg = DC_AL_DEVID;
934 phy_reg = DC_AL_ANAR;
937 phy_reg = DC_AL_LPAR;
940 phy_reg = DC_AL_ANER;
943 device_printf(dev, "phy_write: bad phy register %x\n",
949 CSR_WRITE_4(sc, phy_reg, data);
953 frame.mii_phyaddr = phy;
954 frame.mii_regaddr = reg;
955 frame.mii_data = data;
957 if (sc->dc_type == DC_TYPE_98713) {
958 phy_reg = CSR_READ_4(sc, DC_NETCFG);
959 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
961 dc_mii_writereg(sc, &frame);
962 if (sc->dc_type == DC_TYPE_98713)
963 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
969 dc_miibus_statchg(device_t dev)
972 struct mii_data *mii;
975 sc = device_get_softc(dev);
976 if (DC_IS_ADMTEK(sc))
979 mii = device_get_softc(sc->dc_miibus);
980 ifm = &mii->mii_media;
981 if (DC_IS_DAVICOM(sc) &&
982 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
983 dc_setcfg(sc, ifm->ifm_media);
984 sc->dc_if_media = ifm->ifm_media;
986 dc_setcfg(sc, mii->mii_media_active);
987 sc->dc_if_media = mii->mii_media_active;
992 * Special support for DM9102A cards with HomePNA PHYs. Note:
993 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
994 * to be impossible to talk to the management interface of the DM9801
995 * PHY (its MDIO pin is not connected to anything). Consequently,
996 * the driver has to just 'know' about the additional mode and deal
997 * with it itself. *sigh*
1000 dc_miibus_mediainit(device_t dev)
1002 struct dc_softc *sc;
1003 struct mii_data *mii;
1004 struct ifmedia *ifm;
1007 rev = pci_get_revid(dev);
1009 sc = device_get_softc(dev);
1010 mii = device_get_softc(sc->dc_miibus);
1011 ifm = &mii->mii_media;
1013 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1014 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
1017 #define DC_BITS_512 9
1018 #define DC_BITS_128 7
1019 #define DC_BITS_64 6
1022 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
1026 /* Compute CRC for the address value. */
1027 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
1030 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1031 * chips is only 128 bits wide.
1033 if (sc->dc_flags & DC_128BIT_HASH)
1034 return (crc & ((1 << DC_BITS_128) - 1));
1036 /* The hash table on the MX98715BEC is only 64 bits wide. */
1037 if (sc->dc_flags & DC_64BIT_HASH)
1038 return (crc & ((1 << DC_BITS_64) - 1));
1040 /* Xircom's hash filtering table is different (read: weird) */
1041 /* Xircom uses the LEAST significant bits */
1042 if (DC_IS_XIRCOM(sc)) {
1043 if ((crc & 0x180) == 0x180)
1044 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
1046 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 +
1050 return (crc & ((1 << DC_BITS_512) - 1));
1054 * Calculate CRC of a multicast group address, return the lower 6 bits.
1057 dc_mchash_be(const uint8_t *addr)
1061 /* Compute CRC for the address value. */
1062 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
1064 /* Return the filter bit position. */
1065 return ((crc >> 26) & 0x0000003F);
1069 * 21143-style RX filter setup routine. Filter programming is done by
1070 * downloading a special setup frame into the TX engine. 21143, Macronix,
1071 * PNIC, PNIC II and Davicom chips are programmed this way.
1073 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1074 * address (our node address) and a 512-bit hash filter for multicast
1075 * frames. We also sneak the broadcast address into the hash filter since
1079 dc_setfilt_21143(struct dc_softc *sc)
1081 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
1082 struct dc_desc *sframe;
1084 struct ifmultiaddr *ifma;
1090 i = sc->dc_cdata.dc_tx_prod;
1091 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1092 sc->dc_cdata.dc_tx_cnt++;
1093 sframe = &sc->dc_ldata->dc_tx_list[i];
1094 sp = sc->dc_cdata.dc_sbuf;
1095 bzero(sp, DC_SFRAME_LEN);
1097 sframe->dc_data = htole32(sc->dc_saddr);
1098 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1099 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1101 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1103 /* If we want promiscuous mode, set the allframes bit. */
1104 if (ifp->if_flags & IFF_PROMISC)
1105 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1107 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1109 if (ifp->if_flags & IFF_ALLMULTI)
1110 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1112 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1115 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1116 if (ifma->ifma_addr->sa_family != AF_LINK)
1118 h = dc_mchash_le(sc,
1119 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1120 sp[h >> 4] |= htole32(1 << (h & 0xF));
1122 IF_ADDR_UNLOCK(ifp);
1124 if (ifp->if_flags & IFF_BROADCAST) {
1125 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1126 sp[h >> 4] |= htole32(1 << (h & 0xF));
1129 /* Set our MAC address. */
1130 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1131 sp[39] = DC_SP_MAC(eaddr[0]);
1132 sp[40] = DC_SP_MAC(eaddr[1]);
1133 sp[41] = DC_SP_MAC(eaddr[2]);
1135 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1136 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1139 * The PNIC takes an exceedingly long time to process its
1140 * setup frame; wait 10ms after posting the setup frame
1141 * before proceeding, just so it has time to swallow its
1146 sc->dc_wdog_timer = 5;
1150 dc_setfilt_admtek(struct dc_softc *sc)
1152 uint8_t eaddr[ETHER_ADDR_LEN];
1154 struct ifmultiaddr *ifma;
1156 u_int32_t hashes[2] = { 0, 0 };
1160 /* Init our MAC address. */
1161 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1162 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 |
1163 eaddr[1] << 8 | eaddr[0]);
1164 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]);
1166 /* If we want promiscuous mode, set the allframes bit. */
1167 if (ifp->if_flags & IFF_PROMISC)
1168 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1170 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1172 if (ifp->if_flags & IFF_ALLMULTI)
1173 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1175 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1177 /* First, zot all the existing hash bits. */
1178 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1179 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1182 * If we're already in promisc or allmulti mode, we
1183 * don't have to bother programming the multicast filter.
1185 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1188 /* Now program new ones. */
1190 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1191 if (ifma->ifma_addr->sa_family != AF_LINK)
1193 if (DC_IS_CENTAUR(sc))
1194 h = dc_mchash_le(sc,
1195 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1198 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1200 hashes[0] |= (1 << h);
1202 hashes[1] |= (1 << (h - 32));
1204 IF_ADDR_UNLOCK(ifp);
1206 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1207 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1211 dc_setfilt_asix(struct dc_softc *sc)
1213 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
1215 struct ifmultiaddr *ifma;
1217 u_int32_t hashes[2] = { 0, 0 };
1221 /* Init our MAC address. */
1222 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1223 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1224 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]);
1225 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1226 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]);
1228 /* If we want promiscuous mode, set the allframes bit. */
1229 if (ifp->if_flags & IFF_PROMISC)
1230 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1232 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1234 if (ifp->if_flags & IFF_ALLMULTI)
1235 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1237 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1240 * The ASIX chip has a special bit to enable reception
1241 * of broadcast frames.
1243 if (ifp->if_flags & IFF_BROADCAST)
1244 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1246 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1248 /* first, zot all the existing hash bits */
1249 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1250 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1251 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1252 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1255 * If we're already in promisc or allmulti mode, we
1256 * don't have to bother programming the multicast filter.
1258 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1261 /* now program new ones */
1263 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1264 if (ifma->ifma_addr->sa_family != AF_LINK)
1266 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1268 hashes[0] |= (1 << h);
1270 hashes[1] |= (1 << (h - 32));
1272 IF_ADDR_UNLOCK(ifp);
1274 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1275 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1276 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1277 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1281 dc_setfilt_xircom(struct dc_softc *sc)
1283 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
1285 struct ifmultiaddr *ifma;
1286 struct dc_desc *sframe;
1291 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1293 i = sc->dc_cdata.dc_tx_prod;
1294 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1295 sc->dc_cdata.dc_tx_cnt++;
1296 sframe = &sc->dc_ldata->dc_tx_list[i];
1297 sp = sc->dc_cdata.dc_sbuf;
1298 bzero(sp, DC_SFRAME_LEN);
1300 sframe->dc_data = htole32(sc->dc_saddr);
1301 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1302 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1304 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1306 /* If we want promiscuous mode, set the allframes bit. */
1307 if (ifp->if_flags & IFF_PROMISC)
1308 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1310 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1312 if (ifp->if_flags & IFF_ALLMULTI)
1313 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1315 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1318 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1319 if (ifma->ifma_addr->sa_family != AF_LINK)
1321 h = dc_mchash_le(sc,
1322 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1323 sp[h >> 4] |= htole32(1 << (h & 0xF));
1325 IF_ADDR_UNLOCK(ifp);
1327 if (ifp->if_flags & IFF_BROADCAST) {
1328 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1329 sp[h >> 4] |= htole32(1 << (h & 0xF));
1332 /* Set our MAC address. */
1333 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1334 sp[0] = DC_SP_MAC(eaddr[0]);
1335 sp[1] = DC_SP_MAC(eaddr[1]);
1336 sp[2] = DC_SP_MAC(eaddr[2]);
1338 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1339 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1340 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1341 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1342 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1349 sc->dc_wdog_timer = 5;
1353 dc_setfilt(struct dc_softc *sc)
1356 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1357 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1358 dc_setfilt_21143(sc);
1361 dc_setfilt_asix(sc);
1363 if (DC_IS_ADMTEK(sc))
1364 dc_setfilt_admtek(sc);
1366 if (DC_IS_XIRCOM(sc))
1367 dc_setfilt_xircom(sc);
1371 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in
1372 * the netconfig register, we first have to put the transmit and/or
1373 * receive logic in the idle state.
1376 dc_setcfg(struct dc_softc *sc, int media)
1378 int i, restart = 0, watchdogreg;
1381 if (IFM_SUBTYPE(media) == IFM_NONE)
1384 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {
1386 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1388 for (i = 0; i < DC_TIMEOUT; i++) {
1389 isr = CSR_READ_4(sc, DC_ISR);
1390 if (isr & DC_ISR_TX_IDLE &&
1391 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1392 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1397 if (i == DC_TIMEOUT) {
1398 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc))
1399 device_printf(sc->dc_dev,
1400 "%s: failed to force tx to idle state\n",
1402 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1403 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
1404 !DC_HAS_BROKEN_RXSTATE(sc))
1405 device_printf(sc->dc_dev,
1406 "%s: failed to force rx to idle state\n",
1411 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1412 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1413 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1414 if (sc->dc_pmode == DC_PMODE_MII) {
1415 if (DC_IS_INTEL(sc)) {
1416 /* There's a write enable bit here that reads as 1. */
1417 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1418 watchdogreg &= ~DC_WDOG_CTLWREN;
1419 watchdogreg |= DC_WDOG_JABBERDIS;
1420 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1422 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1424 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1425 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1426 if (sc->dc_type == DC_TYPE_98713)
1427 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1428 DC_NETCFG_SCRAMBLER));
1429 if (!DC_IS_DAVICOM(sc))
1430 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1431 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1432 if (DC_IS_INTEL(sc))
1433 dc_apply_fixup(sc, IFM_AUTO);
1435 if (DC_IS_PNIC(sc)) {
1436 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1437 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1438 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1440 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1441 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1442 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1443 if (DC_IS_INTEL(sc))
1445 (media & IFM_GMASK) == IFM_FDX ?
1446 IFM_100_TX | IFM_FDX : IFM_100_TX);
1450 if (IFM_SUBTYPE(media) == IFM_10_T) {
1451 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1452 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1453 if (sc->dc_pmode == DC_PMODE_MII) {
1454 /* There's a write enable bit here that reads as 1. */
1455 if (DC_IS_INTEL(sc)) {
1456 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1457 watchdogreg &= ~DC_WDOG_CTLWREN;
1458 watchdogreg |= DC_WDOG_JABBERDIS;
1459 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1461 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1463 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1464 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1465 if (sc->dc_type == DC_TYPE_98713)
1466 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1467 if (!DC_IS_DAVICOM(sc))
1468 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1469 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1470 if (DC_IS_INTEL(sc))
1471 dc_apply_fixup(sc, IFM_AUTO);
1473 if (DC_IS_PNIC(sc)) {
1474 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1475 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1476 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1478 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1479 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1480 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1481 if (DC_IS_INTEL(sc)) {
1482 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1483 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1484 if ((media & IFM_GMASK) == IFM_FDX)
1485 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1487 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1488 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1489 DC_CLRBIT(sc, DC_10BTCTRL,
1490 DC_TCTL_AUTONEGENBL);
1492 (media & IFM_GMASK) == IFM_FDX ?
1493 IFM_10_T | IFM_FDX : IFM_10_T);
1500 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1501 * PHY and we want HomePNA mode, set the portsel bit to turn
1502 * on the external MII port.
1504 if (DC_IS_DAVICOM(sc)) {
1505 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1506 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1509 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1513 if ((media & IFM_GMASK) == IFM_FDX) {
1514 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1515 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1516 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1518 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1519 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1520 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1524 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON);
1528 dc_reset(struct dc_softc *sc)
1532 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1534 for (i = 0; i < DC_TIMEOUT; i++) {
1536 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1540 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) ||
1541 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) {
1543 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1547 if (i == DC_TIMEOUT)
1548 device_printf(sc->dc_dev, "reset never completed!\n");
1550 /* Wait a little while for the chip to get its brains in order. */
1553 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1554 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1555 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1558 * Bring the SIA out of reset. In some cases, it looks
1559 * like failing to unreset the SIA soon enough gets it
1560 * into a state where it will never come out of reset
1561 * until we reset the whole chip again.
1563 if (DC_IS_INTEL(sc)) {
1564 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1565 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1566 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1570 static const struct dc_type *
1571 dc_devtype(device_t dev)
1573 const struct dc_type *t;
1578 devid = pci_get_devid(dev);
1579 rev = pci_get_revid(dev);
1581 while (t->dc_name != NULL) {
1582 if (devid == t->dc_devid && rev >= t->dc_minrev)
1591 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1592 * IDs against our list and return a device name if we find a match.
1593 * We do a little bit of extra work to identify the exact type of
1594 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1595 * but different revision IDs. The same is true for 98715/98715A
1596 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1597 * cases, the exact chip revision affects driver behavior.
1600 dc_probe(device_t dev)
1602 const struct dc_type *t;
1604 t = dc_devtype(dev);
1607 device_set_desc(dev, t->dc_name);
1608 return (BUS_PROBE_DEFAULT);
1615 dc_apply_fixup(struct dc_softc *sc, int media)
1617 struct dc_mediainfo *m;
1625 if (m->dc_media == media)
1633 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1634 reg = (p[0] | (p[1] << 8)) << 16;
1635 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1638 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1639 reg = (p[0] | (p[1] << 8)) << 16;
1640 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1645 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1647 struct dc_mediainfo *m;
1649 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1650 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) {
1651 case DC_SIA_CODE_10BT:
1652 m->dc_media = IFM_10_T;
1654 case DC_SIA_CODE_10BT_FDX:
1655 m->dc_media = IFM_10_T | IFM_FDX;
1657 case DC_SIA_CODE_10B2:
1658 m->dc_media = IFM_10_2;
1660 case DC_SIA_CODE_10B5:
1661 m->dc_media = IFM_10_5;
1668 * We need to ignore CSR13, CSR14, CSR15 for SIA mode.
1669 * Things apparently already work for cards that do
1670 * supply Media Specific Data.
1672 if (l->dc_sia_code & DC_SIA_CODE_EXT) {
1675 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1679 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1682 m->dc_next = sc->dc_mi;
1685 sc->dc_pmode = DC_PMODE_SIA;
1689 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1691 struct dc_mediainfo *m;
1693 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1694 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1695 m->dc_media = IFM_100_TX;
1697 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1698 m->dc_media = IFM_100_TX | IFM_FDX;
1701 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1703 m->dc_next = sc->dc_mi;
1706 sc->dc_pmode = DC_PMODE_SYM;
1710 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1712 struct dc_mediainfo *m;
1715 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1716 /* We abuse IFM_AUTO to represent MII. */
1717 m->dc_media = IFM_AUTO;
1718 m->dc_gp_len = l->dc_gpr_len;
1721 p += sizeof(struct dc_eblock_mii);
1723 p += 2 * l->dc_gpr_len;
1724 m->dc_reset_len = *p;
1726 m->dc_reset_ptr = p;
1728 m->dc_next = sc->dc_mi;
1733 dc_read_srom(struct dc_softc *sc, int bits)
1738 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1739 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1743 dc_parse_21143_srom(struct dc_softc *sc)
1745 struct dc_leaf_hdr *lhdr;
1746 struct dc_eblock_hdr *hdr;
1747 int have_mii, i, loff;
1751 loff = sc->dc_srom[27];
1752 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1755 ptr += sizeof(struct dc_leaf_hdr) - 1;
1757 * Look if we got a MII media block.
1759 for (i = 0; i < lhdr->dc_mcnt; i++) {
1760 hdr = (struct dc_eblock_hdr *)ptr;
1761 if (hdr->dc_type == DC_EBLOCK_MII)
1764 ptr += (hdr->dc_len & 0x7F);
1769 * Do the same thing again. Only use SIA and SYM media
1770 * blocks if no MII media block is available.
1773 ptr += sizeof(struct dc_leaf_hdr) - 1;
1774 for (i = 0; i < lhdr->dc_mcnt; i++) {
1775 hdr = (struct dc_eblock_hdr *)ptr;
1776 switch (hdr->dc_type) {
1778 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1782 dc_decode_leaf_sia(sc,
1783 (struct dc_eblock_sia *)hdr);
1787 dc_decode_leaf_sym(sc,
1788 (struct dc_eblock_sym *)hdr);
1791 /* Don't care. Yet. */
1794 ptr += (hdr->dc_len & 0x7F);
1800 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1805 ("%s: wrong number of segments (%d)", __func__, nseg));
1807 *paddr = segs->ds_addr;
1811 * Attach the interface. Allocate softc structures, do ifmedia
1812 * setup and ethernet/BPF attach.
1815 dc_attach(device_t dev)
1818 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
1820 struct dc_softc *sc;
1822 u_int32_t reg, revision;
1823 int error = 0, rid, mac_offset;
1827 sc = device_get_softc(dev);
1830 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1834 * Map control/status registers.
1836 pci_enable_busmaster(dev);
1839 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
1841 if (sc->dc_res == NULL) {
1842 device_printf(dev, "couldn't map ports/memory\n");
1847 sc->dc_btag = rman_get_bustag(sc->dc_res);
1848 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1850 /* Allocate interrupt. */
1852 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1853 RF_SHAREABLE | RF_ACTIVE);
1855 if (sc->dc_irq == NULL) {
1856 device_printf(dev, "couldn't map interrupt\n");
1861 /* Need this info to decide on a chip type. */
1862 sc->dc_info = dc_devtype(dev);
1863 revision = pci_get_revid(dev);
1865 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
1866 if (sc->dc_info->dc_devid !=
1867 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) &&
1868 sc->dc_info->dc_devid !=
1869 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201))
1870 dc_eeprom_width(sc);
1872 switch (sc->dc_info->dc_devid) {
1873 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143):
1874 sc->dc_type = DC_TYPE_21143;
1875 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1876 sc->dc_flags |= DC_REDUCED_MII_POLL;
1877 /* Save EEPROM contents so we can parse them later. */
1878 dc_read_srom(sc, sc->dc_romwidth);
1880 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009):
1881 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100):
1882 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102):
1883 sc->dc_type = DC_TYPE_DM9102;
1884 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS;
1885 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD;
1886 sc->dc_flags |= DC_TX_ALIGN;
1887 sc->dc_pmode = DC_PMODE_MII;
1889 /* Increase the latency timer value. */
1890 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1);
1892 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981):
1893 sc->dc_type = DC_TYPE_AL981;
1894 sc->dc_flags |= DC_TX_USE_TX_INTR;
1895 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1896 sc->dc_pmode = DC_PMODE_MII;
1897 dc_read_srom(sc, sc->dc_romwidth);
1899 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985):
1900 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511):
1901 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513):
1902 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD):
1903 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511):
1904 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500):
1905 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX):
1906 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242):
1907 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX):
1908 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T):
1909 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB):
1910 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120):
1911 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130):
1912 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08):
1913 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09):
1914 sc->dc_type = DC_TYPE_AN985;
1915 sc->dc_flags |= DC_64BIT_HASH;
1916 sc->dc_flags |= DC_TX_USE_TX_INTR;
1917 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1918 sc->dc_pmode = DC_PMODE_MII;
1919 /* Don't read SROM for - auto-loaded on reset */
1921 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713):
1922 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP):
1923 if (revision < DC_REVISION_98713A) {
1924 sc->dc_type = DC_TYPE_98713;
1926 if (revision >= DC_REVISION_98713A) {
1927 sc->dc_type = DC_TYPE_98713A;
1928 sc->dc_flags |= DC_21143_NWAY;
1930 sc->dc_flags |= DC_REDUCED_MII_POLL;
1931 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1933 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5):
1934 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217):
1936 * Macronix MX98715AEC-C/D/E parts have only a
1937 * 128-bit hash table. We need to deal with these
1938 * in the same manner as the PNIC II so that we
1939 * get the right number of bits out of the
1942 if (revision >= DC_REVISION_98715AEC_C &&
1943 revision < DC_REVISION_98725)
1944 sc->dc_flags |= DC_128BIT_HASH;
1945 sc->dc_type = DC_TYPE_987x5;
1946 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1947 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1949 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727):
1950 sc->dc_type = DC_TYPE_987x5;
1951 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1952 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1954 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115):
1955 sc->dc_type = DC_TYPE_PNICII;
1956 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH;
1957 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1959 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168):
1960 sc->dc_type = DC_TYPE_PNIC;
1961 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS;
1962 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1963 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
1964 if (revision < DC_REVISION_82C169)
1965 sc->dc_pmode = DC_PMODE_SYM;
1967 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A):
1968 sc->dc_type = DC_TYPE_ASIX;
1969 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG;
1970 sc->dc_flags |= DC_REDUCED_MII_POLL;
1971 sc->dc_pmode = DC_PMODE_MII;
1973 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201):
1974 sc->dc_type = DC_TYPE_XIRCOM;
1975 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
1978 * We don't actually need to coalesce, but we're doing
1979 * it to obtain a double word aligned buffer.
1980 * The DC_TX_COALESCE flag is required.
1982 sc->dc_pmode = DC_PMODE_MII;
1984 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112):
1985 sc->dc_type = DC_TYPE_CONEXANT;
1986 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1987 sc->dc_flags |= DC_REDUCED_MII_POLL;
1988 sc->dc_pmode = DC_PMODE_MII;
1989 dc_read_srom(sc, sc->dc_romwidth);
1992 device_printf(dev, "unknown device: %x\n",
1993 sc->dc_info->dc_devid);
1997 /* Save the cache line size. */
1998 if (DC_IS_DAVICOM(sc))
1999 sc->dc_cachesize = 0;
2001 sc->dc_cachesize = pci_get_cachelnsz(dev);
2003 /* Reset the adapter. */
2006 /* Take 21143 out of snooze mode */
2007 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2008 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2009 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
2010 pci_write_config(dev, DC_PCI_CFDD, command, 4);
2014 * Try to learn something about the supported media.
2015 * We know that ASIX and ADMtek and Davicom devices
2016 * will *always* be using MII media, so that's a no-brainer.
2017 * The tricky ones are the Macronix/PNIC II and the
2020 if (DC_IS_INTEL(sc))
2021 dc_parse_21143_srom(sc);
2022 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2023 if (sc->dc_type == DC_TYPE_98713)
2024 sc->dc_pmode = DC_PMODE_MII;
2026 sc->dc_pmode = DC_PMODE_SYM;
2027 } else if (!sc->dc_pmode)
2028 sc->dc_pmode = DC_PMODE_MII;
2031 * Get station address from the EEPROM.
2033 switch(sc->dc_type) {
2035 case DC_TYPE_98713A:
2037 case DC_TYPE_PNICII:
2038 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2039 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2040 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2043 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2045 case DC_TYPE_DM9102:
2046 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2049 * If this is an onboard dc(4) the station address read from
2050 * the EEPROM is all zero and we have to get it from the FCode.
2052 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0)
2053 OF_getetheraddr(dev, (caddr_t)&eaddr);
2058 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2062 reg = CSR_READ_4(sc, DC_AL_PAR0);
2063 mac = (uint8_t *)&eaddr[0];
2064 mac[0] = (reg >> 0) & 0xff;
2065 mac[1] = (reg >> 8) & 0xff;
2066 mac[2] = (reg >> 16) & 0xff;
2067 mac[3] = (reg >> 24) & 0xff;
2068 reg = CSR_READ_4(sc, DC_AL_PAR1);
2069 mac[4] = (reg >> 0) & 0xff;
2070 mac[5] = (reg >> 8) & 0xff;
2072 case DC_TYPE_CONEXANT:
2073 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr,
2076 case DC_TYPE_XIRCOM:
2077 /* The MAC comes from the CIS. */
2078 mac = pci_get_ether(dev);
2080 device_printf(dev, "No station address in CIS!\n");
2084 bcopy(mac, eaddr, ETHER_ADDR_LEN);
2087 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2091 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
2092 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0,
2093 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2094 sizeof(struct dc_list_data), 1, sizeof(struct dc_list_data),
2095 0, NULL, NULL, &sc->dc_ltag);
2097 device_printf(dev, "failed to allocate busdma tag\n");
2101 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata,
2102 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap);
2104 device_printf(dev, "failed to allocate DMA safe memory\n");
2108 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata,
2109 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr,
2112 device_printf(dev, "cannot get address of the descriptors\n");
2118 * Allocate a busdma tag and DMA safe memory for the multicast
2121 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0,
2122 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2123 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN,
2124 0, NULL, NULL, &sc->dc_stag);
2126 device_printf(dev, "failed to allocate busdma tag\n");
2130 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf,
2131 BUS_DMA_NOWAIT, &sc->dc_smap);
2133 device_printf(dev, "failed to allocate DMA safe memory\n");
2137 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf,
2138 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT);
2140 device_printf(dev, "cannot get address of the descriptors\n");
2145 /* Allocate a busdma tag for mbufs. */
2146 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
2147 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2148 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES,
2149 0, NULL, NULL, &sc->dc_mtag);
2151 device_printf(dev, "failed to allocate busdma tag\n");
2156 /* Create the TX/RX busdma maps. */
2157 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2158 error = bus_dmamap_create(sc->dc_mtag, 0,
2159 &sc->dc_cdata.dc_tx_map[i]);
2161 device_printf(dev, "failed to init TX ring\n");
2166 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2167 error = bus_dmamap_create(sc->dc_mtag, 0,
2168 &sc->dc_cdata.dc_rx_map[i]);
2170 device_printf(dev, "failed to init RX ring\n");
2175 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap);
2177 device_printf(dev, "failed to init RX ring\n");
2182 ifp = sc->dc_ifp = if_alloc(IFT_ETHER);
2184 device_printf(dev, "can not if_alloc()\n");
2189 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2190 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2191 ifp->if_ioctl = dc_ioctl;
2192 ifp->if_start = dc_start;
2193 ifp->if_init = dc_init;
2194 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2195 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1;
2196 IFQ_SET_READY(&ifp->if_snd);
2199 * Do MII setup. If this is a 21143, check for a PHY on the
2200 * MII bus after applying any necessary fixups to twiddle the
2201 * GPIO bits. If we don't end up finding a PHY, restore the
2202 * old selection (SIA only or SIA/SYM) and attach the dcphy
2205 if (DC_IS_INTEL(sc)) {
2206 dc_apply_fixup(sc, IFM_AUTO);
2208 sc->dc_pmode = DC_PMODE_MII;
2212 * Setup General Purpose port mode and data so the tulip can talk
2213 * to the MII. This needs to be done before mii_phy_probe so that
2214 * we can actually see them.
2216 if (DC_IS_XIRCOM(sc)) {
2217 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2218 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2220 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2221 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2225 error = mii_phy_probe(dev, &sc->dc_miibus,
2226 dc_ifmedia_upd, dc_ifmedia_sts);
2228 if (error && DC_IS_INTEL(sc)) {
2230 if (sc->dc_pmode != DC_PMODE_SIA)
2231 sc->dc_pmode = DC_PMODE_SYM;
2232 sc->dc_flags |= DC_21143_NWAY;
2233 mii_phy_probe(dev, &sc->dc_miibus,
2234 dc_ifmedia_upd, dc_ifmedia_sts);
2236 * For non-MII cards, we need to have the 21143
2237 * drive the LEDs. Except there are some systems
2238 * like the NEC VersaPro NoteBook PC which have no
2239 * LEDs, and twiddling these bits has adverse effects
2240 * on them. (I.e. you suddenly can't get a link.)
2242 if (!(pci_get_subvendor(dev) == 0x1033 &&
2243 pci_get_subdevice(dev) == 0x8028))
2244 sc->dc_flags |= DC_TULIP_LEDS;
2249 device_printf(dev, "MII without any PHY!\n");
2253 if (DC_IS_ADMTEK(sc)) {
2255 * Set automatic TX underrun recovery for the ADMtek chips
2257 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2261 * Tell the upper layer(s) we support long frames.
2263 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2264 ifp->if_capabilities |= IFCAP_VLAN_MTU;
2265 ifp->if_capenable = ifp->if_capabilities;
2266 #ifdef DEVICE_POLLING
2267 ifp->if_capabilities |= IFCAP_POLLING;
2270 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0);
2271 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0);
2274 * Call MI attach routine.
2276 ether_ifattach(ifp, (caddr_t)eaddr);
2278 /* Hook interrupt last to avoid having to lock softc */
2279 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE,
2280 NULL, dc_intr, sc, &sc->dc_intrhand);
2283 device_printf(dev, "couldn't set up irq\n");
2284 ether_ifdetach(ifp);
2295 * Shutdown hardware and free up resources. This can be called any
2296 * time after the mutex has been initialized. It is called in both
2297 * the error case in attach and the normal detach case so it needs
2298 * to be careful about only freeing resources that have actually been
2302 dc_detach(device_t dev)
2304 struct dc_softc *sc;
2306 struct dc_mediainfo *m;
2309 sc = device_get_softc(dev);
2310 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized"));
2314 #ifdef DEVICE_POLLING
2315 if (ifp->if_capenable & IFCAP_POLLING)
2316 ether_poll_deregister(ifp);
2319 /* These should only be active if attach succeeded */
2320 if (device_is_attached(dev)) {
2324 callout_drain(&sc->dc_stat_ch);
2325 callout_drain(&sc->dc_wdog_ch);
2326 ether_ifdetach(ifp);
2329 device_delete_child(dev, sc->dc_miibus);
2330 bus_generic_detach(dev);
2332 if (sc->dc_intrhand)
2333 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2335 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2337 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2342 if (sc->dc_cdata.dc_sbuf != NULL)
2343 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap);
2344 if (sc->dc_ldata != NULL)
2345 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap);
2347 for (i = 0; i < DC_TX_LIST_CNT; i++)
2348 if (sc->dc_cdata.dc_tx_map[i] != NULL)
2349 bus_dmamap_destroy(sc->dc_mtag,
2350 sc->dc_cdata.dc_tx_map[i]);
2351 for (i = 0; i < DC_RX_LIST_CNT; i++)
2352 if (sc->dc_cdata.dc_rx_map[i] != NULL)
2353 bus_dmamap_destroy(sc->dc_mtag,
2354 sc->dc_cdata.dc_rx_map[i]);
2355 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap);
2358 bus_dma_tag_destroy(sc->dc_stag);
2360 bus_dma_tag_destroy(sc->dc_mtag);
2362 bus_dma_tag_destroy(sc->dc_ltag);
2364 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2366 while (sc->dc_mi != NULL) {
2367 m = sc->dc_mi->dc_next;
2368 free(sc->dc_mi, M_DEVBUF);
2371 free(sc->dc_srom, M_DEVBUF);
2373 mtx_destroy(&sc->dc_mtx);
2379 * Initialize the transmit descriptors.
2382 dc_list_tx_init(struct dc_softc *sc)
2384 struct dc_chain_data *cd;
2385 struct dc_list_data *ld;
2390 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2391 if (i == DC_TX_LIST_CNT - 1)
2395 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti));
2396 cd->dc_tx_chain[i] = NULL;
2397 ld->dc_tx_list[i].dc_data = 0;
2398 ld->dc_tx_list[i].dc_ctl = 0;
2401 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2402 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2403 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2409 * Initialize the RX descriptors and allocate mbufs for them. Note that
2410 * we arrange the descriptors in a closed ring, so that the last descriptor
2411 * points back to the first.
2414 dc_list_rx_init(struct dc_softc *sc)
2416 struct dc_chain_data *cd;
2417 struct dc_list_data *ld;
2423 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2424 if (dc_newbuf(sc, i, 1) != 0)
2426 if (i == DC_RX_LIST_CNT - 1)
2430 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti));
2434 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2435 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2440 * Initialize an RX descriptor and attach an MBUF cluster.
2443 dc_newbuf(struct dc_softc *sc, int i, int alloc)
2447 bus_dma_segment_t segs[1];
2451 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2455 m_new = sc->dc_cdata.dc_rx_chain[i];
2456 m_new->m_data = m_new->m_ext.ext_buf;
2458 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2459 m_adj(m_new, sizeof(u_int64_t));
2462 * If this is a PNIC chip, zero the buffer. This is part
2463 * of the workaround for the receive bug in the 82c168 and
2466 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2467 bzero(mtod(m_new, char *), m_new->m_len);
2469 /* No need to remap the mbuf if we're reusing it. */
2471 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, sc->dc_sparemap,
2472 m_new, segs, &nseg, 0);
2478 ("%s: wrong number of segments (%d)", __func__, nseg));
2479 sc->dc_ldata->dc_rx_list[i].dc_data = htole32(segs->ds_addr);
2480 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]);
2481 tmp = sc->dc_cdata.dc_rx_map[i];
2482 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap;
2483 sc->dc_sparemap = tmp;
2484 sc->dc_cdata.dc_rx_chain[i] = m_new;
2487 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2488 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
2489 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
2490 BUS_DMASYNC_PREREAD);
2491 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2492 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2498 * The PNIC chip has a terrible bug in it that manifests itself during
2499 * periods of heavy activity. The exact mode of failure if difficult to
2500 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2501 * will happen on slow machines. The bug is that sometimes instead of
2502 * uploading one complete frame during reception, it uploads what looks
2503 * like the entire contents of its FIFO memory. The frame we want is at
2504 * the end of the whole mess, but we never know exactly how much data has
2505 * been uploaded, so salvaging the frame is hard.
2507 * There is only one way to do it reliably, and it's disgusting.
2508 * Here's what we know:
2510 * - We know there will always be somewhere between one and three extra
2511 * descriptors uploaded.
2513 * - We know the desired received frame will always be at the end of the
2514 * total data upload.
2516 * - We know the size of the desired received frame because it will be
2517 * provided in the length field of the status word in the last descriptor.
2519 * Here's what we do:
2521 * - When we allocate buffers for the receive ring, we bzero() them.
2522 * This means that we know that the buffer contents should be all
2523 * zeros, except for data uploaded by the chip.
2525 * - We also force the PNIC chip to upload frames that include the
2526 * ethernet CRC at the end.
2528 * - We gather all of the bogus frame data into a single buffer.
2530 * - We then position a pointer at the end of this buffer and scan
2531 * backwards until we encounter the first non-zero byte of data.
2532 * This is the end of the received frame. We know we will encounter
2533 * some data at the end of the frame because the CRC will always be
2534 * there, so even if the sender transmits a packet of all zeros,
2535 * we won't be fooled.
2537 * - We know the size of the actual received frame, so we subtract
2538 * that value from the current pointer location. This brings us
2539 * to the start of the actual received packet.
2541 * - We copy this into an mbuf and pass it on, along with the actual
2544 * The performance hit is tremendous, but it beats dropping frames all
2548 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
2550 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2552 struct dc_desc *cur_rx;
2553 struct dc_desc *c = NULL;
2554 struct mbuf *m = NULL;
2557 u_int32_t rxstat = 0;
2559 i = sc->dc_pnic_rx_bug_save;
2560 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2561 ptr = sc->dc_pnic_rx_buf;
2562 bzero(ptr, DC_RXLEN * 5);
2564 /* Copy all the bytes from the bogus buffers. */
2566 c = &sc->dc_ldata->dc_rx_list[i];
2567 rxstat = le32toh(c->dc_status);
2568 m = sc->dc_cdata.dc_rx_chain[i];
2569 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2571 /* If this is the last buffer, break out. */
2572 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2574 dc_newbuf(sc, i, 0);
2575 DC_INC(i, DC_RX_LIST_CNT);
2578 /* Find the length of the actual receive frame. */
2579 total_len = DC_RXBYTES(rxstat);
2581 /* Scan backwards until we hit a non-zero byte. */
2582 while (*ptr == 0x00)
2586 if ((uintptr_t)(ptr) & 0x3)
2589 /* Now find the start of the frame. */
2591 if (ptr < sc->dc_pnic_rx_buf)
2592 ptr = sc->dc_pnic_rx_buf;
2595 * Now copy the salvaged frame to the last mbuf and fake up
2596 * the status word to make it look like a successful
2599 dc_newbuf(sc, i, 0);
2600 bcopy(ptr, mtod(m, char *), total_len);
2601 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
2605 * This routine searches the RX ring for dirty descriptors in the
2606 * event that the rxeof routine falls out of sync with the chip's
2607 * current descriptor pointer. This may happen sometimes as a result
2608 * of a "no RX buffer available" condition that happens when the chip
2609 * consumes all of the RX buffers before the driver has a chance to
2610 * process the RX ring. This routine may need to be called more than
2611 * once to bring the driver back in sync with the chip, however we
2612 * should still be getting RX DONE interrupts to drive the search
2613 * for new packets in the RX ring, so we should catch up eventually.
2616 dc_rx_resync(struct dc_softc *sc)
2618 struct dc_desc *cur_rx;
2621 pos = sc->dc_cdata.dc_rx_prod;
2623 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2624 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2625 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN))
2627 DC_INC(pos, DC_RX_LIST_CNT);
2630 /* If the ring really is empty, then just return. */
2631 if (i == DC_RX_LIST_CNT)
2634 /* We've fallen behing the chip: catch it. */
2635 sc->dc_cdata.dc_rx_prod = pos;
2641 * A frame has been uploaded: pass the resulting mbuf chain up to
2642 * the higher level protocols.
2645 dc_rxeof(struct dc_softc *sc)
2647 struct mbuf *m, *m0;
2649 struct dc_desc *cur_rx;
2650 int i, total_len = 0;
2656 i = sc->dc_cdata.dc_rx_prod;
2658 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
2659 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) &
2661 #ifdef DEVICE_POLLING
2662 if (ifp->if_capenable & IFCAP_POLLING) {
2663 if (sc->rxcycles <= 0)
2668 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2669 rxstat = le32toh(cur_rx->dc_status);
2670 m = sc->dc_cdata.dc_rx_chain[i];
2671 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
2672 BUS_DMASYNC_POSTREAD);
2673 total_len = DC_RXBYTES(rxstat);
2675 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2676 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2677 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2678 sc->dc_pnic_rx_bug_save = i;
2679 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2680 DC_INC(i, DC_RX_LIST_CNT);
2683 dc_pnic_rx_bug_war(sc, i);
2684 rxstat = le32toh(cur_rx->dc_status);
2685 total_len = DC_RXBYTES(rxstat);
2690 * If an error occurs, update stats, clear the
2691 * status word and leave the mbuf cluster in place:
2692 * it should simply get re-used next time this descriptor
2693 * comes up in the ring. However, don't report long
2694 * frames as errors since they could be vlans.
2696 if ((rxstat & DC_RXSTAT_RXERR)) {
2697 if (!(rxstat & DC_RXSTAT_GIANT) ||
2698 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2699 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2700 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2702 if (rxstat & DC_RXSTAT_COLLSEEN)
2703 ifp->if_collisions++;
2704 dc_newbuf(sc, i, 0);
2705 if (rxstat & DC_RXSTAT_CRCERR) {
2706 DC_INC(i, DC_RX_LIST_CNT);
2715 /* No errors; receive the packet. */
2716 total_len -= ETHER_CRC_LEN;
2717 #ifdef __NO_STRICT_ALIGNMENT
2719 * On architectures without alignment problems we try to
2720 * allocate a new buffer for the receive ring, and pass up
2721 * the one where the packet is already, saving the expensive
2722 * copy done in m_devget().
2723 * If we are on an architecture with alignment problems, or
2724 * if the allocation fails, then use m_devget and leave the
2725 * existing buffer in the receive ring.
2727 if (dc_newbuf(sc, i, 1) == 0) {
2728 m->m_pkthdr.rcvif = ifp;
2729 m->m_pkthdr.len = m->m_len = total_len;
2730 DC_INC(i, DC_RX_LIST_CNT);
2734 m0 = m_devget(mtod(m, char *), total_len,
2735 ETHER_ALIGN, ifp, NULL);
2736 dc_newbuf(sc, i, 0);
2737 DC_INC(i, DC_RX_LIST_CNT);
2747 (*ifp->if_input)(ifp, m);
2751 sc->dc_cdata.dc_rx_prod = i;
2755 * A frame was downloaded to the chip. It's safe for us to clean up
2759 dc_txeof(struct dc_softc *sc)
2761 struct dc_desc *cur_tx = NULL;
2764 u_int32_t ctl, txstat;
2769 * Go through our tx list and free mbufs for those
2770 * frames that have been transmitted.
2772 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
2773 idx = sc->dc_cdata.dc_tx_cons;
2774 while (idx != sc->dc_cdata.dc_tx_prod) {
2776 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2777 txstat = le32toh(cur_tx->dc_status);
2778 ctl = le32toh(cur_tx->dc_ctl);
2780 if (txstat & DC_TXSTAT_OWN)
2783 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) {
2784 if (ctl & DC_TXCTL_SETUP) {
2786 * Yes, the PNIC is so brain damaged
2787 * that it will sometimes generate a TX
2788 * underrun error while DMAing the RX
2789 * filter setup frame. If we detect this,
2790 * we have to send the setup frame again,
2791 * or else the filter won't be programmed
2794 if (DC_IS_PNIC(sc)) {
2795 if (txstat & DC_TXSTAT_ERRSUM)
2798 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2800 sc->dc_cdata.dc_tx_cnt--;
2801 DC_INC(idx, DC_TX_LIST_CNT);
2805 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2807 * XXX: Why does my Xircom taunt me so?
2808 * For some reason it likes setting the CARRLOST flag
2809 * even when the carrier is there. wtf?!?
2810 * Who knows, but Conexant chips have the
2811 * same problem. Maybe they took lessons
2814 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2815 sc->dc_pmode == DC_PMODE_MII &&
2816 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2817 DC_TXSTAT_NOCARRIER)))
2818 txstat &= ~DC_TXSTAT_ERRSUM;
2820 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2821 sc->dc_pmode == DC_PMODE_MII &&
2822 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2823 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST)))
2824 txstat &= ~DC_TXSTAT_ERRSUM;
2827 if (txstat & DC_TXSTAT_ERRSUM) {
2829 if (txstat & DC_TXSTAT_EXCESSCOLL)
2830 ifp->if_collisions++;
2831 if (txstat & DC_TXSTAT_LATECOLL)
2832 ifp->if_collisions++;
2833 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2839 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2842 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2843 bus_dmamap_sync(sc->dc_mtag,
2844 sc->dc_cdata.dc_tx_map[idx],
2845 BUS_DMASYNC_POSTWRITE);
2846 bus_dmamap_unload(sc->dc_mtag,
2847 sc->dc_cdata.dc_tx_map[idx]);
2848 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2849 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2852 sc->dc_cdata.dc_tx_cnt--;
2853 DC_INC(idx, DC_TX_LIST_CNT);
2855 sc->dc_cdata.dc_tx_cons = idx;
2857 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_RSVD)
2858 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2860 if (sc->dc_cdata.dc_tx_cnt == 0)
2861 sc->dc_wdog_timer = 0;
2867 struct dc_softc *sc;
2868 struct mii_data *mii;
2875 mii = device_get_softc(sc->dc_miibus);
2877 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2878 if (sc->dc_flags & DC_21143_NWAY) {
2879 r = CSR_READ_4(sc, DC_10BTSTAT);
2880 if (IFM_SUBTYPE(mii->mii_media_active) ==
2881 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2885 if (IFM_SUBTYPE(mii->mii_media_active) ==
2886 IFM_10_T && (r & DC_TSTAT_LS10)) {
2890 if (sc->dc_link == 0)
2894 * For NICs which never report DC_RXSTATE_WAIT, we
2895 * have to bite the bullet...
2897 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc,
2898 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
2899 sc->dc_cdata.dc_tx_cnt == 0) {
2901 if (!(mii->mii_media_status & IFM_ACTIVE))
2909 * When the init routine completes, we expect to be able to send
2910 * packets right away, and in fact the network code will send a
2911 * gratuitous ARP the moment the init routine marks the interface
2912 * as running. However, even though the MAC may have been initialized,
2913 * there may be a delay of a few seconds before the PHY completes
2914 * autonegotiation and the link is brought up. Any transmissions
2915 * made during that delay will be lost. Dealing with this is tricky:
2916 * we can't just pause in the init routine while waiting for the
2917 * PHY to come ready since that would bring the whole system to
2918 * a screeching halt for several seconds.
2920 * What we do here is prevent the TX start routine from sending
2921 * any packets until a link has been established. After the
2922 * interface has been initialized, the tick routine will poll
2923 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2924 * that time, packets will stay in the send queue, and once the
2925 * link comes up, they will be flushed out to the wire.
2927 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE &&
2928 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2930 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2931 dc_start_locked(ifp);
2934 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2935 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
2937 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
2941 * A transmit underrun has occurred. Back off the transmit threshold,
2942 * or switch to store and forward mode if we have to.
2945 dc_tx_underrun(struct dc_softc *sc)
2950 if (DC_IS_DAVICOM(sc))
2953 if (DC_IS_INTEL(sc)) {
2955 * The real 21143 requires that the transmitter be idle
2956 * in order to change the transmit threshold or store
2957 * and forward state.
2959 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2961 for (i = 0; i < DC_TIMEOUT; i++) {
2962 isr = CSR_READ_4(sc, DC_ISR);
2963 if (isr & DC_ISR_TX_IDLE)
2967 if (i == DC_TIMEOUT) {
2968 device_printf(sc->dc_dev,
2969 "%s: failed to force tx to idle state\n",
2975 device_printf(sc->dc_dev, "TX underrun -- ");
2976 sc->dc_txthresh += DC_TXTHRESH_INC;
2977 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2978 printf("using store and forward mode\n");
2979 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2981 printf("increasing TX threshold\n");
2982 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2983 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2986 if (DC_IS_INTEL(sc))
2987 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2990 #ifdef DEVICE_POLLING
2991 static poll_handler_t dc_poll;
2994 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2996 struct dc_softc *sc = ifp->if_softc;
3000 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3005 sc->rxcycles = count;
3008 if (!IFQ_IS_EMPTY(&ifp->if_snd) &&
3009 !(ifp->if_drv_flags & IFF_DRV_OACTIVE))
3010 dc_start_locked(ifp);
3012 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3015 status = CSR_READ_4(sc, DC_ISR);
3016 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF |
3017 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN |
3023 /* ack what we have */
3024 CSR_WRITE_4(sc, DC_ISR, status);
3026 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) {
3027 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3028 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3030 if (dc_rx_resync(sc))
3033 /* restart transmit unit if necessary */
3034 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3035 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3037 if (status & DC_ISR_TX_UNDERRUN)
3040 if (status & DC_ISR_BUS_ERR) {
3041 if_printf(ifp, "%s: bus error\n", __func__);
3048 #endif /* DEVICE_POLLING */
3053 struct dc_softc *sc;
3062 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
3067 #ifdef DEVICE_POLLING
3068 if (ifp->if_capenable & IFCAP_POLLING) {
3074 /* Suppress unwanted interrupts */
3075 if (!(ifp->if_flags & IFF_UP)) {
3076 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
3082 /* Disable interrupts. */
3083 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3085 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) &&
3086 status != 0xFFFFFFFF &&
3087 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3089 CSR_WRITE_4(sc, DC_ISR, status);
3091 if (status & DC_ISR_RX_OK) {
3093 curpkts = ifp->if_ipackets;
3095 if (curpkts == ifp->if_ipackets) {
3096 while (dc_rx_resync(sc))
3101 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF))
3104 if (status & DC_ISR_TX_IDLE) {
3106 if (sc->dc_cdata.dc_tx_cnt) {
3107 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3108 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3112 if (status & DC_ISR_TX_UNDERRUN)
3115 if ((status & DC_ISR_RX_WATDOGTIMEO)
3116 || (status & DC_ISR_RX_NOBUF)) {
3118 curpkts = ifp->if_ipackets;
3120 if (curpkts == ifp->if_ipackets) {
3121 while (dc_rx_resync(sc))
3126 if (status & DC_ISR_BUS_ERR) {
3132 /* Re-enable interrupts. */
3133 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3135 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3136 dc_start_locked(ifp);
3142 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3143 * pointers to the fragment pointers.
3146 dc_encap(struct dc_softc *sc, struct mbuf **m_head)
3148 bus_dma_segment_t segs[DC_MAXFRAGS];
3151 int cur, defragged, error, first, frag, i, idx, nseg;
3154 * If there's no way we can send any packets, return now.
3156 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD)
3161 if (sc->dc_flags & DC_TX_COALESCE &&
3162 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) {
3163 m = m_defrag(*m_head, M_DONTWAIT);
3167 * Count the number of frags in this chain to see if we
3168 * need to m_collapse. Since the descriptor list is shared
3169 * by all packets, we'll m_collapse long chains so that they
3170 * do not use up the entire list, even if they would fit.
3173 for (m = *m_head; m != NULL; m = m->m_next)
3175 if (i > DC_TX_LIST_CNT / 4 ||
3176 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <=
3178 m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS);
3182 if (defragged != 0) {
3191 idx = sc->dc_cdata.dc_tx_prod;
3192 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag,
3193 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3194 if (error == EFBIG) {
3195 if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT,
3196 DC_MAXFRAGS)) == NULL) {
3199 return (defragged != 0 ? error : ENOBUFS);
3202 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag,
3203 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3209 } else if (error != 0)
3211 KASSERT(nseg <= DC_MAXFRAGS,
3212 ("%s: wrong number of segments (%d)", __func__, nseg));
3219 first = cur = frag = sc->dc_cdata.dc_tx_prod;
3220 for (i = 0; i < nseg; i++) {
3221 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3222 (frag == (DC_TX_LIST_CNT - 1)) &&
3223 (first != sc->dc_cdata.dc_tx_first)) {
3224 bus_dmamap_unload(sc->dc_mtag,
3225 sc->dc_cdata.dc_tx_map[first]);
3231 f = &sc->dc_ldata->dc_tx_list[frag];
3232 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len);
3235 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG);
3237 f->dc_status = htole32(DC_TXSTAT_OWN);
3238 f->dc_data = htole32(segs[i].ds_addr);
3240 DC_INC(frag, DC_TX_LIST_CNT);
3243 sc->dc_cdata.dc_tx_prod = frag;
3244 sc->dc_cdata.dc_tx_cnt += nseg;
3245 sc->dc_cdata.dc_tx_chain[cur] = *m_head;
3246 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
3247 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3248 sc->dc_ldata->dc_tx_list[first].dc_ctl |=
3249 htole32(DC_TXCTL_FINT);
3250 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3251 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3252 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3253 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3254 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN);
3256 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx],
3257 BUS_DMASYNC_PREWRITE);
3258 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
3259 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3264 dc_start(struct ifnet *ifp)
3266 struct dc_softc *sc;
3270 dc_start_locked(ifp);
3275 * Main transmit routine
3276 * To avoid having to do mbuf copies, we put pointers to the mbuf data
3277 * regions directly in the transmit lists. We also save a copy of the
3278 * pointers since the transmit list fragment pointers are physical
3282 dc_start_locked(struct ifnet *ifp)
3284 struct dc_softc *sc;
3285 struct mbuf *m_head = NULL;
3286 unsigned int queued = 0;
3293 if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
3296 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
3299 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod;
3301 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3302 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3306 if (dc_encap(sc, &m_head)) {
3309 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3310 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3313 idx = sc->dc_cdata.dc_tx_prod;
3317 * If there's a BPF listener, bounce a copy of this frame
3320 BPF_MTAP(ifp, m_head);
3322 if (sc->dc_flags & DC_TX_ONE) {
3323 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3330 if (!(sc->dc_flags & DC_TX_POLL))
3331 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3334 * Set a timeout in case the chip goes out to lunch.
3336 sc->dc_wdog_timer = 5;
3343 struct dc_softc *sc = xsc;
3351 dc_init_locked(struct dc_softc *sc)
3353 struct ifnet *ifp = sc->dc_ifp;
3354 struct mii_data *mii;
3358 mii = device_get_softc(sc->dc_miibus);
3361 * Cancel pending I/O and free all RX/TX buffers.
3367 * Set cache alignment and burst length.
3369 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3370 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3372 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE);
3374 * Evenly share the bus between receive and transmit process.
3376 if (DC_IS_INTEL(sc))
3377 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3378 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3379 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3381 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3383 if (sc->dc_flags & DC_TX_POLL)
3384 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3385 switch(sc->dc_cachesize) {
3387 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3390 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3393 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3397 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3401 if (sc->dc_flags & DC_TX_STORENFWD)
3402 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3404 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3405 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3407 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3408 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3412 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3413 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3415 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3417 * The app notes for the 98713 and 98715A say that
3418 * in order to have the chips operate properly, a magic
3419 * number must be written to CSR16. Macronix does not
3420 * document the meaning of these bits so there's no way
3421 * to know exactly what they do. The 98713 has a magic
3422 * number all its own; the rest all use a different one.
3424 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3425 if (sc->dc_type == DC_TYPE_98713)
3426 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3428 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3431 if (DC_IS_XIRCOM(sc)) {
3433 * setup General Purpose Port mode and data so the tulip
3434 * can talk to the MII.
3436 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3437 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3439 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3440 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3444 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3445 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3447 /* Init circular RX list. */
3448 if (dc_list_rx_init(sc) == ENOBUFS) {
3449 device_printf(sc->dc_dev,
3450 "initialization failed: no memory for rx buffers\n");
3456 * Init TX descriptors.
3458 dc_list_tx_init(sc);
3461 * Load the address of the RX list.
3463 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0));
3464 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0));
3467 * Enable interrupts.
3469 #ifdef DEVICE_POLLING
3471 * ... but only if we are not polling, and make sure they are off in
3472 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3475 if (ifp->if_capenable & IFCAP_POLLING)
3476 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3479 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3480 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3482 /* Enable transmitter. */
3483 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3486 * If this is an Intel 21143 and we're not using the
3487 * MII port, program the LED control pins so we get
3488 * link and activity indications.
3490 if (sc->dc_flags & DC_TULIP_LEDS) {
3491 CSR_WRITE_4(sc, DC_WATCHDOG,
3492 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY);
3493 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3497 * Load the RX/multicast filter. We do this sort of late
3498 * because the filter programming scheme on the 21143 and
3499 * some clones requires DMAing a setup frame via the TX
3500 * engine, and we need the transmitter enabled for that.
3504 /* Enable receiver. */
3505 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3506 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3509 dc_setcfg(sc, sc->dc_if_media);
3511 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3512 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3514 /* Don't start the ticker if this is a homePNA link. */
3515 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3518 if (sc->dc_flags & DC_21143_NWAY)
3519 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3521 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3524 sc->dc_wdog_timer = 0;
3525 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
3529 * Set media options.
3532 dc_ifmedia_upd(struct ifnet *ifp)
3534 struct dc_softc *sc;
3535 struct mii_data *mii;
3536 struct ifmedia *ifm;
3539 mii = device_get_softc(sc->dc_miibus);
3542 ifm = &mii->mii_media;
3544 if (DC_IS_DAVICOM(sc) &&
3545 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3546 dc_setcfg(sc, ifm->ifm_media);
3555 * Report current media status.
3558 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3560 struct dc_softc *sc;
3561 struct mii_data *mii;
3562 struct ifmedia *ifm;
3565 mii = device_get_softc(sc->dc_miibus);
3568 ifm = &mii->mii_media;
3569 if (DC_IS_DAVICOM(sc)) {
3570 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3571 ifmr->ifm_active = ifm->ifm_media;
3572 ifmr->ifm_status = 0;
3577 ifmr->ifm_active = mii->mii_media_active;
3578 ifmr->ifm_status = mii->mii_media_status;
3583 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3585 struct dc_softc *sc = ifp->if_softc;
3586 struct ifreq *ifr = (struct ifreq *)data;
3587 struct mii_data *mii;
3593 if (ifp->if_flags & IFF_UP) {
3594 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3595 (IFF_PROMISC | IFF_ALLMULTI);
3597 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3601 sc->dc_txthresh = 0;
3605 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3608 sc->dc_if_flags = ifp->if_flags;
3621 mii = device_get_softc(sc->dc_miibus);
3622 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3625 #ifdef DEVICE_POLLING
3626 if (ifr->ifr_reqcap & IFCAP_POLLING &&
3627 !(ifp->if_capenable & IFCAP_POLLING)) {
3628 error = ether_poll_register(dc_poll, ifp);
3632 /* Disable interrupts */
3633 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3634 ifp->if_capenable |= IFCAP_POLLING;
3638 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
3639 ifp->if_capenable & IFCAP_POLLING) {
3640 error = ether_poll_deregister(ifp);
3641 /* Enable interrupts. */
3643 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3644 ifp->if_capenable &= ~IFCAP_POLLING;
3648 #endif /* DEVICE_POLLING */
3651 error = ether_ioctl(ifp, command, data);
3659 dc_watchdog(void *xsc)
3661 struct dc_softc *sc = xsc;
3666 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) {
3667 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
3673 device_printf(sc->dc_dev, "watchdog timeout\n");
3679 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3680 dc_start_locked(ifp);
3684 * Stop the adapter and free any mbufs allocated to the
3688 dc_stop(struct dc_softc *sc)
3691 struct dc_list_data *ld;
3692 struct dc_chain_data *cd;
3702 callout_stop(&sc->dc_stat_ch);
3703 callout_stop(&sc->dc_wdog_ch);
3704 sc->dc_wdog_timer = 0;
3706 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3708 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON));
3709 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3710 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3711 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3715 * Free data in the RX lists.
3717 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3718 if (cd->dc_rx_chain[i] != NULL) {
3719 m_freem(cd->dc_rx_chain[i]);
3720 cd->dc_rx_chain[i] = NULL;
3723 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list));
3726 * Free the TX list buffers.
3728 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3729 if (cd->dc_tx_chain[i] != NULL) {
3730 ctl = le32toh(ld->dc_tx_list[i].dc_ctl);
3731 if ((ctl & DC_TXCTL_SETUP) ||
3732 !(ctl & DC_TXCTL_LASTFRAG)) {
3733 cd->dc_tx_chain[i] = NULL;
3736 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]);
3737 m_freem(cd->dc_tx_chain[i]);
3738 cd->dc_tx_chain[i] = NULL;
3741 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list));
3745 * Device suspend routine. Stop the interface and save some PCI
3746 * settings in case the BIOS doesn't restore them properly on
3750 dc_suspend(device_t dev)
3752 struct dc_softc *sc;
3754 sc = device_get_softc(dev);
3764 * Device resume routine. Restore some PCI settings in case the BIOS
3765 * doesn't, re-enable busmastering, and restart the interface if
3769 dc_resume(device_t dev)
3771 struct dc_softc *sc;
3774 sc = device_get_softc(dev);
3777 /* reinitialize interface if necessary */
3779 if (ifp->if_flags & IFF_UP)
3789 * Stop all chip I/O so that the kernel's probe routines don't
3790 * get confused by errant DMAs when rebooting.
3793 dc_shutdown(device_t dev)
3795 struct dc_softc *sc;
3797 sc = device_get_softc(dev);
projects / FreeBSD / releng / 7.2.git / blob