1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
36 #include "dev/drm/i915_reg.h"
38 /* General customization:
41 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
43 #define DRIVER_NAME "i915"
44 #define DRIVER_DESC "Intel Graphics"
45 #define DRIVER_DATE "20080730"
52 #define I915_NUM_PIPE 2
57 * 1.2: Add Power Management
58 * 1.3: Add vblank support
59 * 1.4: Fix cmdbuffer path, add heap destroy
60 * 1.5: Add vblank pipe configuration
61 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
62 * - Support vertical blank on secondary display pipe
64 #define DRIVER_MAJOR 1
65 #define DRIVER_MINOR 6
66 #define DRIVER_PATCHLEVEL 0
68 #define WATCH_COHERENCY 0
73 #define WATCH_INACTIVE 0
74 #define WATCH_PWRITE 0
76 typedef struct _drm_i915_ring_buffer {
84 struct drm_gem_object *ring_obj;
85 } drm_i915_ring_buffer_t;
88 struct mem_block *next;
89 struct mem_block *prev;
92 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
95 struct opregion_header;
97 struct opregion_swsci;
100 struct intel_opregion {
101 struct opregion_header *header;
102 struct opregion_acpi *acpi;
103 struct opregion_swsci *swsci;
104 struct opregion_asle *asle;
108 typedef struct drm_i915_private {
109 struct drm_device *dev;
111 drm_local_map_t *sarea;
112 drm_local_map_t *mmio_map;
114 drm_i915_sarea_t *sarea_priv;
115 drm_i915_ring_buffer_t ring;
117 drm_dma_handle_t *status_page_dmah;
118 void *hw_status_page;
119 dma_addr_t dma_status_page;
121 unsigned int status_gfx_addr;
122 drm_local_map_t hws_map;
123 struct drm_gem_object *hws_obj;
131 wait_queue_head_t irq_queue;
132 atomic_t irq_received;
133 /** Protects user_irq_refcount and irq_mask_reg */
134 DRM_SPINTYPE user_irq_lock;
135 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
136 int user_irq_refcount;
137 /** Cached value of IER to avoid reads in updating the bitfield */
141 int tex_lru_log_granularity;
142 int allow_batchbuffer;
143 struct mem_block *agp_heap;
144 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
147 struct intel_opregion opregion;
176 u32 savePFIT_PGM_RATIOS;
178 u32 saveBLC_PWM_CTL2;
203 u32 savePP_ON_DELAYS;
204 u32 savePP_OFF_DELAYS;
212 u32 savePFIT_CONTROL;
213 u32 save_palette_a[256];
214 u32 save_palette_b[256];
215 u32 saveFBC_CFB_BASE;
218 u32 saveFBC_CONTROL2;
222 u32 saveCACHE_MODE_0;
225 u32 saveMI_ARB_STATE;
235 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
239 struct drm_mm gtt_space;
242 * List of objects currently involved in rendering from the
245 * A reference is held on the buffer while on this list.
247 struct list_head active_list;
250 * List of objects which are not in the ringbuffer but which
251 * still have a write_domain which needs to be flushed before
254 * A reference is held on the buffer while on this list.
256 struct list_head flushing_list;
259 * LRU list of objects which are not in the ringbuffer and
260 * are ready to unbind, but are still in the GTT.
262 * A reference is not held on the buffer while on this list,
263 * as merely being GTT-bound shouldn't prevent its being
264 * freed, and we'll pull it off the list in the free path.
266 struct list_head inactive_list;
269 * List of breadcrumbs associated with GPU requests currently
272 struct list_head request_list;
275 * We leave the user IRQ off as much as possible,
276 * but this means that requests will finish and never
277 * be retired once the system goes idle. Set a timer to
278 * fire periodically while the ring is running. When it
279 * fires, go retire requests.
281 struct delayed_work retire_work;
283 uint32_t next_gem_seqno;
286 * Waiting sequence number, if any
288 uint32_t waiting_gem_seqno;
291 * Last seq seen at irq time
293 uint32_t irq_gem_seqno;
296 * Flag if the X Server, and thus DRM, is not currently in
297 * control of the device.
299 * This is set between LeaveVT and EnterVT. It needs to be
300 * replaced with a semaphore. It also needs to be
301 * transitioned away from for kernel modesetting.
306 * Flag if the hardware appears to be wedged.
308 * This is set when attempts to idle the device timeout.
309 * It prevents command submission from occuring and makes
310 * every pending request fail
314 /** Bit 6 swizzling required for X tiling */
315 uint32_t bit_6_swizzle_x;
316 /** Bit 6 swizzling required for Y tiling */
317 uint32_t bit_6_swizzle_y;
319 } drm_i915_private_t;
321 enum intel_chip_family {
328 /** driver private structure attached to each drm_gem_object */
329 struct drm_i915_gem_object {
330 struct drm_gem_object *obj;
332 /** Current space allocated to this object in the GTT, if any. */
333 struct drm_mm_node *gtt_space;
335 /** This object's place on the active/flushing/inactive lists */
336 struct list_head list;
339 * This is set if the object is on the active or flushing lists
340 * (has pending rendering), and is not set if it's on inactive (ready
346 * This is set if the object has been written to since last bound
351 /** AGP memory structure for our GTT binding. */
352 DRM_AGP_MEM *agp_mem;
354 struct page **page_list;
357 * Current offset of the object in GTT space.
359 * This is the same as gtt_space->start
363 /** Boolean whether this object has a valid gtt offset. */
366 /** How many users have pinned this object in GTT space */
369 /** Breadcrumb of last rendering to the buffer. */
370 uint32_t last_rendering_seqno;
372 /** Current tiling mode for the object. */
373 uint32_t tiling_mode;
375 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
379 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when
380 * GEM_DOMAIN_CPU is not in the object's read domain.
382 uint8_t *page_cpu_valid;
386 * Request queue structure.
388 * The request queue allows us to note sequence numbers that have been emitted
389 * and may be associated with active buffers to be retired.
391 * By keeping this list, we can avoid having to do questionable
392 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
393 * an emission time with seqnos for tracking how far ahead of the GPU we are.
395 struct drm_i915_gem_request {
396 /** GEM sequence number associated with this request. */
399 /** Time at which this request was emitted, in jiffies. */
400 unsigned long emitted_jiffies;
402 /** Cache domains that were flushed at the start of the request. */
403 uint32_t flush_domains;
405 struct list_head list;
408 struct drm_i915_file_private {
410 uint32_t last_gem_seqno;
411 uint32_t last_gem_throttle_seqno;
415 extern struct drm_ioctl_desc i915_ioctls[];
416 extern int i915_max_ioctl;
419 extern void i915_kernel_lost_context(struct drm_device * dev);
420 extern int i915_driver_load(struct drm_device *, unsigned long flags);
421 extern int i915_driver_unload(struct drm_device *);
422 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
423 extern void i915_driver_lastclose(struct drm_device * dev);
424 extern void i915_driver_preclose(struct drm_device *dev,
425 struct drm_file *file_priv);
426 extern void i915_driver_postclose(struct drm_device *dev,
427 struct drm_file *file_priv);
428 extern int i915_driver_device_is_agp(struct drm_device * dev);
429 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
431 extern int i915_emit_box(struct drm_device *dev,
432 struct drm_clip_rect __user *boxes,
433 int i, int DR1, int DR4);
436 extern int i915_irq_emit(struct drm_device *dev, void *data,
437 struct drm_file *file_priv);
438 extern int i915_irq_wait(struct drm_device *dev, void *data,
439 struct drm_file *file_priv);
440 void i915_user_irq_get(struct drm_device *dev);
441 void i915_user_irq_put(struct drm_device *dev);
443 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
444 extern void i915_driver_irq_preinstall(struct drm_device * dev);
445 extern int i915_driver_irq_postinstall(struct drm_device *dev);
446 extern void i915_driver_irq_uninstall(struct drm_device * dev);
447 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
448 struct drm_file *file_priv);
449 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
450 struct drm_file *file_priv);
451 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
452 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
453 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
454 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
455 extern int i915_vblank_swap(struct drm_device *dev, void *data,
456 struct drm_file *file_priv);
459 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
462 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
466 extern int i915_mem_alloc(struct drm_device *dev, void *data,
467 struct drm_file *file_priv);
468 extern int i915_mem_free(struct drm_device *dev, void *data,
469 struct drm_file *file_priv);
470 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
471 struct drm_file *file_priv);
472 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
473 struct drm_file *file_priv);
474 extern void i915_mem_takedown(struct mem_block **heap);
475 extern void i915_mem_release(struct drm_device * dev,
476 struct drm_file *file_priv, struct mem_block *heap);
479 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
480 struct drm_file *file_priv);
481 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
482 struct drm_file *file_priv);
483 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
484 struct drm_file *file_priv);
485 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
486 struct drm_file *file_priv);
487 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
488 struct drm_file *file_priv);
489 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
490 struct drm_file *file_priv);
491 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
492 struct drm_file *file_priv);
493 int i915_gem_execbuffer(struct drm_device *dev, void *data,
494 struct drm_file *file_priv);
495 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
496 struct drm_file *file_priv);
497 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
498 struct drm_file *file_priv);
499 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
500 struct drm_file *file_priv);
501 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
502 struct drm_file *file_priv);
503 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
504 struct drm_file *file_priv);
505 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
506 struct drm_file *file_priv);
507 int i915_gem_set_tiling(struct drm_device *dev, void *data,
508 struct drm_file *file_priv);
509 int i915_gem_get_tiling(struct drm_device *dev, void *data,
510 struct drm_file *file_priv);
511 void i915_gem_load(struct drm_device *dev);
512 int i915_gem_proc_init(struct drm_minor *minor);
513 void i915_gem_proc_cleanup(struct drm_minor *minor);
514 int i915_gem_init_object(struct drm_gem_object *obj);
515 void i915_gem_free_object(struct drm_gem_object *obj);
516 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
517 void i915_gem_object_unpin(struct drm_gem_object *obj);
518 void i915_gem_lastclose(struct drm_device *dev);
519 uint32_t i915_get_gem_seqno(struct drm_device *dev);
520 void i915_gem_retire_requests(struct drm_device *dev);
521 void i915_gem_retire_work_handler(struct work_struct *work);
522 void i915_gem_clflush_object(struct drm_gem_object *obj);
524 /* i915_gem_tiling.c */
525 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
527 /* i915_gem_debug.c */
528 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
529 const char *where, uint32_t mark);
531 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
533 #define i915_verify_inactive(dev, file, line)
535 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
536 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
537 const char *where, uint32_t mark);
538 void i915_dump_lru(struct drm_device *dev, const char *where);
539 #endif /* I915_HAVE_GEM */
542 extern int i915_save_state(struct drm_device *dev);
543 extern int i915_restore_state(struct drm_device *dev);
545 /* i915_opregion.c */
546 extern int intel_opregion_init(struct drm_device *dev);
547 extern void intel_opregion_free(struct drm_device *dev);
548 extern void opregion_asle_intr(struct drm_device *dev);
549 extern void opregion_enable_asle(struct drm_device *dev);
552 * Lock test for when it's just for synchronization of ring access.
554 * In that case, we don't need to do it when GEM is initialized as nobody else
555 * has access to the ring.
557 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
558 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
559 LOCK_TEST_WITH_RETURN(dev, file_priv); \
562 #if defined(__FreeBSD__)
563 typedef boolean_t bool;
566 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
567 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
568 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
569 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
570 #define I915_READ8(reg) DRM_READ8(dev_priv->mmio_map, (reg))
571 #define I915_WRITE8(reg,val) DRM_WRITE8(dev_priv->mmio_map, (reg), (val))
573 #define I915_VERBOSE 0
575 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
578 #define BEGIN_LP_RING(n) do { \
580 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
581 if (dev_priv->ring.space < (n)*4) \
582 i915_wait_ring(dev, (n)*4, __func__); \
584 outring = dev_priv->ring.tail; \
585 ringmask = dev_priv->ring.tail_mask; \
586 virt = dev_priv->ring.virtual_start; \
589 #define OUT_RING(n) do { \
590 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
591 *(volatile unsigned int *)(virt + outring) = (n); \
594 outring &= ringmask; \
597 #define ADVANCE_LP_RING() do { \
598 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
599 dev_priv->ring.tail = outring; \
600 dev_priv->ring.space -= outcount * 4; \
601 I915_WRITE(PRB0_TAIL, outring); \
605 * Reads a dword out of the status page, which is written to from the command
606 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
609 * The following dwords have a reserved meaning:
610 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
611 * 0x04: ring 0 head pointer
612 * 0x05: ring 1 head pointer (915-class)
613 * 0x06: ring 2 head pointer (915-class)
614 * 0x10-0x1b: Context status DWords (GM45)
615 * 0x1f: Last written status offset. (GM45)
617 * The area from dword 0x20 to 0x3ff is available for driver usage.
619 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
620 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
621 #define I915_GEM_HWS_INDEX 0x20
622 #define I915_BREADCRUMB_INDEX 0x21
624 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
626 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
627 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
628 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
629 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
630 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
632 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
633 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
634 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
635 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
636 (dev)->pci_device == 0x27AE)
637 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
638 (dev)->pci_device == 0x2982 || \
639 (dev)->pci_device == 0x2992 || \
640 (dev)->pci_device == 0x29A2 || \
641 (dev)->pci_device == 0x2A02 || \
642 (dev)->pci_device == 0x2A12 || \
643 (dev)->pci_device == 0x2A42 || \
644 (dev)->pci_device == 0x2E02 || \
645 (dev)->pci_device == 0x2E12 || \
646 (dev)->pci_device == 0x2E22)
648 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
650 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
652 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
653 (dev)->pci_device == 0x2E12 || \
654 (dev)->pci_device == 0x2E22)
656 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
657 (dev)->pci_device == 0x29B2 || \
658 (dev)->pci_device == 0x29D2)
660 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
661 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
663 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
664 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
666 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
668 #define PRIMARY_RINGBUFFER_SIZE (128*1024)