sys/dev/drm/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*-
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include "dev/drm/drmP.h"
  33 #include "dev/drm/drm.h"
  34 #include "dev/drm/i915_drm.h"
  35 #include "dev/drm/i915_drv.h"
  36
  37 #define MAX_NOPID ((u32)~0)
  38
  39 /**
  40  * Interrupts that are always left unmasked.
  41  *
  42  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  43  * we leave them always unmasked in IMR and then control enabling them through
  44  * PIPESTAT alone.
  45  */
  46 #define I915_INTERRUPT_ENABLE_FIX (I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
  47                                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
  48
  49 /** Interrupts that we mask and unmask at runtime. */
  50 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  51
  52 /** These are all of the interrupts used by the driver */
  53 #define I915_INTERRUPT_ENABLE_MASK (I915_INTERRUPT_ENABLE_FIX | \
  54                                     I915_INTERRUPT_ENABLE_VAR)
  55
  56 static inline void
  57 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
  58 {
  59         DRM_DEBUG("irq_enable_reg = 0x%08x, mask = 0x%08x\n",
  60             dev_priv->irq_mask_reg, mask);
  61         mask &= I915_INTERRUPT_ENABLE_VAR;
  62         if ((dev_priv->irq_mask_reg & mask) != 0) {
  63                 dev_priv->irq_mask_reg &= ~mask;
  64                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  65                 (void) I915_READ(IMR);
  66         }
  67 }
  68
  69 static inline void
  70 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
  71 {
  72         mask &= I915_INTERRUPT_ENABLE_VAR;
  73         if ((dev_priv->irq_mask_reg & mask) != mask) {
  74                 dev_priv->irq_mask_reg |= mask;
  75                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  76                 (void) I915_READ(IMR);
  77         }
  78 }
  79
  80 static inline u32
  81 i915_pipestat(int pipe)
  82 {
  83         if (pipe == 0)
  84             return PIPEASTAT;
  85         if (pipe == 1)
  86             return PIPEBSTAT;
  87         return -EINVAL;
  88 }
  89
  90 void
  91 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  92 {
  93         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  94                 u32 reg = i915_pipestat(pipe);
  95
  96                 dev_priv->pipestat[pipe] |= mask;
  97                 /* Enable the interrupt, clear any pending status */
  98                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  99                 (void) I915_READ(reg);
 100         }
 101 }
 102
 103 void
 104 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 105 {
 106         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 107                 u32 reg = i915_pipestat(pipe);
 108
 109                 dev_priv->pipestat[pipe] &= ~mask;
 110                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 111                 (void) I915_READ(reg);
 112         }
 113 }
 114
 115 /**
 116  * i915_pipe_enabled - check if a pipe is enabled
 117  * @dev: DRM device
 118  * @pipe: pipe to check
 119  *
 120  * Reading certain registers when the pipe is disabled can hang the chip.
 121  * Use this routine to make sure the PLL is running and the pipe is active
 122  * before reading such registers if unsure.
 123  */
 124 static int
 125 i915_pipe_enabled(struct drm_device *dev, int pipe)
 126 {
 127         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 128         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 129
 130         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 131                 return 1;
 132
 133         return 0;
 134 }
 135
 136 /* Called from drm generic code, passed a 'crtc', which
 137  * we use as a pipe index
 138  */
 139 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 140 {
 141         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 142         unsigned long high_frame;
 143         unsigned long low_frame;
 144         u32 high1, high2, low, count;
 145
 146         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 147         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 148
 149         if (!i915_pipe_enabled(dev, pipe)) {
 150                 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
 151                 return 0;
 152         }
 153
 154         /*
 155          * High & low register fields aren't synchronized, so make sure
 156          * we get a low value that's stable across two reads of the high
 157          * register.
 158          */
 159         do {
 160                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 161                          PIPE_FRAME_HIGH_SHIFT);
 162                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 163                         PIPE_FRAME_LOW_SHIFT);
 164                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 165                          PIPE_FRAME_HIGH_SHIFT);
 166         } while (high1 != high2);
 167
 168         count = (high1 << 8) | low;
 169
 170         return count;
 171 }
 172
 173 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 174 {
 175         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 176         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 177
 178         if (!i915_pipe_enabled(dev, pipe)) {
 179                 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
 180                 return 0;
 181         }
 182
 183         return I915_READ(reg);
 184 }
 185
 186 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 187 {
 188         struct drm_device *dev = (struct drm_device *) arg;
 189         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 190         u32 iir, new_iir;
 191         u32 pipea_stats, pipeb_stats;
 192
 193         atomic_inc(&dev_priv->irq_received);
 194
 195         for (iir = I915_READ(IIR) ; iir != 0 ; iir = new_iir) {
 196
 197                 pipea_stats = pipeb_stats = 0;
 198
 199                 /*
 200                  * Clear the PIPE(A|B)STAT regs before the IIR
 201                  */
 202                 if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
 203                         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 204                         pipea_stats = I915_READ(PIPEASTAT);
 205                         I915_WRITE(PIPEASTAT, pipea_stats);
 206                         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 207                 }
 208
 209                 if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
 210                         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 211                         pipeb_stats = I915_READ(PIPEBSTAT);
 212                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 213                         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 214                 }
 215
 216                 I915_WRITE(IIR, iir);
 217                 new_iir = I915_READ(IIR);
 218
 219                 DRM_DEBUG("iir = 0x%08x, pipestats a = 0x%08x, b = 0x%08x\n",
 220                     iir, pipea_stats, pipeb_stats);
 221
 222                 if (dev_priv->sarea_priv)
 223                         dev_priv->sarea_priv->last_dispatch =
 224                             READ_BREADCRUMB(dev_priv);
 225
 226                 if (iir & I915_USER_INTERRUPT) {
 227 #ifdef I915_HAVE_GEM
 228                         dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
 229 #endif
 230                         DRM_WAKEUP(&dev_priv->irq_queue);
 231                 }
 232
 233                 if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS |
 234                     PIPE_VBLANK_INTERRUPT_STATUS))
 235                         drm_handle_vblank(dev, 0);
 236
 237                 if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS |
 238                     PIPE_VBLANK_INTERRUPT_STATUS))
 239                         drm_handle_vblank(dev, 1);
 240 #ifdef __linux__
 241                 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 242                     (iir & I915_ASLE_INTERRUPT))
 243                         opregion_asle_intr(dev);
 244 #endif
 245         }
 246 }
 247
 248 static int i915_emit_irq(struct drm_device * dev)
 249 {
 250         drm_i915_private_t *dev_priv = dev->dev_private;
 251         RING_LOCALS;
 252
 253         i915_kernel_lost_context(dev);
 254
 255         DRM_DEBUG("\n");
 256
 257         dev_priv->counter++;
 258         if (dev_priv->counter > 0x7FFFFFFFUL)
 259                 dev_priv->counter = 1;
 260         if (dev_priv->sarea_priv)
 261                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 262
 263         BEGIN_LP_RING(4);
 264         OUT_RING(MI_STORE_DWORD_INDEX);
 265         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 266         OUT_RING(dev_priv->counter);
 267         OUT_RING(MI_USER_INTERRUPT);
 268         ADVANCE_LP_RING();
 269
 270         return dev_priv->counter;
 271 }
 272
 273 void i915_user_irq_get(struct drm_device *dev)
 274 {
 275         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 276         unsigned long irqflags;
 277
 278         DRM_DEBUG("\n");
 279         DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
 280         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
 281                 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 282         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
 283 }
 284
 285 void i915_user_irq_put(struct drm_device *dev)
 286 {
 287         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 288         unsigned long irqflags;
 289
 290         DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
 291 #ifdef __linux__
 292         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
 293 #endif
 294         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
 295                 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 296         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
 297 }
 298
 299 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 300 {
 301         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 302         int ret = 0;
 303
 304         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
 305                   READ_BREADCRUMB(dev_priv));
 306
 307         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 308                 if (dev_priv->sarea_priv) {
 309                         dev_priv->sarea_priv->last_dispatch =
 310                                 READ_BREADCRUMB(dev_priv);
 311                 }
 312                 return 0;
 313         }
 314
 315         if (dev_priv->sarea_priv)
 316                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 317
 318         i915_user_irq_get(dev);
 319         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 320                     READ_BREADCRUMB(dev_priv) >= irq_nr);
 321         i915_user_irq_put(dev);
 322
 323         if (ret == -EBUSY) {
 324                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 325                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 326         }
 327
 328         if (dev_priv->sarea_priv)
 329                 dev_priv->sarea_priv->last_dispatch =
 330                         READ_BREADCRUMB(dev_priv);
 331
 332         return ret;
 333 }
 334
 335 /* Needs the lock as it touches the ring.
 336  */
 337 int i915_irq_emit(struct drm_device *dev, void *data,
 338                          struct drm_file *file_priv)
 339 {
 340         drm_i915_private_t *dev_priv = dev->dev_private;
 341         drm_i915_irq_emit_t *emit = data;
 342         int result;
 343
 344         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 345
 346         if (!dev_priv) {
 347                 DRM_ERROR("called with no initialization\n");
 348                 return -EINVAL;
 349         }
 350
 351         result = i915_emit_irq(dev);
 352
 353         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 354                 DRM_ERROR("copy_to_user\n");
 355                 return -EFAULT;
 356         }
 357
 358         return 0;
 359 }
 360
 361 /* Doesn't need the hardware lock.
 362  */
 363 int i915_irq_wait(struct drm_device *dev, void *data,
 364                          struct drm_file *file_priv)
 365 {
 366         drm_i915_private_t *dev_priv = dev->dev_private;
 367         drm_i915_irq_wait_t *irqwait = data;
 368
 369         if (!dev_priv) {
 370                 DRM_ERROR("called with no initialization\n");
 371                 return -EINVAL;
 372         }
 373
 374         return i915_wait_irq(dev, irqwait->irq_seq);
 375 }
 376
 377 /* Called from drm generic code, passed 'crtc' which
 378  * we use as a pipe index
 379  */
 380 int i915_enable_vblank(struct drm_device *dev, int pipe)
 381 {
 382         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 383         unsigned long irqflags;
 384         u32 pipestat;
 385
 386         /*
 387          * Older chips didn't have the start vblank interrupt,
 388          * but
 389          */
 390         if (IS_I965G (dev))
 391                 pipestat = PIPE_START_VBLANK_INTERRUPT_ENABLE;
 392         else
 393                 pipestat = PIPE_VBLANK_INTERRUPT_ENABLE;
 394
 395         DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
 396         i915_enable_pipestat(dev_priv, pipe, pipestat);
 397         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
 398         return 0;
 399 }
 400
 401 /* Called from drm generic code, passed 'crtc' which
 402  * we use as a pipe index
 403  */
 404 void i915_disable_vblank(struct drm_device *dev, int pipe)
 405 {
 406         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 407         unsigned long irqflags;
 408
 409         DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
 410         i915_disable_pipestat(dev_priv, pipe,
 411             PIPE_START_VBLANK_INTERRUPT_ENABLE | PIPE_VBLANK_INTERRUPT_ENABLE);
 412         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
 413 }
 414
 415 /* Set the vblank monitor pipe
 416  */
 417 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 418                          struct drm_file *file_priv)
 419 {
 420         drm_i915_private_t *dev_priv = dev->dev_private;
 421
 422         if (!dev_priv) {
 423                 DRM_ERROR("called with no initialization\n");
 424                 return -EINVAL;
 425         }
 426
 427         return 0;
 428 }
 429
 430 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 431                          struct drm_file *file_priv)
 432 {
 433         drm_i915_private_t *dev_priv = dev->dev_private;
 434         drm_i915_vblank_pipe_t *pipe = data;
 435
 436         if (!dev_priv) {
 437                 DRM_ERROR("called with no initialization\n");
 438                 return -EINVAL;
 439         }
 440
 441         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 442
 443         return 0;
 444 }
 445
 446 /**
 447  * Schedule buffer swap at given vertical blank.
 448  */
 449 int i915_vblank_swap(struct drm_device *dev, void *data,
 450                      struct drm_file *file_priv)
 451 {
 452         /* The delayed swap mechanism was fundamentally racy, and has been
 453          * removed.  The model was that the client requested a delayed flip/swap
 454          * from the kernel, then waited for vblank before continuing to perform
 455          * rendering.  The problem was that the kernel might wake the client
 456          * up before it dispatched the vblank swap (since the lock has to be
 457          * held while touching the ringbuffer), in which case the client would
 458          * clear and start the next frame before the swap occurred, and
 459          * flicker would occur in addition to likely missing the vblank.
 460          *
 461          * In the absence of this ioctl, userland falls back to a correct path
 462          * of waiting for a vblank, then dispatching the swap on its own.
 463          * Context switching to userland and back is plenty fast enough for
 464          * meeting the requirements of vblank swapping.
 465          */
 466
 467         return -EINVAL;
 468 }
 469
 470 /* drm_dma.h hooks
 471 */
 472 void i915_driver_irq_preinstall(struct drm_device * dev)
 473 {
 474         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 475
 476         I915_WRITE(HWSTAM, 0xeffe);
 477         I915_WRITE(PIPEASTAT, 0);
 478         I915_WRITE(PIPEBSTAT, 0);
 479         I915_WRITE(IMR, 0xffffffff);
 480         I915_WRITE(IER, 0x0);
 481         (void) I915_READ(IER);
 482 }
 483
 484 int i915_driver_irq_postinstall(struct drm_device *dev)
 485 {
 486         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 487
 488         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 489
 490         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 491
 492         /* Unmask the interrupts that we always want on. */
 493         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
 494
 495         dev_priv->pipestat[0] = 0;
 496         dev_priv->pipestat[1] = 0;
 497
 498         /* Disable pipe interrupt enables, clear pending pipe status */
 499         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
 500         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
 501
 502         /* Clear pending interrupt status */
 503         I915_WRITE(IIR, I915_READ(IIR));
 504
 505         I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
 506         I915_WRITE(IMR, dev_priv->irq_mask_reg);
 507         (void) I915_READ(IER);
 508 #ifdef __linux__
 509         opregion_enable_asle(dev);
 510 #endif
 511         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
 512
 513         i915_enable_vblank(dev, 0);
 514         i915_enable_vblank(dev, 1);
 515
 516         return 0;
 517 }
 518
 519 void i915_driver_irq_uninstall(struct drm_device * dev)
 520 {
 521         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 522
 523         if (!dev_priv)
 524                 return;
 525
 526         dev_priv->vblank_pipe = 0;
 527
 528         I915_WRITE(HWSTAM, 0xffffffff);
 529         I915_WRITE(PIPEASTAT, 0);
 530         I915_WRITE(PIPEBSTAT, 0);
 531         I915_WRITE(IMR, 0xffffffff);
 532         I915_WRITE(IER, 0x0);
 533
 534         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
 535         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
 536         I915_WRITE(IIR, I915_READ(IIR));
 537 }