1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD$");
32 * The Bridge device's PCI config space has information about the
33 * fb aperture size and the amount of pre-reserved memory.
35 #define INTEL_GMCH_CTRL 0x52
36 #define INTEL_GMCH_ENABLED 0x4
37 #define INTEL_GMCH_MEM_MASK 0x1
38 #define INTEL_GMCH_MEM_64M 0x1
39 #define INTEL_GMCH_MEM_128M 0
41 #define INTEL_855_GMCH_GMS_MASK (0x7 << 4)
42 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
43 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
44 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
45 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
46 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
47 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
49 #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
50 #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
52 /* PCI config space */
54 #define HPLLCC 0xc0 /* 855 only */
55 #define GC_CLOCK_CONTROL_MASK (3 << 0)
56 #define GC_CLOCK_133_200 (0 << 0)
57 #define GC_CLOCK_100_200 (1 << 0)
58 #define GC_CLOCK_100_133 (2 << 0)
59 #define GC_CLOCK_166_250 (3 << 0)
60 #define GCFGC 0xf0 /* 915+ only */
61 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
62 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
63 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
64 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
69 #define VGA_ST01_MDA 0x3ba
70 #define VGA_ST01_CGA 0x3da
72 #define VGA_MSR_WRITE 0x3c2
73 #define VGA_MSR_READ 0x3cc
74 #define VGA_MSR_MEM_EN (1<<1)
75 #define VGA_MSR_CGA_MODE (1<<0)
77 #define VGA_SR_INDEX 0x3c4
78 #define VGA_SR_DATA 0x3c5
80 #define VGA_AR_INDEX 0x3c0
81 #define VGA_AR_VID_EN (1<<5)
82 #define VGA_AR_DATA_WRITE 0x3c0
83 #define VGA_AR_DATA_READ 0x3c1
85 #define VGA_GR_INDEX 0x3ce
86 #define VGA_GR_DATA 0x3cf
88 #define VGA_GR_MEM_READ_MODE_SHIFT 3
89 #define VGA_GR_MEM_READ_MODE_PLANE 1
91 #define VGA_GR_MEM_MODE_MASK 0xc
92 #define VGA_GR_MEM_MODE_SHIFT 2
93 #define VGA_GR_MEM_A0000_AFFFF 0
94 #define VGA_GR_MEM_A0000_BFFFF 1
95 #define VGA_GR_MEM_B0000_B7FFF 2
96 #define VGA_GR_MEM_B0000_BFFFF 3
98 #define VGA_DACMASK 0x3c6
99 #define VGA_DACRX 0x3c7
100 #define VGA_DACWX 0x3c8
101 #define VGA_DACDATA 0x3c9
103 #define VGA_CR_INDEX_MDA 0x3b4
104 #define VGA_CR_DATA_MDA 0x3b5
105 #define VGA_CR_INDEX_CGA 0x3d4
106 #define VGA_CR_DATA_CGA 0x3d5
109 * Memory interface instructions used by the kernel
111 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
113 #define MI_NOOP MI_INSTR(0, 0)
114 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
115 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
116 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
117 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
118 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
119 #define MI_FLUSH MI_INSTR(0x04, 0)
120 #define MI_READ_FLUSH (1 << 0)
121 #define MI_EXE_FLUSH (1 << 1)
122 #define MI_NO_WRITE_FLUSH (1 << 2)
123 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
124 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
125 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
126 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
127 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
128 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
129 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
130 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
131 #define MI_STORE_DWORD_INDEX_SHIFT 2
132 #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
133 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
134 #define MI_BATCH_NON_SECURE (1)
135 #define MI_BATCH_NON_SECURE_I965 (1<<8)
136 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
139 * 3D instructions used by the kernel
141 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
143 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
144 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
145 #define SC_UPDATE_SCISSOR (0x1<<1)
146 #define SC_ENABLE_MASK (0x1<<0)
147 #define SC_ENABLE (0x1<<0)
148 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
149 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
150 #define SCI_YMIN_MASK (0xffff<<16)
151 #define SCI_XMIN_MASK (0xffff<<0)
152 #define SCI_YMAX_MASK (0xffff<<16)
153 #define SCI_XMAX_MASK (0xffff<<0)
154 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
155 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
156 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
157 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
158 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
159 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
160 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
161 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
162 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
163 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
164 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
165 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
166 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
167 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
168 #define BLT_DEPTH_8 (0<<24)
169 #define BLT_DEPTH_16_565 (1<<24)
170 #define BLT_DEPTH_16_1555 (2<<24)
171 #define BLT_DEPTH_32 (3<<24)
172 #define BLT_ROP_GXCOPY (0xcc<<16)
173 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
174 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
175 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
176 #define ASYNC_FLIP (1<<22)
177 #define DISPLAY_PLANE_A (0<<20)
178 #define DISPLAY_PLANE_B (1<<20)
181 * Instruction and interrupt control regs
184 #define PRB0_TAIL 0x02030
185 #define PRB0_HEAD 0x02034
186 #define PRB0_START 0x02038
187 #define PRB0_CTL 0x0203c
188 #define TAIL_ADDR 0x001FFFF8
189 #define HEAD_WRAP_COUNT 0xFFE00000
190 #define HEAD_WRAP_ONE 0x00200000
191 #define HEAD_ADDR 0x001FFFFC
192 #define RING_NR_PAGES 0x001FF000
193 #define RING_REPORT_MASK 0x00000006
194 #define RING_REPORT_64K 0x00000002
195 #define RING_REPORT_128K 0x00000004
196 #define RING_NO_REPORT 0x00000000
197 #define RING_VALID_MASK 0x00000001
198 #define RING_VALID 0x00000001
199 #define RING_INVALID 0x00000000
200 #define PRB1_TAIL 0x02040 /* 915+ only */
201 #define PRB1_HEAD 0x02044 /* 915+ only */
202 #define PRB1_START 0x02048 /* 915+ only */
203 #define PRB1_CTL 0x0204c /* 915+ only */
204 #define ACTHD_I965 0x02074
205 #define HWS_PGA 0x02080
206 #define HWS_ADDRESS_MASK 0xfffff000
207 #define HWS_START_ADDRESS_SHIFT 4
208 #define IPEIR 0x02088
209 #define NOPID 0x02094
210 #define HWSTAM 0x02098
211 #define SCPD0 0x0209c /* 915+ only */
216 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
217 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
218 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
219 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14)
220 #define I915_HWB_OOM_INTERRUPT (1<<13)
221 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
222 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
223 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
224 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
225 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
226 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
227 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
228 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
229 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
230 #define I915_DEBUG_INTERRUPT (1<<2)
231 #define I915_USER_INTERRUPT (1<<1)
232 #define I915_ASLE_INTERRUPT (1<<0)
236 #define INSTPM 0x020c0
237 #define ACTHD 0x020c8
238 #define FW_BLC 0x020d8
239 #define FW_BLC_SELF 0x020e0 /* 915+ only */
240 #define MI_ARB_STATE 0x020e4 /* 915+ only */
241 #define CACHE_MODE_0 0x02120 /* 915+ only */
242 #define CM0_MASK_SHIFT 16
243 #define CM0_IZ_OPT_DISABLE (1<<6)
244 #define CM0_ZR_OPT_DISABLE (1<<5)
245 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
246 #define CM0_COLOR_EVICT_DISABLE (1<<3)
247 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
248 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
249 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
252 * Framebuffer compression (915+ only)
255 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
256 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
257 #define FBC_CONTROL 0x03208
258 #define FBC_CTL_EN (1<<31)
259 #define FBC_CTL_PERIODIC (1<<30)
260 #define FBC_CTL_INTERVAL_SHIFT (16)
261 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
262 #define FBC_CTL_STRIDE_SHIFT (5)
263 #define FBC_CTL_FENCENO (1<<0)
264 #define FBC_COMMAND 0x0320c
265 #define FBC_CMD_COMPRESS (1<<0)
266 #define FBC_STATUS 0x03210
267 #define FBC_STAT_COMPRESSING (1<<31)
268 #define FBC_STAT_COMPRESSED (1<<30)
269 #define FBC_STAT_MODIFIED (1<<29)
270 #define FBC_STAT_CURRENT_LINE (1<<0)
271 #define FBC_CONTROL2 0x03214
272 #define FBC_CTL_FENCE_DBL (0<<4)
273 #define FBC_CTL_IDLE_IMM (0<<2)
274 #define FBC_CTL_IDLE_FULL (1<<2)
275 #define FBC_CTL_IDLE_LINE (2<<2)
276 #define FBC_CTL_IDLE_DEBUG (3<<2)
277 #define FBC_CTL_CPU_FENCE (1<<1)
278 #define FBC_CTL_PLANEA (0<<0)
279 #define FBC_CTL_PLANEB (1<<0)
280 #define FBC_FENCE_OFF 0x0321b
282 #define FBC_LL_SIZE (1536)
295 # define GPIO_CLOCK_DIR_MASK (1 << 0)
296 # define GPIO_CLOCK_DIR_IN (0 << 1)
297 # define GPIO_CLOCK_DIR_OUT (1 << 1)
298 # define GPIO_CLOCK_VAL_MASK (1 << 2)
299 # define GPIO_CLOCK_VAL_OUT (1 << 3)
300 # define GPIO_CLOCK_VAL_IN (1 << 4)
301 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
302 # define GPIO_DATA_DIR_MASK (1 << 8)
303 # define GPIO_DATA_DIR_IN (0 << 9)
304 # define GPIO_DATA_DIR_OUT (1 << 9)
305 # define GPIO_DATA_VAL_MASK (1 << 10)
306 # define GPIO_DATA_VAL_OUT (1 << 11)
307 # define GPIO_DATA_VAL_IN (1 << 12)
308 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
311 * Clock control & power management
316 #define VGA_PD 0x6010
317 #define VGA0_PD_P2_DIV_4 (1 << 7)
318 #define VGA0_PD_P1_DIV_2 (1 << 5)
319 #define VGA0_PD_P1_SHIFT 0
320 #define VGA0_PD_P1_MASK (0x1f << 0)
321 #define VGA1_PD_P2_DIV_4 (1 << 15)
322 #define VGA1_PD_P1_DIV_2 (1 << 13)
323 #define VGA1_PD_P1_SHIFT 8
324 #define VGA1_PD_P1_MASK (0x1f << 8)
325 #define DPLL_A 0x06014
326 #define DPLL_B 0x06018
327 #define DPLL_VCO_ENABLE (1 << 31)
328 #define DPLL_DVO_HIGH_SPEED (1 << 30)
329 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
330 #define DPLL_VGA_MODE_DIS (1 << 28)
331 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
332 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
333 #define DPLL_MODE_MASK (3 << 26)
334 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
335 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
336 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
337 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
338 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
339 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
341 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
342 #define I915_CRC_ERROR_ENABLE (1UL<<29)
343 #define I915_CRC_DONE_ENABLE (1UL<<28)
344 #define I915_GMBUS_EVENT_ENABLE (1UL<<27)
345 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
346 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
347 #define I915_DPST_EVENT_ENABLE (1UL<<23)
348 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
349 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
350 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
351 #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
352 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
353 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
354 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
355 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
356 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
357 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
358 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
359 #define I915_DPST_EVENT_STATUS (1UL<<7)
360 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
361 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
362 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
363 #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
364 #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
365 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
367 #define SRX_INDEX 0x3c4
368 #define SRX_DATA 0x3c5
370 #define SR01_SCREEN_OFF (1<<5)
373 #define PPCR_ON (1<<0)
376 #define DVOB_ON (1<<31)
378 #define DVOC_ON (1<<31)
380 #define LVDS_ON (1<<31)
383 #define ADPA_DPMS_MASK (~(3<<10))
384 #define ADPA_DPMS_ON (0<<10)
385 #define ADPA_DPMS_SUSPEND (1<<10)
386 #define ADPA_DPMS_STANDBY (2<<10)
387 #define ADPA_DPMS_OFF (3<<10)
389 #define RING_TAIL 0x00
390 #define TAIL_ADDR 0x001FFFF8
391 #define RING_HEAD 0x04
392 #define HEAD_WRAP_COUNT 0xFFE00000
393 #define HEAD_WRAP_ONE 0x00200000
394 #define HEAD_ADDR 0x001FFFFC
395 #define RING_START 0x08
396 #define START_ADDR 0xFFFFF000
397 #define RING_LEN 0x0C
398 #define RING_NR_PAGES 0x001FF000
399 #define RING_REPORT_MASK 0x00000006
400 #define RING_REPORT_64K 0x00000002
401 #define RING_REPORT_128K 0x00000004
402 #define RING_NO_REPORT 0x00000000
403 #define RING_VALID_MASK 0x00000001
404 #define RING_VALID 0x00000001
405 #define RING_INVALID 0x00000000
407 /* Scratch pad debug 0 reg:
409 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
411 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
412 * this field (only one bit may be set).
414 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
415 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
416 /* i830, required in DVO non-gang */
417 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
418 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
419 #define PLL_REF_INPUT_DREFCLK (0 << 13)
420 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
421 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
422 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
423 #define PLL_REF_INPUT_MASK (3 << 13)
424 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
426 * Parallel to Serial Load Pulse phase selection.
427 * Selects the phase for the 10X DPLL clock for the PCIe
428 * digital display port. The range is 4 to 13; 10 or more
429 * is just a flip delay. The default is 6
431 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
432 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
434 * SDVO multiplier for 945G/GM. Not used on 965.
436 #define SDVO_MULTIPLIER_MASK 0x000000ff
437 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
438 #define SDVO_MULTIPLIER_SHIFT_VGA 0
439 #define DPLL_A_MD 0x0601c /* 965+ only */
441 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
443 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
445 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
446 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
447 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
448 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
449 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
451 * SDVO/UDI pixel multiplier.
453 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
454 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
455 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
456 * dummy bytes in the datastream at an increased clock rate, with both sides of
457 * the link knowing how many bytes are fill.
459 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
460 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
461 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
462 * through an SDVO command.
464 * This register field has values of multiplication factor minus 1, with
465 * a maximum multiplier of 5 for SDVO.
467 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
468 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
470 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
471 * This best be set to the default value (3) or the CRT won't work. No,
472 * I don't entirely understand what this does...
474 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
475 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
476 #define DPLL_B_MD 0x06020 /* 965+ only */
481 #define FP_N_DIV_MASK 0x003f0000
482 #define FP_N_DIV_SHIFT 16
483 #define FP_M1_DIV_MASK 0x00003f00
484 #define FP_M1_DIV_SHIFT 8
485 #define FP_M2_DIV_MASK 0x0000003f
486 #define FP_M2_DIV_SHIFT 0
487 #define DPLL_TEST 0x606c
488 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
489 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
490 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
491 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
492 #define DPLLB_TEST_N_BYPASS (1 << 19)
493 #define DPLLB_TEST_M_BYPASS (1 << 18)
494 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
495 #define DPLLA_TEST_N_BYPASS (1 << 3)
496 #define DPLLA_TEST_M_BYPASS (1 << 2)
497 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
498 #define D_STATE 0x6104
499 #define CG_2D_DIS 0x6200
500 #define CG_3D_DIS 0x6204
506 #define PALETTE_A 0x0a000
507 #define PALETTE_B 0x0a800
514 * This mirrors the MCHBAR MMIO space whose location is determined by
515 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
516 * every way. It is not accessible from the CP register read instructions.
519 #define MCHBAR_MIRROR_BASE 0x10000
521 /** 915-945 and GM965 MCH register controlling DRAM channel access */
523 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
524 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
525 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
526 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
527 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
529 /** 965 MCH register controlling DRAM channel configuration */
530 #define C0DRB3 0x10206
531 #define C1DRB3 0x10606
537 #define OVADD 0x30000
538 #define DOVSTA 0x30008
539 #define OC_BUF (0x3<<20)
540 #define OGAMC5 0x30010
541 #define OGAMC4 0x30014
542 #define OGAMC3 0x30018
543 #define OGAMC2 0x3001c
544 #define OGAMC1 0x30020
545 #define OGAMC0 0x30024
548 * Display engine regs
551 /* Pipe A timing regs */
552 #define HTOTAL_A 0x60000
553 #define HBLANK_A 0x60004
554 #define HSYNC_A 0x60008
555 #define VTOTAL_A 0x6000c
556 #define VBLANK_A 0x60010
557 #define VSYNC_A 0x60014
558 #define PIPEASRC 0x6001c
559 #define BCLRPAT_A 0x60020
561 /* Pipe B timing regs */
562 #define HTOTAL_B 0x61000
563 #define HBLANK_B 0x61004
564 #define HSYNC_B 0x61008
565 #define VTOTAL_B 0x6100c
566 #define VBLANK_B 0x61010
567 #define VSYNC_B 0x61014
568 #define PIPEBSRC 0x6101c
569 #define BCLRPAT_B 0x61020
571 /* VGA port control */
573 #define ADPA_DAC_ENABLE (1<<31)
574 #define ADPA_DAC_DISABLE 0
575 #define ADPA_PIPE_SELECT_MASK (1<<30)
576 #define ADPA_PIPE_A_SELECT 0
577 #define ADPA_PIPE_B_SELECT (1<<30)
578 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
579 #define ADPA_SETS_HVPOLARITY 0
580 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
581 #define ADPA_VSYNC_CNTL_ENABLE 0
582 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
583 #define ADPA_HSYNC_CNTL_ENABLE 0
584 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
585 #define ADPA_VSYNC_ACTIVE_LOW 0
586 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
587 #define ADPA_HSYNC_ACTIVE_LOW 0
588 #define ADPA_DPMS_MASK (~(3<<10))
589 #define ADPA_DPMS_ON (0<<10)
590 #define ADPA_DPMS_SUSPEND (1<<10)
591 #define ADPA_DPMS_STANDBY (2<<10)
592 #define ADPA_DPMS_OFF (3<<10)
594 /* Hotplug control (945+ only) */
595 #define PORT_HOTPLUG_EN 0x61110
596 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
597 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
598 #define TV_HOTPLUG_INT_EN (1 << 18)
599 #define CRT_HOTPLUG_INT_EN (1 << 9)
600 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
602 #define PORT_HOTPLUG_STAT 0x61114
603 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
604 #define TV_HOTPLUG_INT_STATUS (1 << 10)
605 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
606 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
607 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
608 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
609 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
610 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
612 /* SDVO port control */
613 #define SDVOB 0x61140
614 #define SDVOC 0x61160
615 #define SDVO_ENABLE (1 << 31)
616 #define SDVO_PIPE_B_SELECT (1 << 30)
617 #define SDVO_STALL_SELECT (1 << 29)
618 #define SDVO_INTERRUPT_ENABLE (1 << 26)
620 * 915G/GM SDVO pixel multiplier.
622 * Programmed value is multiplier - 1, up to 5x.
624 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
626 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
627 #define SDVO_PORT_MULTIPLY_SHIFT 23
628 #define SDVO_PHASE_SELECT_MASK (15 << 19)
629 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
630 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
631 #define SDVOC_GANG_MODE (1 << 16)
632 #define SDVO_BORDER_ENABLE (1 << 7)
633 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
634 #define SDVO_DETECTED (1 << 2)
635 /* Bits to be preserved when writing */
636 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
637 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
639 /* DVO port control */
643 #define DVO_ENABLE (1 << 31)
644 #define DVO_PIPE_B_SELECT (1 << 30)
645 #define DVO_PIPE_STALL_UNUSED (0 << 28)
646 #define DVO_PIPE_STALL (1 << 28)
647 #define DVO_PIPE_STALL_TV (2 << 28)
648 #define DVO_PIPE_STALL_MASK (3 << 28)
649 #define DVO_USE_VGA_SYNC (1 << 15)
650 #define DVO_DATA_ORDER_I740 (0 << 14)
651 #define DVO_DATA_ORDER_FP (1 << 14)
652 #define DVO_VSYNC_DISABLE (1 << 11)
653 #define DVO_HSYNC_DISABLE (1 << 10)
654 #define DVO_VSYNC_TRISTATE (1 << 9)
655 #define DVO_HSYNC_TRISTATE (1 << 8)
656 #define DVO_BORDER_ENABLE (1 << 7)
657 #define DVO_DATA_ORDER_GBRG (1 << 6)
658 #define DVO_DATA_ORDER_RGGB (0 << 6)
659 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
660 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
661 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
662 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
663 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
664 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
665 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
666 #define DVO_PRESERVE_MASK (0x7<<24)
667 #define DVOA_SRCDIM 0x61124
668 #define DVOB_SRCDIM 0x61144
669 #define DVOC_SRCDIM 0x61164
670 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
671 #define DVO_SRCDIM_VERTICAL_SHIFT 0
673 /* LVDS port control */
676 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
677 * the DPLL semantics change when the LVDS is assigned to that pipe.
679 #define LVDS_PORT_EN (1 << 31)
680 /* Selects pipe B for LVDS data. Must be set on pre-965. */
681 #define LVDS_PIPEB_SELECT (1 << 30)
683 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
686 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
687 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
688 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
690 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
691 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
694 #define LVDS_A3_POWER_MASK (3 << 6)
695 #define LVDS_A3_POWER_DOWN (0 << 6)
696 #define LVDS_A3_POWER_UP (3 << 6)
698 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
701 #define LVDS_CLKB_POWER_MASK (3 << 4)
702 #define LVDS_CLKB_POWER_DOWN (0 << 4)
703 #define LVDS_CLKB_POWER_UP (3 << 4)
705 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
706 * setting for whether we are in dual-channel mode. The B3 pair will
707 * additionally only be powered up when LVDS_A3_POWER_UP is set.
709 #define LVDS_B0B3_POWER_MASK (3 << 2)
710 #define LVDS_B0B3_POWER_DOWN (0 << 2)
711 #define LVDS_B0B3_POWER_UP (3 << 2)
713 /* Panel power sequencing */
714 #define PP_STATUS 0x61200
715 #define PP_ON (1 << 31)
717 * Indicates that all dependencies of the panel are on:
721 * - LVDS/DVOB/DVOC on
723 #define PP_READY (1 << 30)
724 #define PP_SEQUENCE_NONE (0 << 28)
725 #define PP_SEQUENCE_ON (1 << 28)
726 #define PP_SEQUENCE_OFF (2 << 28)
727 #define PP_SEQUENCE_MASK 0x30000000
728 #define PP_CONTROL 0x61204
729 #define POWER_TARGET_ON (1 << 0)
730 #define PP_ON_DELAYS 0x61208
731 #define PP_OFF_DELAYS 0x6120c
732 #define PP_DIVISOR 0x61210
735 #define PFIT_CONTROL 0x61230
736 #define PFIT_ENABLE (1 << 31)
737 #define PFIT_PIPE_MASK (3 << 29)
738 #define PFIT_PIPE_SHIFT 29
739 #define VERT_INTERP_DISABLE (0 << 10)
740 #define VERT_INTERP_BILINEAR (1 << 10)
741 #define VERT_INTERP_MASK (3 << 10)
742 #define VERT_AUTO_SCALE (1 << 9)
743 #define HORIZ_INTERP_DISABLE (0 << 6)
744 #define HORIZ_INTERP_BILINEAR (1 << 6)
745 #define HORIZ_INTERP_MASK (3 << 6)
746 #define HORIZ_AUTO_SCALE (1 << 5)
747 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
748 #define PFIT_PGM_RATIOS 0x61234
749 #define PFIT_VERT_SCALE_MASK 0xfff00000
750 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
751 #define PFIT_AUTO_RATIOS 0x61238
753 /* Backlight control */
754 #define BLC_PWM_CTL 0x61254
755 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
756 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
757 #define BLM_COMBINATION_MODE (1 << 30)
759 * This is the most significant 15 bits of the number of backlight cycles in a
760 * complete cycle of the modulated backlight control.
762 * The actual value is this field multiplied by two.
764 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
765 #define BLM_LEGACY_MODE (1 << 16)
767 * This is the number of cycles out of the backlight modulation cycle for which
768 * the backlight is on.
770 * This field must be no greater than the number of cycles in the complete
771 * backlight modulation cycle.
773 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
774 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
776 /* TV port control */
777 #define TV_CTL 0x68000
778 /** Enables the TV encoder */
779 # define TV_ENC_ENABLE (1 << 31)
780 /** Sources the TV encoder input from pipe B instead of A. */
781 # define TV_ENC_PIPEB_SELECT (1 << 30)
782 /** Outputs composite video (DAC A only) */
783 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
784 /** Outputs SVideo video (DAC B/C) */
785 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
786 /** Outputs Component video (DAC A/B/C) */
787 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
788 /** Outputs Composite and SVideo (DAC A/B/C) */
789 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
790 # define TV_TRILEVEL_SYNC (1 << 21)
791 /** Enables slow sync generation (945GM only) */
792 # define TV_SLOW_SYNC (1 << 20)
793 /** Selects 4x oversampling for 480i and 576p */
794 # define TV_OVERSAMPLE_4X (0 << 18)
795 /** Selects 2x oversampling for 720p and 1080i */
796 # define TV_OVERSAMPLE_2X (1 << 18)
797 /** Selects no oversampling for 1080p */
798 # define TV_OVERSAMPLE_NONE (2 << 18)
799 /** Selects 8x oversampling */
800 # define TV_OVERSAMPLE_8X (3 << 18)
801 /** Selects progressive mode rather than interlaced */
802 # define TV_PROGRESSIVE (1 << 17)
803 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
804 # define TV_PAL_BURST (1 << 16)
805 /** Field for setting delay of Y compared to C */
806 # define TV_YC_SKEW_MASK (7 << 12)
807 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
808 # define TV_ENC_SDP_FIX (1 << 11)
810 * Enables a fix for the 915GM only.
812 * Not sure what it does.
814 # define TV_ENC_C0_FIX (1 << 10)
815 /** Bits that must be preserved by software */
816 # define TV_CTL_SAVE ((3 << 8) | (3 << 6))
817 # define TV_FUSE_STATE_MASK (3 << 4)
818 /** Read-only state that reports all features enabled */
819 # define TV_FUSE_STATE_ENABLED (0 << 4)
820 /** Read-only state that reports that Macrovision is disabled in hardware*/
821 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
822 /** Read-only state that reports that TV-out is disabled in hardware. */
823 # define TV_FUSE_STATE_DISABLED (2 << 4)
824 /** Normal operation */
825 # define TV_TEST_MODE_NORMAL (0 << 0)
826 /** Encoder test pattern 1 - combo pattern */
827 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
828 /** Encoder test pattern 2 - full screen vertical 75% color bars */
829 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
830 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
831 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
832 /** Encoder test pattern 4 - random noise */
833 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
834 /** Encoder test pattern 5 - linear color ramps */
835 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
837 * This test mode forces the DACs to 50% of full output.
839 * This is used for load detection in combination with TVDAC_SENSE_MASK
841 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
842 # define TV_TEST_MODE_MASK (7 << 0)
844 #define TV_DAC 0x68004
846 * Reports that DAC state change logic has reported change (RO).
848 * This gets cleared when TV_DAC_STATE_EN is cleared
850 # define TVDAC_STATE_CHG (1 << 31)
851 # define TVDAC_SENSE_MASK (7 << 28)
852 /** Reports that DAC A voltage is above the detect threshold */
853 # define TVDAC_A_SENSE (1 << 30)
854 /** Reports that DAC B voltage is above the detect threshold */
855 # define TVDAC_B_SENSE (1 << 29)
856 /** Reports that DAC C voltage is above the detect threshold */
857 # define TVDAC_C_SENSE (1 << 28)
859 * Enables DAC state detection logic, for load-based TV detection.
861 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
862 * to off, for load detection to work.
864 # define TVDAC_STATE_CHG_EN (1 << 27)
865 /** Sets the DAC A sense value to high */
866 # define TVDAC_A_SENSE_CTL (1 << 26)
867 /** Sets the DAC B sense value to high */
868 # define TVDAC_B_SENSE_CTL (1 << 25)
869 /** Sets the DAC C sense value to high */
870 # define TVDAC_C_SENSE_CTL (1 << 24)
871 /** Overrides the ENC_ENABLE and DAC voltage levels */
872 # define DAC_CTL_OVERRIDE (1 << 7)
873 /** Sets the slew rate. Must be preserved in software */
874 # define ENC_TVDAC_SLEW_FAST (1 << 6)
875 # define DAC_A_1_3_V (0 << 4)
876 # define DAC_A_1_1_V (1 << 4)
877 # define DAC_A_0_7_V (2 << 4)
878 # define DAC_A_OFF (3 << 4)
879 # define DAC_B_1_3_V (0 << 2)
880 # define DAC_B_1_1_V (1 << 2)
881 # define DAC_B_0_7_V (2 << 2)
882 # define DAC_B_OFF (3 << 2)
883 # define DAC_C_1_3_V (0 << 0)
884 # define DAC_C_1_1_V (1 << 0)
885 # define DAC_C_0_7_V (2 << 0)
886 # define DAC_C_OFF (3 << 0)
889 * CSC coefficients are stored in a floating point format with 9 bits of
890 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
891 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
892 * -1 (0x3) being the only legal negative value.
894 #define TV_CSC_Y 0x68010
895 # define TV_RY_MASK 0x07ff0000
896 # define TV_RY_SHIFT 16
897 # define TV_GY_MASK 0x00000fff
898 # define TV_GY_SHIFT 0
900 #define TV_CSC_Y2 0x68014
901 # define TV_BY_MASK 0x07ff0000
902 # define TV_BY_SHIFT 16
904 * Y attenuation for component video.
906 * Stored in 1.9 fixed point.
908 # define TV_AY_MASK 0x000003ff
909 # define TV_AY_SHIFT 0
911 #define TV_CSC_U 0x68018
912 # define TV_RU_MASK 0x07ff0000
913 # define TV_RU_SHIFT 16
914 # define TV_GU_MASK 0x000007ff
915 # define TV_GU_SHIFT 0
917 #define TV_CSC_U2 0x6801c
918 # define TV_BU_MASK 0x07ff0000
919 # define TV_BU_SHIFT 16
921 * U attenuation for component video.
923 * Stored in 1.9 fixed point.
925 # define TV_AU_MASK 0x000003ff
926 # define TV_AU_SHIFT 0
928 #define TV_CSC_V 0x68020
929 # define TV_RV_MASK 0x0fff0000
930 # define TV_RV_SHIFT 16
931 # define TV_GV_MASK 0x000007ff
932 # define TV_GV_SHIFT 0
934 #define TV_CSC_V2 0x68024
935 # define TV_BV_MASK 0x07ff0000
936 # define TV_BV_SHIFT 16
938 * V attenuation for component video.
940 * Stored in 1.9 fixed point.
942 # define TV_AV_MASK 0x000007ff
943 # define TV_AV_SHIFT 0
945 #define TV_CLR_KNOBS 0x68028
946 /** 2s-complement brightness adjustment */
947 # define TV_BRIGHTNESS_MASK 0xff000000
948 # define TV_BRIGHTNESS_SHIFT 24
949 /** Contrast adjustment, as a 2.6 unsigned floating point number */
950 # define TV_CONTRAST_MASK 0x00ff0000
951 # define TV_CONTRAST_SHIFT 16
952 /** Saturation adjustment, as a 2.6 unsigned floating point number */
953 # define TV_SATURATION_MASK 0x0000ff00
954 # define TV_SATURATION_SHIFT 8
955 /** Hue adjustment, as an integer phase angle in degrees */
956 # define TV_HUE_MASK 0x000000ff
957 # define TV_HUE_SHIFT 0
959 #define TV_CLR_LEVEL 0x6802c
960 /** Controls the DAC level for black */
961 # define TV_BLACK_LEVEL_MASK 0x01ff0000
962 # define TV_BLACK_LEVEL_SHIFT 16
963 /** Controls the DAC level for blanking */
964 # define TV_BLANK_LEVEL_MASK 0x000001ff
965 # define TV_BLANK_LEVEL_SHIFT 0
967 #define TV_H_CTL_1 0x68030
968 /** Number of pixels in the hsync. */
969 # define TV_HSYNC_END_MASK 0x1fff0000
970 # define TV_HSYNC_END_SHIFT 16
971 /** Total number of pixels minus one in the line (display and blanking). */
972 # define TV_HTOTAL_MASK 0x00001fff
973 # define TV_HTOTAL_SHIFT 0
975 #define TV_H_CTL_2 0x68034
976 /** Enables the colorburst (needed for non-component color) */
977 # define TV_BURST_ENA (1 << 31)
978 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
979 # define TV_HBURST_START_SHIFT 16
980 # define TV_HBURST_START_MASK 0x1fff0000
981 /** Length of the colorburst */
982 # define TV_HBURST_LEN_SHIFT 0
983 # define TV_HBURST_LEN_MASK 0x0001fff
985 #define TV_H_CTL_3 0x68038
986 /** End of hblank, measured in pixels minus one from start of hsync */
987 # define TV_HBLANK_END_SHIFT 16
988 # define TV_HBLANK_END_MASK 0x1fff0000
989 /** Start of hblank, measured in pixels minus one from start of hsync */
990 # define TV_HBLANK_START_SHIFT 0
991 # define TV_HBLANK_START_MASK 0x0001fff
993 #define TV_V_CTL_1 0x6803c
995 # define TV_NBR_END_SHIFT 16
996 # define TV_NBR_END_MASK 0x07ff0000
998 # define TV_VI_END_F1_SHIFT 8
999 # define TV_VI_END_F1_MASK 0x00003f00
1001 # define TV_VI_END_F2_SHIFT 0
1002 # define TV_VI_END_F2_MASK 0x0000003f
1004 #define TV_V_CTL_2 0x68040
1005 /** Length of vsync, in half lines */
1006 # define TV_VSYNC_LEN_MASK 0x07ff0000
1007 # define TV_VSYNC_LEN_SHIFT 16
1008 /** Offset of the start of vsync in field 1, measured in one less than the
1009 * number of half lines.
1011 # define TV_VSYNC_START_F1_MASK 0x00007f00
1012 # define TV_VSYNC_START_F1_SHIFT 8
1014 * Offset of the start of vsync in field 2, measured in one less than the
1015 * number of half lines.
1017 # define TV_VSYNC_START_F2_MASK 0x0000007f
1018 # define TV_VSYNC_START_F2_SHIFT 0
1020 #define TV_V_CTL_3 0x68044
1021 /** Enables generation of the equalization signal */
1022 # define TV_EQUAL_ENA (1 << 31)
1023 /** Length of vsync, in half lines */
1024 # define TV_VEQ_LEN_MASK 0x007f0000
1025 # define TV_VEQ_LEN_SHIFT 16
1026 /** Offset of the start of equalization in field 1, measured in one less than
1027 * the number of half lines.
1029 # define TV_VEQ_START_F1_MASK 0x0007f00
1030 # define TV_VEQ_START_F1_SHIFT 8
1032 * Offset of the start of equalization in field 2, measured in one less than
1033 * the number of half lines.
1035 # define TV_VEQ_START_F2_MASK 0x000007f
1036 # define TV_VEQ_START_F2_SHIFT 0
1038 #define TV_V_CTL_4 0x68048
1040 * Offset to start of vertical colorburst, measured in one less than the
1041 * number of lines from vertical start.
1043 # define TV_VBURST_START_F1_MASK 0x003f0000
1044 # define TV_VBURST_START_F1_SHIFT 16
1046 * Offset to the end of vertical colorburst, measured in one less than the
1047 * number of lines from the start of NBR.
1049 # define TV_VBURST_END_F1_MASK 0x000000ff
1050 # define TV_VBURST_END_F1_SHIFT 0
1052 #define TV_V_CTL_5 0x6804c
1054 * Offset to start of vertical colorburst, measured in one less than the
1055 * number of lines from vertical start.
1057 # define TV_VBURST_START_F2_MASK 0x003f0000
1058 # define TV_VBURST_START_F2_SHIFT 16
1060 * Offset to the end of vertical colorburst, measured in one less than the
1061 * number of lines from the start of NBR.
1063 # define TV_VBURST_END_F2_MASK 0x000000ff
1064 # define TV_VBURST_END_F2_SHIFT 0
1066 #define TV_V_CTL_6 0x68050
1068 * Offset to start of vertical colorburst, measured in one less than the
1069 * number of lines from vertical start.
1071 # define TV_VBURST_START_F3_MASK 0x003f0000
1072 # define TV_VBURST_START_F3_SHIFT 16
1074 * Offset to the end of vertical colorburst, measured in one less than the
1075 * number of lines from the start of NBR.
1077 # define TV_VBURST_END_F3_MASK 0x000000ff
1078 # define TV_VBURST_END_F3_SHIFT 0
1080 #define TV_V_CTL_7 0x68054
1082 * Offset to start of vertical colorburst, measured in one less than the
1083 * number of lines from vertical start.
1085 # define TV_VBURST_START_F4_MASK 0x003f0000
1086 # define TV_VBURST_START_F4_SHIFT 16
1088 * Offset to the end of vertical colorburst, measured in one less than the
1089 * number of lines from the start of NBR.
1091 # define TV_VBURST_END_F4_MASK 0x000000ff
1092 # define TV_VBURST_END_F4_SHIFT 0
1094 #define TV_SC_CTL_1 0x68060
1095 /** Turns on the first subcarrier phase generation DDA */
1096 # define TV_SC_DDA1_EN (1 << 31)
1097 /** Turns on the first subcarrier phase generation DDA */
1098 # define TV_SC_DDA2_EN (1 << 30)
1099 /** Turns on the first subcarrier phase generation DDA */
1100 # define TV_SC_DDA3_EN (1 << 29)
1101 /** Sets the subcarrier DDA to reset frequency every other field */
1102 # define TV_SC_RESET_EVERY_2 (0 << 24)
1103 /** Sets the subcarrier DDA to reset frequency every fourth field */
1104 # define TV_SC_RESET_EVERY_4 (1 << 24)
1105 /** Sets the subcarrier DDA to reset frequency every eighth field */
1106 # define TV_SC_RESET_EVERY_8 (2 << 24)
1107 /** Sets the subcarrier DDA to never reset the frequency */
1108 # define TV_SC_RESET_NEVER (3 << 24)
1109 /** Sets the peak amplitude of the colorburst.*/
1110 # define TV_BURST_LEVEL_MASK 0x00ff0000
1111 # define TV_BURST_LEVEL_SHIFT 16
1112 /** Sets the increment of the first subcarrier phase generation DDA */
1113 # define TV_SCDDA1_INC_MASK 0x00000fff
1114 # define TV_SCDDA1_INC_SHIFT 0
1116 #define TV_SC_CTL_2 0x68064
1117 /** Sets the rollover for the second subcarrier phase generation DDA */
1118 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
1119 # define TV_SCDDA2_SIZE_SHIFT 16
1120 /** Sets the increent of the second subcarrier phase generation DDA */
1121 # define TV_SCDDA2_INC_MASK 0x00007fff
1122 # define TV_SCDDA2_INC_SHIFT 0
1124 #define TV_SC_CTL_3 0x68068
1125 /** Sets the rollover for the third subcarrier phase generation DDA */
1126 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
1127 # define TV_SCDDA3_SIZE_SHIFT 16
1128 /** Sets the increent of the third subcarrier phase generation DDA */
1129 # define TV_SCDDA3_INC_MASK 0x00007fff
1130 # define TV_SCDDA3_INC_SHIFT 0
1132 #define TV_WIN_POS 0x68070
1133 /** X coordinate of the display from the start of horizontal active */
1134 # define TV_XPOS_MASK 0x1fff0000
1135 # define TV_XPOS_SHIFT 16
1136 /** Y coordinate of the display from the start of vertical active (NBR) */
1137 # define TV_YPOS_MASK 0x00000fff
1138 # define TV_YPOS_SHIFT 0
1140 #define TV_WIN_SIZE 0x68074
1141 /** Horizontal size of the display window, measured in pixels*/
1142 # define TV_XSIZE_MASK 0x1fff0000
1143 # define TV_XSIZE_SHIFT 16
1145 * Vertical size of the display window, measured in pixels.
1147 * Must be even for interlaced modes.
1149 # define TV_YSIZE_MASK 0x00000fff
1150 # define TV_YSIZE_SHIFT 0
1152 #define TV_FILTER_CTL_1 0x68080
1154 * Enables automatic scaling calculation.
1156 * If set, the rest of the registers are ignored, and the calculated values can
1157 * be read back from the register.
1159 # define TV_AUTO_SCALE (1 << 31)
1161 * Disables the vertical filter.
1163 * This is required on modes more than 1024 pixels wide */
1164 # define TV_V_FILTER_BYPASS (1 << 29)
1165 /** Enables adaptive vertical filtering */
1166 # define TV_VADAPT (1 << 28)
1167 # define TV_VADAPT_MODE_MASK (3 << 26)
1168 /** Selects the least adaptive vertical filtering mode */
1169 # define TV_VADAPT_MODE_LEAST (0 << 26)
1170 /** Selects the moderately adaptive vertical filtering mode */
1171 # define TV_VADAPT_MODE_MODERATE (1 << 26)
1172 /** Selects the most adaptive vertical filtering mode */
1173 # define TV_VADAPT_MODE_MOST (3 << 26)
1175 * Sets the horizontal scaling factor.
1177 * This should be the fractional part of the horizontal scaling factor divided
1178 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
1180 * (src width - 1) / ((oversample * dest width) - 1)
1182 # define TV_HSCALE_FRAC_MASK 0x00003fff
1183 # define TV_HSCALE_FRAC_SHIFT 0
1185 #define TV_FILTER_CTL_2 0x68084
1187 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1189 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
1191 # define TV_VSCALE_INT_MASK 0x00038000
1192 # define TV_VSCALE_INT_SHIFT 15
1194 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1196 * \sa TV_VSCALE_INT_MASK
1198 # define TV_VSCALE_FRAC_MASK 0x00007fff
1199 # define TV_VSCALE_FRAC_SHIFT 0
1201 #define TV_FILTER_CTL_3 0x68088
1203 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1205 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
1207 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1209 # define TV_VSCALE_IP_INT_MASK 0x00038000
1210 # define TV_VSCALE_IP_INT_SHIFT 15
1212 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1214 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1216 * \sa TV_VSCALE_IP_INT_MASK
1218 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
1219 # define TV_VSCALE_IP_FRAC_SHIFT 0
1221 #define TV_CC_CONTROL 0x68090
1222 # define TV_CC_ENABLE (1 << 31)
1224 * Specifies which field to send the CC data in.
1226 * CC data is usually sent in field 0.
1228 # define TV_CC_FID_MASK (1 << 27)
1229 # define TV_CC_FID_SHIFT 27
1230 /** Sets the horizontal position of the CC data. Usually 135. */
1231 # define TV_CC_HOFF_MASK 0x03ff0000
1232 # define TV_CC_HOFF_SHIFT 16
1233 /** Sets the vertical position of the CC data. Usually 21 */
1234 # define TV_CC_LINE_MASK 0x0000003f
1235 # define TV_CC_LINE_SHIFT 0
1237 #define TV_CC_DATA 0x68094
1238 # define TV_CC_RDY (1 << 31)
1239 /** Second word of CC data to be transmitted. */
1240 # define TV_CC_DATA_2_MASK 0x007f0000
1241 # define TV_CC_DATA_2_SHIFT 16
1242 /** First word of CC data to be transmitted. */
1243 # define TV_CC_DATA_1_MASK 0x0000007f
1244 # define TV_CC_DATA_1_SHIFT 0
1246 #define TV_H_LUMA_0 0x68100
1247 #define TV_H_LUMA_59 0x681ec
1248 #define TV_H_CHROMA_0 0x68200
1249 #define TV_H_CHROMA_59 0x682ec
1250 #define TV_V_LUMA_0 0x68300
1251 #define TV_V_LUMA_42 0x683a8
1252 #define TV_V_CHROMA_0 0x68400
1253 #define TV_V_CHROMA_42 0x684a8
1255 /* Display & cursor control */
1258 #define PIPEADSL 0x70000
1259 #define PIPEACONF 0x70008
1260 #define PIPEACONF_ENABLE (1<<31)
1261 #define PIPEACONF_DISABLE 0
1262 #define PIPEACONF_DOUBLE_WIDE (1<<30)
1263 #define I965_PIPECONF_ACTIVE (1<<30)
1264 #define PIPEACONF_SINGLE_WIDE 0
1265 #define PIPEACONF_PIPE_UNLOCKED 0
1266 #define PIPEACONF_PIPE_LOCKED (1<<25)
1267 #define PIPEACONF_PALETTE 0
1268 #define PIPEACONF_GAMMA (1<<24)
1269 #define PIPECONF_FORCE_BORDER (1<<25)
1270 #define PIPECONF_PROGRESSIVE (0 << 21)
1271 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1272 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1273 #define PIPEASTAT 0x70024
1274 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
1275 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
1276 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
1277 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
1278 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
1279 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
1280 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
1281 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
1282 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
1283 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
1284 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
1285 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
1286 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
1287 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
1288 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
1289 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
1290 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
1291 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
1292 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
1293 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
1294 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
1295 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
1296 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
1297 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
1298 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
1299 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
1300 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
1301 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
1302 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
1304 #define DSPARB 0x70030
1305 #define DSPARB_CSTART_MASK (0x7f << 7)
1306 #define DSPARB_CSTART_SHIFT 7
1307 #define DSPARB_BSTART_MASK (0x7f)
1308 #define DSPARB_BSTART_SHIFT 0
1310 * The two pipe frame counter registers are not synchronized, so
1311 * reading a stable value is somewhat tricky. The following code
1315 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1316 * PIPE_FRAME_HIGH_SHIFT;
1317 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
1318 * PIPE_FRAME_LOW_SHIFT);
1319 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1320 * PIPE_FRAME_HIGH_SHIFT);
1321 * } while (high1 != high2);
1322 * frame = (high1 << 8) | low1;
1324 #define PIPEAFRAMEHIGH 0x70040
1325 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
1326 #define PIPE_FRAME_HIGH_SHIFT 0
1327 #define PIPEAFRAMEPIXEL 0x70044
1328 #define PIPE_FRAME_LOW_MASK 0xff000000
1329 #define PIPE_FRAME_LOW_SHIFT 24
1330 #define PIPE_PIXEL_MASK 0x00ffffff
1331 #define PIPE_PIXEL_SHIFT 0
1332 /* GM45+ just has to be different */
1333 #define PIPEA_FRMCOUNT_GM45 0x70040
1334 #define PIPEA_FLIPCOUNT_GM45 0x70044
1336 /* Cursor A & B regs */
1337 #define CURACNTR 0x70080
1338 #define CURSOR_MODE_DISABLE 0x00
1339 #define CURSOR_MODE_64_32B_AX 0x07
1340 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
1341 #define MCURSOR_GAMMA_ENABLE (1 << 26)
1342 #define CURABASE 0x70084
1343 #define CURAPOS 0x70088
1344 #define CURSOR_POS_MASK 0x007FF
1345 #define CURSOR_POS_SIGN 0x8000
1346 #define CURSOR_X_SHIFT 0
1347 #define CURSOR_Y_SHIFT 16
1348 #define CURBCNTR 0x700c0
1349 #define CURBBASE 0x700c4
1350 #define CURBPOS 0x700c8
1352 /* Display A control */
1353 #define DSPACNTR 0x70180
1354 #define DISPLAY_PLANE_ENABLE (1<<31)
1355 #define DISPLAY_PLANE_DISABLE 0
1356 #define DISPPLANE_GAMMA_ENABLE (1<<30)
1357 #define DISPPLANE_GAMMA_DISABLE 0
1358 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1359 #define DISPPLANE_8BPP (0x2<<26)
1360 #define DISPPLANE_15_16BPP (0x4<<26)
1361 #define DISPPLANE_16BPP (0x5<<26)
1362 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1363 #define DISPPLANE_32BPP (0x7<<26)
1364 #define DISPPLANE_STEREO_ENABLE (1<<25)
1365 #define DISPPLANE_STEREO_DISABLE 0
1366 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
1367 #define DISPPLANE_SEL_PIPE_A 0
1368 #define DISPPLANE_SEL_PIPE_B (1<<24)
1369 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1370 #define DISPPLANE_SRC_KEY_DISABLE 0
1371 #define DISPPLANE_LINE_DOUBLE (1<<20)
1372 #define DISPPLANE_NO_LINE_DOUBLE 0
1373 #define DISPPLANE_STEREO_POLARITY_FIRST 0
1374 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1375 #define DSPAADDR 0x70184
1376 #define DSPASTRIDE 0x70188
1377 #define DSPAPOS 0x7018C /* reserved */
1378 #define DSPASIZE 0x70190
1379 #define DSPASURF 0x7019C /* 965+ only */
1380 #define DSPATILEOFF 0x701A4 /* 965+ only */
1383 #define SWF00 0x71410
1384 #define SWF01 0x71414
1385 #define SWF02 0x71418
1386 #define SWF03 0x7141c
1387 #define SWF04 0x71420
1388 #define SWF05 0x71424
1389 #define SWF06 0x71428
1390 #define SWF10 0x70410
1391 #define SWF11 0x70414
1392 #define SWF14 0x71420
1393 #define SWF30 0x72414
1394 #define SWF31 0x72418
1395 #define SWF32 0x7241c
1398 #define PIPEBDSL 0x71000
1399 #define PIPEBCONF 0x71008
1400 #define PIPEBSTAT 0x71024
1401 #define PIPEBFRAMEHIGH 0x71040
1402 #define PIPEBFRAMEPIXEL 0x71044
1403 #define PIPEB_FRMCOUNT_GM45 0x71040
1404 #define PIPEB_FLIPCOUNT_GM45 0x71044
1406 /* Display B control */
1407 #define DSPBCNTR 0x71180
1408 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1409 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
1410 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
1411 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1412 #define DSPBADDR 0x71184
1413 #define DSPBSTRIDE 0x71188
1414 #define DSPBPOS 0x7118C
1415 #define DSPBSIZE 0x71190
1416 #define DSPBSURF 0x7119C
1417 #define DSPBTILEOFF 0x711A4
1420 #define VGACNTRL 0x71400
1421 # define VGA_DISP_DISABLE (1 << 31)
1422 # define VGA_2X_MODE (1 << 30)
1423 # define VGA_PIPE_B_SELECT (1 << 29)
1425 #endif /* _I915_REG_H_ */
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