sys/dev/drm/radeon_irq.c

   1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
   2 /*-
   3  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  *    Michel D�zer <michel@daenzer.net>
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include "dev/drm/drmP.h"
  37 #include "dev/drm/drm.h"
  38 #include "dev/drm/radeon_drm.h"
  39 #include "dev/drm/radeon_drv.h"
  40
  41 void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
  42 {
  43         drm_radeon_private_t *dev_priv = dev->dev_private;
  44
  45         if (state)
  46                 dev_priv->irq_enable_reg |= mask;
  47         else
  48                 dev_priv->irq_enable_reg &= ~mask;
  49
  50         if (dev->irq_enabled)
  51                 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
  52 }
  53
  54 static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
  55 {
  56         drm_radeon_private_t *dev_priv = dev->dev_private;
  57
  58         if (state)
  59                 dev_priv->r500_disp_irq_reg |= mask;
  60         else
  61                 dev_priv->r500_disp_irq_reg &= ~mask;
  62
  63         if (dev->irq_enabled)
  64                 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
  65 }
  66
  67 int radeon_enable_vblank(struct drm_device *dev, int crtc)
  68 {
  69         drm_radeon_private_t *dev_priv = dev->dev_private;
  70
  71         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
  72                 switch (crtc) {
  73                 case 0:
  74                         r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
  75                         break;
  76                 case 1:
  77                         r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
  78                         break;
  79                 default:
  80                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
  81                                   crtc);
  82                         return EINVAL;
  83                 }
  84         } else {
  85                 switch (crtc) {
  86                 case 0:
  87                         radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
  88                         break;
  89                 case 1:
  90                         radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
  91                         break;
  92                 default:
  93                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
  94                                   crtc);
  95                         return EINVAL;
  96                 }
  97         }
  98
  99         return 0;
 100 }
 101
 102 void radeon_disable_vblank(struct drm_device *dev, int crtc)
 103 {
 104         drm_radeon_private_t *dev_priv = dev->dev_private;
 105
 106         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 107                 switch (crtc) {
 108                 case 0:
 109                         r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
 110                         break;
 111                 case 1:
 112                         r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
 113                         break;
 114                 default:
 115                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
 116                                   crtc);
 117                         break;
 118                 }
 119         } else {
 120                 switch (crtc) {
 121                 case 0:
 122                         radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
 123                         break;
 124                 case 1:
 125                         radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
 126                         break;
 127                 default:
 128                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
 129                                   crtc);
 130                         break;
 131                 }
 132         }
 133 }
 134
 135 static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, u32 *r500_disp_int)
 136 {
 137         u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
 138         u32 irq_mask = RADEON_SW_INT_TEST;
 139
 140         *r500_disp_int = 0;
 141         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 142                 /* vbl interrupts in a different place */
 143
 144                 if (irqs & R500_DISPLAY_INT_STATUS) {
 145                         /* if a display interrupt */
 146                         u32 disp_irq;
 147
 148                         disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
 149
 150                         *r500_disp_int = disp_irq;
 151                         if (disp_irq & R500_D1_VBLANK_INTERRUPT) {
 152                                 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
 153                         }
 154                         if (disp_irq & R500_D2_VBLANK_INTERRUPT) {
 155                                 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
 156                         }
 157                 }
 158                 irq_mask |= R500_DISPLAY_INT_STATUS;
 159         } else
 160                 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
 161
 162         irqs &= irq_mask;
 163
 164         if (irqs)
 165                 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
 166
 167         return irqs;
 168 }
 169
 170 /* Interrupts - Used for device synchronization and flushing in the
 171  * following circumstances:
 172  *
 173  * - Exclusive FB access with hw idle:
 174  *    - Wait for GUI Idle (?) interrupt, then do normal flush.
 175  *
 176  * - Frame throttling, NV_fence:
 177  *    - Drop marker irq's into command stream ahead of time.
 178  *    - Wait on irq's with lock *not held*
 179  *    - Check each for termination condition
 180  *
 181  * - Internally in cp_getbuffer, etc:
 182  *    - as above, but wait with lock held???
 183  *
 184  * NOTE: These functions are misleadingly named -- the irq's aren't
 185  * tied to dma at all, this is just a hangover from dri prehistory.
 186  */
 187
 188 irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
 189 {
 190         struct drm_device *dev = (struct drm_device *) arg;
 191         drm_radeon_private_t *dev_priv =
 192             (drm_radeon_private_t *) dev->dev_private;
 193         u32 stat;
 194         u32 r500_disp_int;
 195         u32 tmp;
 196
 197         /* Only consider the bits we're interested in - others could be used
 198          * outside the DRM
 199          */
 200         stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
 201         if (!stat)
 202                 return IRQ_NONE;
 203
 204         stat &= dev_priv->irq_enable_reg;
 205
 206         /* SW interrupt */
 207         if (stat & RADEON_SW_INT_TEST)
 208                 DRM_WAKEUP(&dev_priv->swi_queue);
 209
 210         /* VBLANK interrupt */
 211         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 212                 if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
 213                         drm_handle_vblank(dev, 0);
 214                 if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
 215                         drm_handle_vblank(dev, 1);
 216         } else {
 217                 if (stat & RADEON_CRTC_VBLANK_STAT)
 218                         drm_handle_vblank(dev, 0);
 219                 if (stat & RADEON_CRTC2_VBLANK_STAT)
 220                         drm_handle_vblank(dev, 1);
 221         }
 222         if (dev->msi_enabled) {
 223                 switch(dev_priv->flags & RADEON_FAMILY_MASK) {
 224                         case CHIP_RS400:
 225                         case CHIP_RS480:
 226                                 tmp = RADEON_READ(RADEON_AIC_CNTL) &
 227                                     ~RS400_MSI_REARM;
 228                                 RADEON_WRITE(RADEON_AIC_CNTL, tmp);
 229                                 RADEON_WRITE(RADEON_AIC_CNTL,
 230                                     tmp | RS400_MSI_REARM);
 231                                 break;
 232                         case CHIP_RS600:
 233                         case CHIP_RS690:
 234                         case CHIP_RS740:
 235                                 tmp = RADEON_READ(RADEON_BUS_CNTL) &
 236                                     ~RS600_MSI_REARM;
 237                                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 238                                 RADEON_WRITE(RADEON_BUS_CNTL, tmp |
 239                                     RS600_MSI_REARM);
 240                                 break;
 241                          default:
 242                                 tmp = RADEON_READ(RADEON_MSI_REARM_EN) &
 243                                     ~RV370_MSI_REARM_EN;
 244                                 RADEON_WRITE(RADEON_MSI_REARM_EN, tmp);
 245                                 RADEON_WRITE(RADEON_MSI_REARM_EN,
 246                                     tmp | RV370_MSI_REARM_EN);
 247                                 break;
 248                 }
 249         }
 250         return IRQ_HANDLED;
 251 }
 252
 253 static int radeon_emit_irq(struct drm_device * dev)
 254 {
 255         drm_radeon_private_t *dev_priv = dev->dev_private;
 256         unsigned int ret;
 257         RING_LOCALS;
 258
 259         atomic_inc(&dev_priv->swi_emitted);
 260         ret = atomic_read(&dev_priv->swi_emitted);
 261
 262         BEGIN_RING(4);
 263         OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
 264         OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
 265         ADVANCE_RING();
 266         COMMIT_RING();
 267
 268         return ret;
 269 }
 270
 271 static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
 272 {
 273         drm_radeon_private_t *dev_priv =
 274             (drm_radeon_private_t *) dev->dev_private;
 275         int ret = 0;
 276
 277         if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
 278                 return 0;
 279
 280         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 281
 282         DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
 283                     RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
 284
 285         return ret;
 286 }
 287
 288 u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
 289 {
 290         drm_radeon_private_t *dev_priv = dev->dev_private;
 291
 292         if (!dev_priv) {
 293                 DRM_ERROR("called with no initialization\n");
 294                 return -EINVAL;
 295         }
 296
 297         if (crtc < 0 || crtc > 1) {
 298                 DRM_ERROR("Invalid crtc %d\n", crtc);
 299                 return -EINVAL;
 300         }
 301
 302         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 303                 if (crtc == 0)
 304                         return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
 305                 else
 306                         return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
 307         } else {
 308                 if (crtc == 0)
 309                         return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
 310                 else
 311                         return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
 312         }
 313 }
 314
 315 /* Needs the lock as it touches the ring.
 316  */
 317 int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
 318 {
 319         drm_radeon_private_t *dev_priv = dev->dev_private;
 320         drm_radeon_irq_emit_t *emit = data;
 321         int result;
 322
 323         LOCK_TEST_WITH_RETURN(dev, file_priv);
 324
 325         if (!dev_priv) {
 326                 DRM_ERROR("called with no initialization\n");
 327                 return -EINVAL;
 328         }
 329
 330         result = radeon_emit_irq(dev);
 331
 332         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 333                 DRM_ERROR("copy_to_user\n");
 334                 return -EFAULT;
 335         }
 336
 337         return 0;
 338 }
 339
 340 /* Doesn't need the hardware lock.
 341  */
 342 int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
 343 {
 344         drm_radeon_private_t *dev_priv = dev->dev_private;
 345         drm_radeon_irq_wait_t *irqwait = data;
 346
 347         if (!dev_priv) {
 348                 DRM_ERROR("called with no initialization\n");
 349                 return -EINVAL;
 350         }
 351
 352         return radeon_wait_irq(dev, irqwait->irq_seq);
 353 }
 354
 355 /* drm_dma.h hooks
 356 */
 357 void radeon_driver_irq_preinstall(struct drm_device * dev)
 358 {
 359         drm_radeon_private_t *dev_priv =
 360             (drm_radeon_private_t *) dev->dev_private;
 361         u32 dummy;
 362
 363         /* Disable *all* interrupts */
 364         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
 365                 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 366         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 367
 368         /* Clear bits if they're already high */
 369         radeon_acknowledge_irqs(dev_priv, &dummy);
 370 }
 371
 372 int radeon_driver_irq_postinstall(struct drm_device * dev)
 373 {
 374         drm_radeon_private_t *dev_priv =
 375             (drm_radeon_private_t *) dev->dev_private;
 376
 377         atomic_set(&dev_priv->swi_emitted, 0);
 378         DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
 379
 380         dev->max_vblank_count = 0x001fffff;
 381
 382         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
 383
 384         return 0;
 385 }
 386
 387 void radeon_driver_irq_uninstall(struct drm_device * dev)
 388 {
 389         drm_radeon_private_t *dev_priv =
 390             (drm_radeon_private_t *) dev->dev_private;
 391         if (!dev_priv)
 392                 return;
 393
 394         dev_priv->irq_enabled = 0;
 395
 396         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
 397                 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 398         /* Disable *all* interrupts */
 399         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 400 }
 401
 402
 403 int radeon_vblank_crtc_get(struct drm_device *dev)
 404 {
 405         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 406
 407         return dev_priv->vblank_crtc;
 408 }
 409
 410 int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
 411 {
 412         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 413         if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
 414                 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
 415                 return -EINVAL;
 416         }
 417         dev_priv->vblank_crtc = (unsigned int)value;
 418         return 0;
 419 }