sys/dev/e1000/e1000_hw.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2008, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_HW_H_
  36 #define _E1000_HW_H_
  37
  38 #include "e1000_osdep.h"
  39 #include "e1000_regs.h"
  40 #include "e1000_defines.h"
  41
  42 struct e1000_hw;
  43
  44 #define E1000_DEV_ID_82542                    0x1000
  45 #define E1000_DEV_ID_82543GC_FIBER            0x1001
  46 #define E1000_DEV_ID_82543GC_COPPER           0x1004
  47 #define E1000_DEV_ID_82544EI_COPPER           0x1008
  48 #define E1000_DEV_ID_82544EI_FIBER            0x1009
  49 #define E1000_DEV_ID_82544GC_COPPER           0x100C
  50 #define E1000_DEV_ID_82544GC_LOM              0x100D
  51 #define E1000_DEV_ID_82540EM                  0x100E
  52 #define E1000_DEV_ID_82540EM_LOM              0x1015
  53 #define E1000_DEV_ID_82540EP_LOM              0x1016
  54 #define E1000_DEV_ID_82540EP                  0x1017
  55 #define E1000_DEV_ID_82540EP_LP               0x101E
  56 #define E1000_DEV_ID_82545EM_COPPER           0x100F
  57 #define E1000_DEV_ID_82545EM_FIBER            0x1011
  58 #define E1000_DEV_ID_82545GM_COPPER           0x1026
  59 #define E1000_DEV_ID_82545GM_FIBER            0x1027
  60 #define E1000_DEV_ID_82545GM_SERDES           0x1028
  61 #define E1000_DEV_ID_82546EB_COPPER           0x1010
  62 #define E1000_DEV_ID_82546EB_FIBER            0x1012
  63 #define E1000_DEV_ID_82546EB_QUAD_COPPER      0x101D
  64 #define E1000_DEV_ID_82546GB_COPPER           0x1079
  65 #define E1000_DEV_ID_82546GB_FIBER            0x107A
  66 #define E1000_DEV_ID_82546GB_SERDES           0x107B
  67 #define E1000_DEV_ID_82546GB_PCIE             0x108A
  68 #define E1000_DEV_ID_82546GB_QUAD_COPPER      0x1099
  69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
  70 #define E1000_DEV_ID_82541EI                  0x1013
  71 #define E1000_DEV_ID_82541EI_MOBILE           0x1018
  72 #define E1000_DEV_ID_82541ER_LOM              0x1014
  73 #define E1000_DEV_ID_82541ER                  0x1078
  74 #define E1000_DEV_ID_82541GI                  0x1076
  75 #define E1000_DEV_ID_82541GI_LF               0x107C
  76 #define E1000_DEV_ID_82541GI_MOBILE           0x1077
  77 #define E1000_DEV_ID_82547EI                  0x1019
  78 #define E1000_DEV_ID_82547EI_MOBILE           0x101A
  79 #define E1000_DEV_ID_82547GI                  0x1075
  80 #define E1000_DEV_ID_82571EB_COPPER           0x105E
  81 #define E1000_DEV_ID_82571EB_FIBER            0x105F
  82 #define E1000_DEV_ID_82571EB_SERDES           0x1060
  83 #define E1000_DEV_ID_82571EB_SERDES_DUAL      0x10D9
  84 #define E1000_DEV_ID_82571EB_SERDES_QUAD      0x10DA
  85 #define E1000_DEV_ID_82571EB_QUAD_COPPER      0x10A4
  86 #define E1000_DEV_ID_82571PT_QUAD_COPPER      0x10D5
  87 #define E1000_DEV_ID_82571EB_QUAD_FIBER       0x10A5
  88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP   0x10BC
  89 #define E1000_DEV_ID_82572EI_COPPER           0x107D
  90 #define E1000_DEV_ID_82572EI_FIBER            0x107E
  91 #define E1000_DEV_ID_82572EI_SERDES           0x107F
  92 #define E1000_DEV_ID_82572EI                  0x10B9
  93 #define E1000_DEV_ID_82573E                   0x108B
  94 #define E1000_DEV_ID_82573E_IAMT              0x108C
  95 #define E1000_DEV_ID_82573L                   0x109A
  96 #define E1000_DEV_ID_82574L                   0x10D3
  97 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT   0x1096
  98 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT   0x1098
  99 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT   0x10BA
 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT   0x10BB
 101 #define E1000_DEV_ID_ICH8_IGP_M_AMT           0x1049
 102 #define E1000_DEV_ID_ICH8_IGP_AMT             0x104A
 103 #define E1000_DEV_ID_ICH8_IGP_C               0x104B
 104 #define E1000_DEV_ID_ICH8_IFE                 0x104C
 105 #define E1000_DEV_ID_ICH8_IFE_GT              0x10C4
 106 #define E1000_DEV_ID_ICH8_IFE_G               0x10C5
 107 #define E1000_DEV_ID_ICH8_IGP_M               0x104D
 108 #define E1000_DEV_ID_ICH9_IGP_M               0x10BF
 109 #define E1000_DEV_ID_ICH9_IGP_M_AMT           0x10F5
 110 #define E1000_DEV_ID_ICH9_IGP_M_V             0x10CB
 111 #define E1000_DEV_ID_ICH9_IGP_AMT             0x10BD
 112 #define E1000_DEV_ID_ICH9_BM                  0x10E5
 113 #define E1000_DEV_ID_ICH9_IGP_C               0x294C
 114 #define E1000_DEV_ID_ICH9_IFE                 0x10C0
 115 #define E1000_DEV_ID_ICH9_IFE_GT              0x10C3
 116 #define E1000_DEV_ID_ICH9_IFE_G               0x10C2
 117 #define E1000_DEV_ID_ICH10_R_BM_LM            0x10CC
 118 #define E1000_DEV_ID_ICH10_R_BM_LF            0x10CD
 119 #define E1000_DEV_ID_ICH10_R_BM_V             0x10CE
 120 #define E1000_DEV_ID_ICH10_D_BM_LM            0x10DE
 121 #define E1000_DEV_ID_ICH10_D_BM_LF            0x10DF
 122 #define E1000_DEV_ID_82576                    0x10C9
 123 #define E1000_DEV_ID_82576_FIBER              0x10E6
 124 #define E1000_DEV_ID_82576_SERDES             0x10E7
 125 #define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
 126 #define E1000_DEV_ID_82576_VF                 0x10CA
 127 #define E1000_DEV_ID_82575EB_COPPER           0x10A7
 128 #define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
 129 #define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
 130 #define E1000_REVISION_0 0
 131 #define E1000_REVISION_1 1
 132 #define E1000_REVISION_2 2
 133 #define E1000_REVISION_3 3
 134 #define E1000_REVISION_4 4
 135
 136 #define E1000_FUNC_0     0
 137 #define E1000_FUNC_1     1
 138
 139 enum e1000_mac_type {
 140         e1000_undefined = 0,
 141         e1000_82542,
 142         e1000_82543,
 143         e1000_82544,
 144         e1000_82540,
 145         e1000_82545,
 146         e1000_82545_rev_3,
 147         e1000_82546,
 148         e1000_82546_rev_3,
 149         e1000_82541,
 150         e1000_82541_rev_2,
 151         e1000_82547,
 152         e1000_82547_rev_2,
 153         e1000_82571,
 154         e1000_82572,
 155         e1000_82573,
 156         e1000_82574,
 157         e1000_80003es2lan,
 158         e1000_ich8lan,
 159         e1000_ich9lan,
 160         e1000_ich10lan,
 161         e1000_82575,
 162         e1000_82576,
 163         e1000_vfadapt,
 164         e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
 165 };
 166
 167 enum e1000_media_type {
 168         e1000_media_type_unknown = 0,
 169         e1000_media_type_copper = 1,
 170         e1000_media_type_fiber = 2,
 171         e1000_media_type_internal_serdes = 3,
 172         e1000_num_media_types
 173 };
 174
 175 enum e1000_nvm_type {
 176         e1000_nvm_unknown = 0,
 177         e1000_nvm_none,
 178         e1000_nvm_eeprom_spi,
 179         e1000_nvm_eeprom_microwire,
 180         e1000_nvm_flash_hw,
 181         e1000_nvm_flash_sw
 182 };
 183
 184 enum e1000_nvm_override {
 185         e1000_nvm_override_none = 0,
 186         e1000_nvm_override_spi_small,
 187         e1000_nvm_override_spi_large,
 188         e1000_nvm_override_microwire_small,
 189         e1000_nvm_override_microwire_large
 190 };
 191
 192 enum e1000_phy_type {
 193         e1000_phy_unknown = 0,
 194         e1000_phy_none,
 195         e1000_phy_m88,
 196         e1000_phy_igp,
 197         e1000_phy_igp_2,
 198         e1000_phy_gg82563,
 199         e1000_phy_igp_3,
 200         e1000_phy_ife,
 201         e1000_phy_bm,
 202         e1000_phy_vf,
 203 };
 204
 205 enum e1000_bus_type {
 206         e1000_bus_type_unknown = 0,
 207         e1000_bus_type_pci,
 208         e1000_bus_type_pcix,
 209         e1000_bus_type_pci_express,
 210         e1000_bus_type_reserved
 211 };
 212
 213 enum e1000_bus_speed {
 214         e1000_bus_speed_unknown = 0,
 215         e1000_bus_speed_33,
 216         e1000_bus_speed_66,
 217         e1000_bus_speed_100,
 218         e1000_bus_speed_120,
 219         e1000_bus_speed_133,
 220         e1000_bus_speed_2500,
 221         e1000_bus_speed_5000,
 222         e1000_bus_speed_reserved
 223 };
 224
 225 enum e1000_bus_width {
 226         e1000_bus_width_unknown = 0,
 227         e1000_bus_width_pcie_x1,
 228         e1000_bus_width_pcie_x2,
 229         e1000_bus_width_pcie_x4 = 4,
 230         e1000_bus_width_pcie_x8 = 8,
 231         e1000_bus_width_32,
 232         e1000_bus_width_64,
 233         e1000_bus_width_reserved
 234 };
 235
 236 enum e1000_1000t_rx_status {
 237         e1000_1000t_rx_status_not_ok = 0,
 238         e1000_1000t_rx_status_ok,
 239         e1000_1000t_rx_status_undefined = 0xFF
 240 };
 241
 242 enum e1000_rev_polarity {
 243         e1000_rev_polarity_normal = 0,
 244         e1000_rev_polarity_reversed,
 245         e1000_rev_polarity_undefined = 0xFF
 246 };
 247
 248 enum e1000_fc_mode {
 249         e1000_fc_none = 0,
 250         e1000_fc_rx_pause,
 251         e1000_fc_tx_pause,
 252         e1000_fc_full,
 253         e1000_fc_default = 0xFF
 254 };
 255
 256 enum e1000_ffe_config {
 257         e1000_ffe_config_enabled = 0,
 258         e1000_ffe_config_active,
 259         e1000_ffe_config_blocked
 260 };
 261
 262 enum e1000_dsp_config {
 263         e1000_dsp_config_disabled = 0,
 264         e1000_dsp_config_enabled,
 265         e1000_dsp_config_activated,
 266         e1000_dsp_config_undefined = 0xFF
 267 };
 268
 269 enum e1000_ms_type {
 270         e1000_ms_hw_default = 0,
 271         e1000_ms_force_master,
 272         e1000_ms_force_slave,
 273         e1000_ms_auto
 274 };
 275
 276 enum e1000_smart_speed {
 277         e1000_smart_speed_default = 0,
 278         e1000_smart_speed_on,
 279         e1000_smart_speed_off
 280 };
 281
 282 /* Receive Descriptor */
 283 struct e1000_rx_desc {
 284         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 285         __le16 length;      /* Length of data DMAed into data buffer */
 286         __le16 csum;        /* Packet checksum */
 287         u8  status;         /* Descriptor status */
 288         u8  errors;         /* Descriptor Errors */
 289         __le16 special;
 290 };
 291
 292 /* Receive Descriptor - Extended */
 293 union e1000_rx_desc_extended {
 294         struct {
 295                 __le64 buffer_addr;
 296                 __le64 reserved;
 297         } read;
 298         struct {
 299                 struct {
 300                         __le32 mrq;           /* Multiple Rx Queues */
 301                         union {
 302                                 __le32 rss;         /* RSS Hash */
 303                                 struct {
 304                                         __le16 ip_id;  /* IP id */
 305                                         __le16 csum;   /* Packet Checksum */
 306                                 } csum_ip;
 307                         } hi_dword;
 308                 } lower;
 309                 struct {
 310                         __le32 status_error;  /* ext status/error */
 311                         __le16 length;
 312                         __le16 vlan;          /* VLAN tag */
 313                 } upper;
 314         } wb;  /* writeback */
 315 };
 316
 317 #define MAX_PS_BUFFERS 4
 318 /* Receive Descriptor - Packet Split */
 319 union e1000_rx_desc_packet_split {
 320         struct {
 321                 /* one buffer for protocol header(s), three data buffers */
 322                 __le64 buffer_addr[MAX_PS_BUFFERS];
 323         } read;
 324         struct {
 325                 struct {
 326                         __le32 mrq;           /* Multiple Rx Queues */
 327                         union {
 328                                 __le32 rss;           /* RSS Hash */
 329                                 struct {
 330                                         __le16 ip_id;    /* IP id */
 331                                         __le16 csum;     /* Packet Checksum */
 332                                 } csum_ip;
 333                         } hi_dword;
 334                 } lower;
 335                 struct {
 336                         __le32 status_error;  /* ext status/error */
 337                         __le16 length0;       /* length of buffer 0 */
 338                         __le16 vlan;          /* VLAN tag */
 339                 } middle;
 340                 struct {
 341                         __le16 header_status;
 342                         __le16 length[3];     /* length of buffers 1-3 */
 343                 } upper;
 344                 __le64 reserved;
 345         } wb; /* writeback */
 346 };
 347
 348 /* Transmit Descriptor */
 349 struct e1000_tx_desc {
 350         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 351         union {
 352                 __le32 data;
 353                 struct {
 354                         __le16 length;    /* Data buffer length */
 355                         u8 cso;           /* Checksum offset */
 356                         u8 cmd;           /* Descriptor control */
 357                 } flags;
 358         } lower;
 359         union {
 360                 __le32 data;
 361                 struct {
 362                         u8 status;        /* Descriptor status */
 363                         u8 css;           /* Checksum start */
 364                         __le16 special;
 365                 } fields;
 366         } upper;
 367 };
 368
 369 /* Offload Context Descriptor */
 370 struct e1000_context_desc {
 371         union {
 372                 __le32 ip_config;
 373                 struct {
 374                         u8 ipcss;         /* IP checksum start */
 375                         u8 ipcso;         /* IP checksum offset */
 376                         __le16 ipcse;     /* IP checksum end */
 377                 } ip_fields;
 378         } lower_setup;
 379         union {
 380                 __le32 tcp_config;
 381                 struct {
 382                         u8 tucss;         /* TCP checksum start */
 383                         u8 tucso;         /* TCP checksum offset */
 384                         __le16 tucse;     /* TCP checksum end */
 385                 } tcp_fields;
 386         } upper_setup;
 387         __le32 cmd_and_length;
 388         union {
 389                 __le32 data;
 390                 struct {
 391                         u8 status;        /* Descriptor status */
 392                         u8 hdr_len;       /* Header length */
 393                         __le16 mss;       /* Maximum segment size */
 394                 } fields;
 395         } tcp_seg_setup;
 396 };
 397
 398 /* Offload data descriptor */
 399 struct e1000_data_desc {
 400         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 401         union {
 402                 __le32 data;
 403                 struct {
 404                         __le16 length;    /* Data buffer length */
 405                         u8 typ_len_ext;
 406                         u8 cmd;
 407                 } flags;
 408         } lower;
 409         union {
 410                 __le32 data;
 411                 struct {
 412                         u8 status;        /* Descriptor status */
 413                         u8 popts;         /* Packet Options */
 414                         __le16 special;
 415                 } fields;
 416         } upper;
 417 };
 418
 419 /* Statistics counters collected by the MAC */
 420 struct e1000_hw_stats {
 421         u64 crcerrs;
 422         u64 algnerrc;
 423         u64 symerrs;
 424         u64 rxerrc;
 425         u64 mpc;
 426         u64 scc;
 427         u64 ecol;
 428         u64 mcc;
 429         u64 latecol;
 430         u64 colc;
 431         u64 dc;
 432         u64 tncrs;
 433         u64 sec;
 434         u64 cexterr;
 435         u64 rlec;
 436         u64 xonrxc;
 437         u64 xontxc;
 438         u64 xoffrxc;
 439         u64 xofftxc;
 440         u64 fcruc;
 441         u64 prc64;
 442         u64 prc127;
 443         u64 prc255;
 444         u64 prc511;
 445         u64 prc1023;
 446         u64 prc1522;
 447         u64 gprc;
 448         u64 bprc;
 449         u64 mprc;
 450         u64 gptc;
 451         u64 gorc;
 452         u64 gotc;
 453         u64 rnbc;
 454         u64 ruc;
 455         u64 rfc;
 456         u64 roc;
 457         u64 rjc;
 458         u64 mgprc;
 459         u64 mgpdc;
 460         u64 mgptc;
 461         u64 tor;
 462         u64 tot;
 463         u64 tpr;
 464         u64 tpt;
 465         u64 ptc64;
 466         u64 ptc127;
 467         u64 ptc255;
 468         u64 ptc511;
 469         u64 ptc1023;
 470         u64 ptc1522;
 471         u64 mptc;
 472         u64 bptc;
 473         u64 tsctc;
 474         u64 tsctfc;
 475         u64 iac;
 476         u64 icrxptc;
 477         u64 icrxatc;
 478         u64 ictxptc;
 479         u64 ictxatc;
 480         u64 ictxqec;
 481         u64 ictxqmtc;
 482         u64 icrxdmtc;
 483         u64 icrxoc;
 484         u64 cbtmpc;
 485         u64 htdpmc;
 486         u64 cbrdpc;
 487         u64 cbrmpc;
 488         u64 rpthc;
 489         u64 hgptc;
 490         u64 htcbdpc;
 491         u64 hgorc;
 492         u64 hgotc;
 493         u64 lenerrs;
 494         u64 scvpc;
 495         u64 hrmpc;
 496         u64 doosync;
 497 };
 498
 499 struct e1000_vf_stats {
 500         u64 base_gprc;
 501         u64 base_gptc;
 502         u64 base_gorc;
 503         u64 base_gotc;
 504         u64 base_mprc;
 505         u64 base_gotlbc;
 506         u64 base_gptlbc;
 507         u64 base_gorlbc;
 508         u64 base_gprlbc;
 509
 510         u32 last_gprc;
 511         u32 last_gptc;
 512         u32 last_gorc;
 513         u32 last_gotc;
 514         u32 last_mprc;
 515         u32 last_gotlbc;
 516         u32 last_gptlbc;
 517         u32 last_gorlbc;
 518         u32 last_gprlbc;
 519
 520         u64 gprc;
 521         u64 gptc;
 522         u64 gorc;
 523         u64 gotc;
 524         u64 mprc;
 525         u64 gotlbc;
 526         u64 gptlbc;
 527         u64 gorlbc;
 528         u64 gprlbc;
 529 };
 530
 531 struct e1000_phy_stats {
 532         u32 idle_errors;
 533         u32 receive_errors;
 534 };
 535
 536 struct e1000_host_mng_dhcp_cookie {
 537         u32 signature;
 538         u8  status;
 539         u8  reserved0;
 540         u16 vlan_id;
 541         u32 reserved1;
 542         u16 reserved2;
 543         u8  reserved3;
 544         u8  checksum;
 545 };
 546
 547 /* Host Interface "Rev 1" */
 548 struct e1000_host_command_header {
 549         u8 command_id;
 550         u8 command_length;
 551         u8 command_options;
 552         u8 checksum;
 553 };
 554
 555 #define E1000_HI_MAX_DATA_LENGTH     252
 556 struct e1000_host_command_info {
 557         struct e1000_host_command_header command_header;
 558         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 559 };
 560
 561 /* Host Interface "Rev 2" */
 562 struct e1000_host_mng_command_header {
 563         u8  command_id;
 564         u8  checksum;
 565         u16 reserved1;
 566         u16 reserved2;
 567         u16 command_length;
 568 };
 569
 570 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 571 struct e1000_host_mng_command_info {
 572         struct e1000_host_mng_command_header command_header;
 573         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 574 };
 575
 576 #include "e1000_mac.h"
 577 #include "e1000_phy.h"
 578 #include "e1000_nvm.h"
 579 #include "e1000_manage.h"
 580
 581 struct e1000_mac_operations {
 582         /* Function pointers for the MAC. */
 583         s32  (*init_params)(struct e1000_hw *);
 584         s32  (*blink_led)(struct e1000_hw *);
 585         s32  (*check_for_link)(struct e1000_hw *);
 586         bool (*check_mng_mode)(struct e1000_hw *hw);
 587         s32  (*cleanup_led)(struct e1000_hw *);
 588         void (*clear_hw_cntrs)(struct e1000_hw *);
 589         void (*clear_vfta)(struct e1000_hw *);
 590         s32  (*get_bus_info)(struct e1000_hw *);
 591         void (*set_lan_id)(struct e1000_hw *);
 592         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 593         s32  (*led_on)(struct e1000_hw *);
 594         s32  (*led_off)(struct e1000_hw *);
 595         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32);
 596         s32  (*reset_hw)(struct e1000_hw *);
 597         s32  (*init_hw)(struct e1000_hw *);
 598         void (*shutdown_serdes)(struct e1000_hw *);
 599         s32  (*setup_link)(struct e1000_hw *);
 600         s32  (*setup_physical_interface)(struct e1000_hw *);
 601         s32  (*setup_led)(struct e1000_hw *);
 602         void (*write_vfta)(struct e1000_hw *, u32, u32);
 603         void (*mta_set)(struct e1000_hw *, u32);
 604         void (*config_collision_dist)(struct e1000_hw *);
 605         void (*rar_set)(struct e1000_hw *, u8*, u32);
 606         s32  (*read_mac_addr)(struct e1000_hw *);
 607         s32  (*validate_mdi_setting)(struct e1000_hw *);
 608         s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
 609         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
 610                       struct e1000_host_mng_command_header*);
 611         s32  (*mng_enable_host_if)(struct e1000_hw *);
 612         s32  (*wait_autoneg)(struct e1000_hw *);
 613 };
 614
 615 struct e1000_phy_operations {
 616         s32  (*init_params)(struct e1000_hw *);
 617         s32  (*acquire)(struct e1000_hw *);
 618         s32  (*cfg_on_link_up)(struct e1000_hw *);
 619         s32  (*check_polarity)(struct e1000_hw *);
 620         s32  (*check_reset_block)(struct e1000_hw *);
 621         s32  (*commit)(struct e1000_hw *);
 622         s32  (*force_speed_duplex)(struct e1000_hw *);
 623         s32  (*get_cfg_done)(struct e1000_hw *hw);
 624         s32  (*get_cable_length)(struct e1000_hw *);
 625         s32  (*get_info)(struct e1000_hw *);
 626         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 627         void (*release)(struct e1000_hw *);
 628         s32  (*reset)(struct e1000_hw *);
 629         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 630         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 631         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 632         void (*power_up)(struct e1000_hw *);
 633         void (*power_down)(struct e1000_hw *);
 634 };
 635
 636 struct e1000_nvm_operations {
 637         s32  (*init_params)(struct e1000_hw *);
 638         s32  (*acquire)(struct e1000_hw *);
 639         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 640         void (*release)(struct e1000_hw *);
 641         void (*reload)(struct e1000_hw *);
 642         s32  (*update)(struct e1000_hw *);
 643         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 644         s32  (*validate)(struct e1000_hw *);
 645         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 646 };
 647
 648 struct e1000_mac_info {
 649         struct e1000_mac_operations ops;
 650         u8 addr[6];
 651         u8 perm_addr[6];
 652
 653         enum e1000_mac_type type;
 654
 655         u32 collision_delta;
 656         u32 ledctl_default;
 657         u32 ledctl_mode1;
 658         u32 ledctl_mode2;
 659         u32 mc_filter_type;
 660         u32 tx_packet_delta;
 661         u32 txcw;
 662
 663         u16 current_ifs_val;
 664         u16 ifs_max_val;
 665         u16 ifs_min_val;
 666         u16 ifs_ratio;
 667         u16 ifs_step_size;
 668         u16 mta_reg_count;
 669         u16 rar_entry_count;
 670
 671         u8  forced_speed_duplex;
 672
 673         bool adaptive_ifs;
 674         bool arc_subsystem_valid;
 675         bool asf_firmware_present;
 676         bool autoneg;
 677         bool autoneg_failed;
 678         bool get_link_status;
 679         bool in_ifs_mode;
 680         bool report_tx_early;
 681         bool serdes_has_link;
 682         bool tx_pkt_filtering;
 683 };
 684
 685 struct e1000_phy_info {
 686         struct e1000_phy_operations ops;
 687         enum e1000_phy_type type;
 688
 689         enum e1000_1000t_rx_status local_rx;
 690         enum e1000_1000t_rx_status remote_rx;
 691         enum e1000_ms_type ms_type;
 692         enum e1000_ms_type original_ms_type;
 693         enum e1000_rev_polarity cable_polarity;
 694         enum e1000_smart_speed smart_speed;
 695
 696         u32 addr;
 697         u32 id;
 698         u32 reset_delay_us; /* in usec */
 699         u32 revision;
 700
 701         enum e1000_media_type media_type;
 702
 703         u16 autoneg_advertised;
 704         u16 autoneg_mask;
 705         u16 cable_length;
 706         u16 max_cable_length;
 707         u16 min_cable_length;
 708
 709         u8 mdix;
 710
 711         bool disable_polarity_correction;
 712         bool is_mdix;
 713         bool polarity_correction;
 714         bool reset_disable;
 715         bool speed_downgraded;
 716         bool autoneg_wait_to_complete;
 717 };
 718
 719 struct e1000_nvm_info {
 720         struct e1000_nvm_operations ops;
 721         enum e1000_nvm_type type;
 722         enum e1000_nvm_override override;
 723
 724         u32 flash_bank_size;
 725         u32 flash_base_addr;
 726
 727         u16 word_size;
 728         u16 delay_usec;
 729         u16 address_bits;
 730         u16 opcode_bits;
 731         u16 page_size;
 732 };
 733
 734 struct e1000_bus_info {
 735         enum e1000_bus_type type;
 736         enum e1000_bus_speed speed;
 737         enum e1000_bus_width width;
 738
 739         u16 func;
 740         u16 pci_cmd_word;
 741 };
 742
 743 struct e1000_fc_info {
 744         u32 high_water;          /* Flow control high-water mark */
 745         u32 low_water;           /* Flow control low-water mark */
 746         u16 pause_time;          /* Flow control pause timer */
 747         bool send_xon;           /* Flow control send XON */
 748         bool strict_ieee;        /* Strict IEEE mode */
 749         enum e1000_fc_mode current_mode; /* FC mode in effect */
 750         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
 751 };
 752
 753 struct e1000_dev_spec_82541 {
 754         enum e1000_dsp_config dsp_config;
 755         enum e1000_ffe_config ffe_config;
 756         u16 spd_default;
 757         bool phy_init_script;
 758 };
 759
 760 struct e1000_dev_spec_82542 {
 761         bool dma_fairness;
 762 };
 763
 764 struct e1000_dev_spec_82543 {
 765         u32  tbi_compatibility;
 766         bool dma_fairness;
 767         bool init_phy_disabled;
 768 };
 769
 770 struct e1000_dev_spec_82571 {
 771         bool laa_is_present;
 772 };
 773
 774 struct e1000_shadow_ram {
 775         u16  value;
 776         bool modified;
 777 };
 778
 779 #define E1000_SHADOW_RAM_WORDS          2048
 780
 781 struct e1000_dev_spec_ich8lan {
 782         bool kmrn_lock_loss_workaround_enabled;
 783         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 784 };
 785
 786 struct e1000_dev_spec_82575 {
 787         bool sgmii_active;
 788 };
 789
 790 struct e1000_dev_spec_vf {
 791         u32     vf_number;
 792 };
 793
 794 struct e1000_hw {
 795         void *back;
 796
 797         u8 *hw_addr;
 798         u8 *flash_address;
 799         unsigned long io_base;
 800
 801         struct e1000_mac_info  mac;
 802         struct e1000_fc_info   fc;
 803         struct e1000_phy_info  phy;
 804         struct e1000_nvm_info  nvm;
 805         struct e1000_bus_info  bus;
 806         struct e1000_host_mng_dhcp_cookie mng_cookie;
 807
 808         union {
 809                 struct e1000_dev_spec_82541     _82541;
 810                 struct e1000_dev_spec_82542     _82542;
 811                 struct e1000_dev_spec_82543     _82543;
 812                 struct e1000_dev_spec_82571     _82571;
 813                 struct e1000_dev_spec_ich8lan   ich8lan;
 814                 struct e1000_dev_spec_82575     _82575;
 815                 struct e1000_dev_spec_vf        vf;
 816         } dev_spec;
 817
 818         u16 device_id;
 819         u16 subsystem_vendor_id;
 820         u16 subsystem_device_id;
 821         u16 vendor_id;
 822
 823         u8  revision_id;
 824 };
 825
 826 #include "e1000_82541.h"
 827 #include "e1000_82543.h"
 828 #include "e1000_82571.h"
 829 #include "e1000_80003es2lan.h"
 830 #include "e1000_ich8lan.h"
 831 #include "e1000_82575.h"
 832
 833 /* These functions must be implemented by drivers */
 834 void e1000_pci_clear_mwi(struct e1000_hw *hw);
 835 void e1000_pci_set_mwi(struct e1000_hw *hw);
 836 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 837 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 838 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 839
 840 #endif