1 /******************************************************************************
3 Copyright (c) 2001-2008, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
36 #ifndef _EM_H_DEFINED_
37 #define _EM_H_DEFINED_
42 * EM_TXD: Maximum number of Transmit Descriptors
43 * Valid Range: 80-256 for 82542 and 82543-based adapters
46 * This value is the number of transmit descriptors allocated by the driver.
47 * Increasing this value allows the driver to queue more transmits. Each
48 * descriptor is 16 bytes.
49 * Since TDLEN should be multiple of 128bytes, the number of transmit
50 * desscriptors should meet the following condition.
51 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
54 #define EM_MAX_TXD_82543 256
55 #define EM_MAX_TXD 4096
56 #define EM_DEFAULT_TXD EM_MAX_TXD_82543
59 * EM_RXD - Maximum number of receive Descriptors
60 * Valid Range: 80-256 for 82542 and 82543-based adapters
63 * This value is the number of receive descriptors allocated by the driver.
64 * Increasing this value allows the driver to buffer more incoming packets.
65 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
66 * descriptor. The maximum MTU size is 16110.
67 * Since TDLEN should be multiple of 128bytes, the number of transmit
68 * desscriptors should meet the following condition.
69 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
72 #define EM_MAX_RXD_82543 256
73 #define EM_MAX_RXD 4096
74 #define EM_DEFAULT_RXD EM_MAX_RXD_82543
77 * EM_TIDV - Transmit Interrupt Delay Value
78 * Valid Range: 0-65535 (0=off)
80 * This value delays the generation of transmit interrupts in units of
81 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
82 * efficiency if properly tuned for specific network traffic. If the
83 * system is reporting dropped transmits, this value may be set too high
84 * causing the driver to run out of available transmit descriptors.
89 * EM_TADV - Transmit Absolute Interrupt Delay Value
90 * (Not valid for 82542/82543/82544)
91 * Valid Range: 0-65535 (0=off)
93 * This value, in units of 1.024 microseconds, limits the delay in which a
94 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
95 * this value ensures that an interrupt is generated after the initial
96 * packet is sent on the wire within the set amount of time. Proper tuning,
97 * along with EM_TIDV, may improve traffic throughput in specific
103 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
104 * Valid Range: 0-65535 (0=off)
106 * This value delays the generation of receive interrupts in units of 1.024
107 * microseconds. Receive interrupt reduction can improve CPU efficiency if
108 * properly tuned for specific network traffic. Increasing this value adds
109 * extra latency to frame reception and can end up decreasing the throughput
110 * of TCP traffic. If the system is reporting dropped receives, this value
111 * may be set too high, causing the driver to run out of available receive
114 * CAUTION: When setting EM_RDTR to a value other than 0, adapters
115 * may hang (stop transmitting) under certain network conditions.
116 * If this occurs a WATCHDOG message is logged in the system
117 * event log. In addition, the controller is automatically reset,
118 * restoring the network connection. To eliminate the potential
119 * for the hang ensure that EM_RDTR is set to 0.
124 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
125 * Valid Range: 0-65535 (0=off)
127 * This value, in units of 1.024 microseconds, limits the delay in which a
128 * receive interrupt is generated. Useful only if EM_RDTR is non-zero,
129 * this value ensures that an interrupt is generated after the initial
130 * packet is received within the set amount of time. Proper tuning,
131 * along with EM_RDTR, may improve traffic throughput in specific network
137 * This parameter controls the duration of transmit watchdog timer.
139 #define EM_TX_TIMEOUT 5
142 * This parameter controls when the driver calls the routine to reclaim
143 * transmit descriptors.
145 #define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
146 #define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
149 * This parameter controls whether or not autonegotation is enabled.
150 * 0 - Disable autonegotiation
151 * 1 - Enable autonegotiation
153 #define DO_AUTO_NEG 1
156 * This parameter control whether or not the driver will wait for
157 * autonegotiation to complete.
158 * 1 - Wait for autonegotiation to complete
159 * 0 - Don't wait for autonegotiation to complete
161 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
163 /* Tunables -- End */
165 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
166 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
169 #define AUTO_ALL_MODES 0
171 /* PHY master/slave setting */
172 #define EM_MASTER_SLAVE e1000_ms_hw_default
175 * Micellaneous constants
177 #define EM_VENDOR_ID 0x8086
178 #define EM_FLASH 0x0014
180 #define EM_JUMBO_PBA 0x00000028
181 #define EM_DEFAULT_PBA 0x00000030
182 #define EM_SMARTSPEED_DOWNSHIFT 3
183 #define EM_SMARTSPEED_MAX 15
184 #define EM_MAX_INTR 10
186 #define MAX_NUM_MULTICAST_ADDRESSES 128
187 #define PCI_ANY_ID (~0U)
188 #define ETHER_ALIGN 2
189 #define EM_FC_PAUSE_TIME 0x0680
190 #define EM_EEPROM_APME 0x400;
192 /* Code compatilbility between 6 and 7 */
193 #ifndef ETHER_BPF_MTAP
194 #define ETHER_BPF_MTAP BPF_MTAP
198 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
199 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
200 * also optimize cache line size effect. H/W supports up to cache line size 128.
202 #define EM_DBA_ALIGN 128
204 #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
206 /* PCI Config defines */
207 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
208 #define EM_BAR_TYPE_MASK 0x00000001
209 #define EM_BAR_TYPE_MMEM 0x00000000
210 #define EM_BAR_TYPE_IO 0x00000001
211 #define EM_BAR_TYPE_FLASH 0x0014
212 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
213 #define EM_BAR_MEM_TYPE_MASK 0x00000006
214 #define EM_BAR_MEM_TYPE_32BIT 0x00000000
215 #define EM_BAR_MEM_TYPE_64BIT 0x00000004
216 #define EM_MSIX_BAR 3 /* On 82575 */
218 /* Defines for printing debug information */
220 #define DEBUG_IOCTL 0
223 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
224 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
225 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
226 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
227 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
228 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
229 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
230 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
231 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
233 #define EM_MAX_SCATTER 64
234 #define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
235 #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
236 #define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
238 #define ETH_ADDR_LEN 6
239 #define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
242 * 82574 has a nonstandard address for EIAC
243 * and since its only used in MSIX, and in
244 * the em driver only 82574 uses MSIX we can
245 * solve it just using this define.
247 #define EM_EIAC 0x000DC
249 /* Used in for 82547 10Mb Half workaround */
250 #define EM_PBA_BYTES_SHIFT 0xA
251 #define EM_TX_HEAD_ADDR_SHIFT 7
252 #define EM_PBA_TX_MASK 0xFFFF0000
253 #define EM_FIFO_HDR 0x10
254 #define EM_82547_PKT_THRESH 0x3e0
257 /* Precision Time Sync (IEEE 1588) defines */
258 #define ETHERTYPE_IEEE1588 0x88F7
259 #define PICOSECS_PER_TICK 20833
260 #define TSYNC_PORT 319 /* UDP port for the protocol */
262 /* TIMESYNC IOCTL defines */
263 #define EM_TIMESYNC_READTS _IOWR('i', 127, struct em_tsync_read)
265 /* Used in the READTS IOCTL */
266 struct em_tsync_read {
267 int read_current_time;
268 struct timespec system_time;
273 unsigned char srcid[6];
278 #endif /* EM_TIMESYNC */
282 struct em_int_delay_info {
283 struct adapter *adapter; /* Back-pointer to the adapter struct */
284 int offset; /* Register offset to read/write */
285 int value; /* Current value in usecs */
289 * Bus dma allocation structure used by
290 * e1000_dma_malloc and e1000_dma_free.
292 struct em_dma_alloc {
293 bus_addr_t dma_paddr;
295 bus_dma_tag_t dma_tag;
296 bus_dmamap_t dma_map;
297 bus_dma_segment_t dma_seg;
301 /* Our adapter structure */
306 /* FreeBSD operating-system-specific structures. */
307 struct e1000_osdep osdep;
310 struct resource *memory;
311 struct resource *flash;
312 struct resource *msix;
314 struct resource *ioport;
317 /* 82574 uses 3 int vectors */
318 struct resource *res[3];
322 struct ifmedia media;
323 struct callout timer;
324 struct callout tx_fifo_timer;
333 int em_insert_vlan_header;
335 /* Task for FAST handling */
336 struct task link_task;
337 struct task rxtx_task;
340 struct taskqueue *tq; /* private task queue */
342 #ifdef EM_HW_VLAN_SUPPORT
343 eventhandler_tag vlan_attach;
344 eventhandler_tag vlan_detach;
347 /* Management and WOL features */
351 /* Info about the board itself */
354 uint16_t link_duplex;
356 struct em_int_delay_info tx_int_delay;
357 struct em_int_delay_info tx_abs_int_delay;
358 struct em_int_delay_info rx_int_delay;
359 struct em_int_delay_info rx_abs_int_delay;
362 * Transmit definitions
364 * We have an array of num_tx_desc descriptors (handled
365 * by the controller) paired with an array of tx_buffers
366 * (at tx_buffer_area).
367 * The index of the next available descriptor is next_avail_tx_desc.
368 * The number of remaining tx_desc is num_tx_desc_avail.
370 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
371 struct e1000_tx_desc *tx_desc_base;
372 uint32_t next_avail_tx_desc;
373 uint32_t next_tx_to_clean;
374 volatile uint16_t num_tx_desc_avail;
375 uint16_t num_tx_desc;
377 struct em_buffer *tx_buffer_area;
378 bus_dma_tag_t txtag; /* dma tag for tx */
379 uint32_t tx_tso; /* last tx was tso */
382 * Receive definitions
384 * we have an array of num_rx_desc rx_desc (handled by the
385 * controller), and paired with an array of rx_buffers
386 * (at rx_buffer_area).
387 * The next pair to check on receive is at offset next_rx_desc_to_check
389 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
390 struct e1000_rx_desc *rx_desc_base;
391 uint32_t next_rx_desc_to_check;
392 uint32_t rx_buffer_len;
393 uint16_t num_rx_desc;
394 int rx_process_limit;
395 struct em_buffer *rx_buffer_area;
397 bus_dmamap_t rx_sparemap;
400 * First/last mbuf pointers, for
401 * collecting multisegment RX packets.
406 /* Misc stats maintained by the driver */
407 unsigned long dropped_pkts;
408 unsigned long mbuf_alloc_failed;
409 unsigned long mbuf_cluster_failed;
410 unsigned long no_tx_desc_avail1;
411 unsigned long no_tx_desc_avail2;
412 unsigned long no_tx_map_avail;
413 unsigned long no_tx_dma_setup;
414 unsigned long watchdog_events;
415 unsigned long rx_overruns;
416 unsigned long rx_irq;
417 unsigned long tx_irq;
418 unsigned long link_irq;
420 /* 82547 workaround */
421 uint32_t tx_fifo_size;
422 uint32_t tx_fifo_head;
423 uint32_t tx_fifo_head_addr;
424 uint64_t tx_fifo_reset_cnt;
425 uint64_t tx_fifo_wrk_cnt;
426 uint32_t tx_head_addr;
428 /* For 82544 PCIX Workaround */
429 boolean_t pcix_82544;
438 struct e1000_hw_stats stats;
441 /* ******************************************************************************
444 * This array contains the list of Subvendor/Subdevice IDs on which the driver
447 * ******************************************************************************/
448 typedef struct _em_vendor_info_t {
449 unsigned int vendor_id;
450 unsigned int device_id;
451 unsigned int subvendor_id;
452 unsigned int subdevice_id;
458 int next_eop; /* Index of the desc to watch */
460 bus_dmamap_t map; /* bus_dma map for packet */
463 /* For 82544 PCIX Workaround */
464 typedef struct _ADDRESS_LENGTH_PAIR
468 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
470 typedef struct _DESCRIPTOR_PAIR
472 ADDRESS_LENGTH_PAIR descriptor[4];
474 } DESC_ARRAY, *PDESC_ARRAY;
476 #define EM_CORE_LOCK_INIT(_sc, _name) \
477 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF)
478 #define EM_TX_LOCK_INIT(_sc, _name) \
479 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF)
480 #define EM_RX_LOCK_INIT(_sc, _name) \
481 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF)
482 #define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
483 #define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
484 #define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
485 #define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
486 #define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
487 #define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
488 #define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
489 #define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
490 #define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
491 #define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
492 #define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
494 #endif /* _EM_H_DEFINED_ */