1 /******************************************************************************
3 Copyright (c) 2001-2008, Intel Corporation
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32 ******************************************************************************/
35 #ifndef _IGB_H_DEFINED_
36 #define _IGB_H_DEFINED_
41 * IGB_TXD: Maximum number of Transmit Descriptors
43 * This value is the number of transmit descriptors allocated by the driver.
44 * Increasing this value allows the driver to queue more transmits. Each
45 * descriptor is 16 bytes.
46 * Since TDLEN should be multiple of 128bytes, the number of transmit
47 * desscriptors should meet the following condition.
48 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
50 #define IGB_MIN_TXD 80
51 #define IGB_DEFAULT_TXD 256
52 #define IGB_MAX_TXD 4096
55 * IGB_RXD: Maximum number of Transmit Descriptors
57 * This value is the number of receive descriptors allocated by the driver.
58 * Increasing this value allows the driver to buffer more incoming packets.
59 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
60 * descriptor. The maximum MTU size is 16110.
61 * Since TDLEN should be multiple of 128bytes, the number of transmit
62 * desscriptors should meet the following condition.
63 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
65 #define IGB_MIN_RXD 80
66 #define IGB_DEFAULT_RXD 256
67 #define IGB_MAX_RXD 4096
70 * IGB_TIDV - Transmit Interrupt Delay Value
71 * Valid Range: 0-65535 (0=off)
73 * This value delays the generation of transmit interrupts in units of
74 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
75 * efficiency if properly tuned for specific network traffic. If the
76 * system is reporting dropped transmits, this value may be set too high
77 * causing the driver to run out of available transmit descriptors.
82 * IGB_TADV - Transmit Absolute Interrupt Delay Value
83 * Valid Range: 0-65535 (0=off)
85 * This value, in units of 1.024 microseconds, limits the delay in which a
86 * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero,
87 * this value ensures that an interrupt is generated after the initial
88 * packet is sent on the wire within the set amount of time. Proper tuning,
89 * along with IGB_TIDV, may improve traffic throughput in specific
95 * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer)
96 * Valid Range: 0-65535 (0=off)
98 * This value delays the generation of receive interrupts in units of 1.024
99 * microseconds. Receive interrupt reduction can improve CPU efficiency if
100 * properly tuned for specific network traffic. Increasing this value adds
101 * extra latency to frame reception and can end up decreasing the throughput
102 * of TCP traffic. If the system is reporting dropped receives, this value
103 * may be set too high, causing the driver to run out of available receive
106 * CAUTION: When setting IGB_RDTR to a value other than 0, adapters
107 * may hang (stop transmitting) under certain network conditions.
108 * If this occurs a WATCHDOG message is logged in the system
109 * event log. In addition, the controller is automatically reset,
110 * restoring the network connection. To eliminate the potential
111 * for the hang ensure that IGB_RDTR is set to 0.
116 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
117 * Valid Range: 0-65535 (0=off)
119 * This value, in units of 1.024 microseconds, limits the delay in which a
120 * receive interrupt is generated. Useful only if IGB_RDTR is non-zero,
121 * this value ensures that an interrupt is generated after the initial
122 * packet is received within the set amount of time. Proper tuning,
123 * along with IGB_RDTR, may improve traffic throughput in specific network
129 * This parameter controls the duration of transmit watchdog timer.
131 #define IGB_TX_TIMEOUT 5 /* set to 5 seconds */
134 * This parameter controls when the driver calls the routine to reclaim
135 * transmit descriptors.
137 #define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
138 #define IGB_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
141 * This parameter controls whether or not autonegotation is enabled.
142 * 0 - Disable autonegotiation
143 * 1 - Enable autonegotiation
145 #define DO_AUTO_NEG 1
148 * This parameter control whether or not the driver will wait for
149 * autonegotiation to complete.
150 * 1 - Wait for autonegotiation to complete
151 * 0 - Don't wait for autonegotiation to complete
153 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
155 /* Tunables -- End */
157 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
158 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
161 #define AUTO_ALL_MODES 0
163 /* PHY master/slave setting */
164 #define IGB_MASTER_SLAVE e1000_ms_hw_default
167 * Micellaneous constants
169 #define IGB_VENDOR_ID 0x8086
171 #define IGB_JUMBO_PBA 0x00000028
172 #define IGB_DEFAULT_PBA 0x00000030
173 #define IGB_SMARTSPEED_DOWNSHIFT 3
174 #define IGB_SMARTSPEED_MAX 15
175 #define IGB_MAX_INTR 10
176 #define IGB_RX_PTHRESH 16
177 #define IGB_RX_HTHRESH 8
178 #define IGB_RX_WTHRESH 1
180 #define MAX_NUM_MULTICAST_ADDRESSES 128
181 #define PCI_ANY_ID (~0U)
182 #define ETHER_ALIGN 2
183 #define IGB_TX_BUFFER_SIZE ((uint32_t) 1514)
184 #define IGB_FC_PAUSE_TIME 0x0680
185 #define IGB_EEPROM_APME 0x400;
187 #define MAX_INTS_PER_SEC 8000
188 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
190 /* Code compatilbility between 6 and 7 */
191 #ifndef ETHER_BPF_MTAP
192 #define ETHER_BPF_MTAP BPF_MTAP
196 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
197 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
198 * also optimize cache line size effect. H/W supports up to cache line size 128.
200 #define IGB_DBA_ALIGN 128
202 #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
204 /* PCI Config defines */
205 #define IGB_MSIX_BAR 3
208 ** This is the total number of MSIX vectors you wish
209 ** to use, it also controls the size of resources.
210 ** The 82575 has a total of 10, 82576 has 25. Set this
211 ** to the real amount you need to streamline data storage.
213 #define IGB_MSIX_VEC 6 /* MSIX vectors configured */
215 /* Defines for printing debug information */
217 #define DEBUG_IOCTL 0
220 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
221 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
222 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
223 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
224 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
225 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
226 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
227 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
228 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
230 #define IGB_MAX_SCATTER 64
231 #define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
232 #define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */
234 #define ETH_ADDR_LEN 6
235 #define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
238 * Interrupt Moderation parameters
240 #define IGB_LOW_LATENCY 128
241 #define IGB_AVE_LATENCY 450
242 #define IGB_BULK_LATENCY 1200
243 #define IGB_LINK_ITR 2000
246 /* Precision Time Sync (IEEE 1588) defines */
247 #define ETHERTYPE_IEEE1588 0x88F7
248 #define PICOSECS_PER_TICK 20833
249 #define TSYNC_PORT 319 /* UDP port for the protocol */
251 /* TIMESYNC IOCTL defines */
252 #define IGB_TIMESYNC_READTS _IOWR('i', 127, struct igb_tsync_read)
253 #define IGB_TIMESTAMP 5 /* A unique return value */
255 /* Used in the READTS IOCTL */
256 struct igb_tsync_read {
257 int read_current_time;
258 struct timespec system_time;
263 unsigned char srcid[6];
268 #endif /* IGB_TIMESYNC */
270 struct adapter; /* forward reference */
272 struct igb_int_delay_info {
273 struct adapter *adapter; /* Back-pointer to the adapter struct */
274 int offset; /* Register offset to read/write */
275 int value; /* Current value in usecs */
279 * Bus dma allocation structure used by
280 * e1000_dma_malloc and e1000_dma_free.
282 struct igb_dma_alloc {
283 bus_addr_t dma_paddr;
285 bus_dma_tag_t dma_tag;
286 bus_dmamap_t dma_map;
287 bus_dma_segment_t dma_seg;
293 * Transmit ring: one per tx queue
296 struct adapter *adapter;
298 u32 msix; /* This ring's MSIX vector */
299 u32 eims; /* This ring's EIMS bit */
302 struct igb_dma_alloc txdma; /* bus_dma glue for tx desc */
303 struct e1000_tx_desc *tx_base;
304 struct task tx_task; /* cleanup tasklet */
307 volatile u16 tx_avail;
308 struct igb_buffer *tx_buffers;
309 bus_dma_tag_t txtag; /* dma tag for tx */
317 * Receive ring: one per rx queue
320 struct adapter *adapter;
322 u32 msix; /* This ring's MSIX vector */
323 u32 eims; /* This ring's EIMS bit */
324 struct igb_dma_alloc rxdma; /* bus_dma glue for tx desc */
325 union e1000_adv_rx_desc *rx_base;
327 struct task rx_task; /* cleanup tasklet */
332 struct igb_buffer *rx_buffers;
333 bus_dma_tag_t rxtag; /* dma tag for tx */
334 bus_dmamap_t rx_spare_map;
336 * First/last mbuf pointers, for
337 * collecting multisegment RX packets.
355 /* FreeBSD operating-system-specific structures. */
356 struct e1000_osdep osdep;
359 struct resource *pci_mem;
360 struct resource *msix_mem;
361 struct resource *res[IGB_MSIX_VEC];
362 void *tag[IGB_MSIX_VEC];
363 int rid[IGB_MSIX_VEC];
370 struct ifmedia media;
371 struct callout timer;
372 int msix; /* total vectors allocated */
377 int igb_insert_vlan_header;
378 struct task link_task;
379 struct task rxtx_task;
380 struct taskqueue *tq; /* private task queue */
382 #ifdef IGB_HW_VLAN_SUPPORT
383 eventhandler_tag vlan_attach;
384 eventhandler_tag vlan_detach;
387 /* Management and WOL features */
391 /* Info about the board itself */
400 struct tx_ring *tx_rings;
408 struct rx_ring *rx_rings;
411 int rx_process_limit;
414 /* Misc stats maintained by the driver */
415 unsigned long dropped_pkts;
416 unsigned long mbuf_alloc_failed;
417 unsigned long mbuf_cluster_failed;
418 unsigned long no_tx_map_avail;
419 unsigned long no_tx_dma_setup;
420 unsigned long watchdog_events;
421 unsigned long rx_overruns;
431 struct e1000_hw_stats stats;
434 /* ******************************************************************************
437 * This array contains the list of Subvendor/Subdevice IDs on which the driver
440 * ******************************************************************************/
441 typedef struct _igb_vendor_info_t {
442 unsigned int vendor_id;
443 unsigned int device_id;
444 unsigned int subvendor_id;
445 unsigned int subdevice_id;
451 int next_eop; /* Index of the desc to watch */
453 bus_dmamap_t map; /* bus_dma map for packet */
456 #define IGB_CORE_LOCK_INIT(_sc, _name) \
457 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF)
458 #define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
459 #define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
460 #define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
461 #define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
462 #define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
463 #define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
464 #define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
465 #define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
466 #define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
467 #define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
468 #define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
470 #endif /* _IGB_H_DEFINED_ */