2 * Copyright (c) 1994 Herb Peyerl <hpeyerl@novatel.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Herb Peyerl.
16 * 4. The name of Herb Peyerl may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * Modified from the FreeBSD 1.1.5.1 version by:
37 * INRIA - Sophia Antipolis, France
38 * avega@sophia.inria.fr
42 * Promiscuous mode added and interrupt logic slightly changed
43 * to reduce the number of adapter failures. Transceiver select
44 * logic changed to use value from EEPROM. Autoconfiguration
48 * Chelindbank (Chelyabinsk, Russia)
49 * babkin@hq.icb.chel.su
53 * Pccard support for 3C589 by:
59 * MAINTAINER: Matthew N. Dodd <winter@jurai.net>
63 #include <sys/param.h>
64 #include <sys/systm.h>
66 #include <sys/socket.h>
67 #include <sys/sockio.h>
70 #include <machine/bus.h>
71 #include <machine/resource.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/ethernet.h>
81 #include <dev/ep/if_epreg.h>
82 #include <dev/ep/if_epvar.h>
84 /* Exported variables */
85 devclass_t ep_devclass;
87 static int ep_media2if_media[] =
88 {IFM_10_T, IFM_10_5, IFM_NONE, IFM_10_2, IFM_NONE};
91 static void epinit(void *);
92 static int epioctl(struct ifnet *, u_long, caddr_t);
93 static void epstart(struct ifnet *);
94 static void epwatchdog(struct ifnet *);
96 static void epstart_locked(struct ifnet *);
97 static void epinit_locked(struct ep_softc *);
99 /* if_media functions */
100 static int ep_ifmedia_upd(struct ifnet *);
101 static void ep_ifmedia_sts(struct ifnet *, struct ifmediareq *);
103 static void epstop(struct ep_softc *);
104 static void epread(struct ep_softc *);
105 static int eeprom_rdy(struct ep_softc *);
107 #define EP_FTST(sc, f) (sc->stat & (f))
108 #define EP_FSET(sc, f) (sc->stat |= (f))
109 #define EP_FRST(sc, f) (sc->stat &= ~(f))
112 eeprom_rdy(struct ep_softc *sc)
116 for (i = 0; is_eeprom_busy(sc) && i < MAX_EEPROMBUSY; i++)
119 if (i >= MAX_EEPROMBUSY) {
120 device_printf(sc->dev, "eeprom failed to come ready.\n");
128 * get_e: gets a 16 bits word from the EEPROM. we must have set the window
132 ep_get_e(struct ep_softc *sc, uint16_t offset, uint16_t *result)
138 CSR_WRITE_2(sc, EP_W0_EEPROM_COMMAND,
139 (EEPROM_CMD_RD << sc->epb.cmd_off) | offset);
144 (*result) = CSR_READ_2(sc, EP_W0_EEPROM_DATA);
150 ep_get_macaddr(struct ep_softc *sc, u_char *addr)
157 macaddr = (uint16_t *) addr;
160 for (i = EEPROM_NODE_ADDR_0; i <= EEPROM_NODE_ADDR_2; i++) {
161 error = ep_get_e(sc, i, &result);
164 macaddr[i] = htons(result);
170 ep_alloc(device_t dev)
172 struct ep_softc *sc = device_get_softc(dev);
178 sc->iobase = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
181 device_printf(dev, "No I/O space?!\n");
186 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
188 device_printf(dev, "No irq?!\n");
193 sc->stat = 0; /* 16 bit access */
195 sc->bst = rman_get_bustag(sc->iobase);
196 sc->bsh = rman_get_bushandle(sc->iobase);
198 sc->ep_connectors = 0;
199 sc->ep_connector = 0;
203 error = ep_get_e(sc, EEPROM_PROD_ID, &result);
206 sc->epb.prod_id = result;
208 error = ep_get_e(sc, EEPROM_RESOURCE_CFG, &result);
211 sc->epb.res_cfg = result;
220 ep_get_media(struct ep_softc *sc)
225 config = CSR_READ_2(sc, EP_W0_CONFIG_CTRL);
227 sc->ep_connectors |= AUI;
229 sc->ep_connectors |= BNC;
231 sc->ep_connectors |= UTP;
233 if (!(sc->ep_connectors & 7))
235 device_printf(sc->dev, "no connectors!\n");
238 * This works for most of the cards so we'll do it here.
239 * The cards that require something different can override
242 sc->ep_connector = CSR_READ_2(sc, EP_W0_ADDRESS_CFG) >> ACF_CONNECTOR_BITS;
246 ep_free(device_t dev)
248 struct ep_softc *sc = device_get_softc(dev);
251 bus_teardown_intr(dev, sc->irq, sc->ep_intrhand);
253 bus_release_resource(dev, SYS_RES_IOPORT, 0, sc->iobase);
255 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
262 ep_setup_station(struct ep_softc *sc, u_char *enaddr)
267 * Setup the station address
270 for (i = 0; i < ETHER_ADDR_LEN; i++)
271 CSR_WRITE_1(sc, EP_W2_ADDR_0 + i, enaddr[i]);
275 ep_attach(struct ep_softc *sc)
277 struct ifnet *ifp = NULL;
278 struct ifmedia *ifm = NULL;
283 if (! (sc->stat & F_ENADDR_SKIP)) {
284 error = ep_get_macaddr(sc, sc->eaddr);
286 device_printf(sc->dev, "Unable to get MAC address!\n");
291 ep_setup_station(sc, sc->eaddr);
292 ifp = sc->ifp = if_alloc(IFT_ETHER);
294 device_printf(sc->dev, "if_alloc() failed\n");
300 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
301 ifp->if_mtu = ETHERMTU;
302 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
303 ifp->if_start = epstart;
304 ifp->if_ioctl = epioctl;
305 ifp->if_watchdog = epwatchdog;
306 ifp->if_init = epinit;
307 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
308 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
309 IFQ_SET_READY(&ifp->if_snd);
311 if (!sc->epb.mii_trans) {
312 ifmedia_init(&sc->ifmedia, 0, ep_ifmedia_upd, ep_ifmedia_sts);
314 if (sc->ep_connectors & AUI)
315 ifmedia_add(&sc->ifmedia,
316 IFM_ETHER | IFM_10_5, 0, NULL);
317 if (sc->ep_connectors & UTP)
318 ifmedia_add(&sc->ifmedia,
319 IFM_ETHER | IFM_10_T, 0, NULL);
320 if (sc->ep_connectors & BNC)
321 ifmedia_add(&sc->ifmedia,
322 IFM_ETHER | IFM_10_2, 0, NULL);
323 if (!sc->ep_connectors)
324 ifmedia_add(&sc->ifmedia,
325 IFM_ETHER | IFM_NONE, 0, NULL);
327 ifmedia_set(&sc->ifmedia,
328 IFM_ETHER | ep_media2if_media[sc->ep_connector]);
331 ifm->ifm_media = ifm->ifm_cur->ifm_media;
334 ether_ifattach(ifp, sc->eaddr);
336 #ifdef EP_LOCAL_STATS
337 sc->rx_no_first = sc->rx_no_mbuf = sc->rx_bpf_disc =
338 sc->rx_overrunf = sc->rx_overrunl = sc->tx_underrun = 0;
340 EP_FSET(sc, F_RX_FIRST);
341 sc->top = sc->mcur = 0;
349 ep_detach(device_t dev)
354 sc = device_get_softc(dev);
356 EP_ASSERT_UNLOCKED(sc);
358 if (bus_child_present(dev))
361 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
375 struct ep_softc *sc = xsc;
382 * The order in here seems important. Otherwise we may not receive
386 epinit_locked(struct ep_softc *sc)
388 struct ifnet *ifp = sc->ifp;
394 EP_ASSERT_LOCKED(sc);
398 CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
400 CSR_WRITE_2(sc, EP_W4_MEDIA_TYPE, DISABLE_UTP);
403 /* Disable the card */
404 CSR_WRITE_2(sc, EP_W0_CONFIG_CTRL, 0);
406 /* Enable the card */
407 CSR_WRITE_2(sc, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);
410 /* Reload the ether_addr. */
411 ep_setup_station(sc, IF_LLADDR(sc->ifp));
413 CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);
414 CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
417 /* Window 1 is operating window */
419 for (i = 0; i < 31; i++)
420 CSR_READ_1(sc, EP_W1_TX_STATUS);
422 /* get rid of stray intr's */
423 CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | 0xff);
425 CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK | S_5_INTS);
426 CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK | S_5_INTS);
428 if (ifp->if_flags & IFF_PROMISC)
429 CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |
430 FIL_MULTICAST | FIL_BRDCST | FIL_PROMISC);
432 CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |
433 FIL_MULTICAST | FIL_BRDCST);
435 if (!sc->epb.mii_trans)
438 CSR_WRITE_2(sc, EP_COMMAND, RX_ENABLE);
439 CSR_WRITE_2(sc, EP_COMMAND, TX_ENABLE);
441 ifp->if_drv_flags |= IFF_DRV_RUNNING;
442 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; /* just in case */
444 #ifdef EP_LOCAL_STATS
445 sc->rx_no_first = sc->rx_no_mbuf =
446 sc->rx_overrunf = sc->rx_overrunl = sc->tx_underrun = 0;
448 EP_FSET(sc, F_RX_FIRST);
451 sc->top = sc->mcur = 0;
453 CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
454 CSR_WRITE_2(sc, EP_COMMAND, SET_TX_START_THRESH | 16);
461 epstart(struct ifnet *ifp)
471 epstart_locked(struct ifnet *ifp)
481 EP_ASSERT_LOCKED(sc);
483 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
486 /* Sneak a peek at the next packet */
487 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
490 for (len = 0, m = m0; m != NULL; m = m->m_next)
496 * The 3c509 automatically pads short packets to minimum
497 * ethernet length, but we drop packets that are too large.
498 * Perhaps we should truncate them instead?
500 if (len + pad > ETHER_MAX_LEN) {
501 /* packet is obviously too large: toss it */
506 if (CSR_READ_2(sc, EP_W1_FREE_TX) < len + pad + 4) {
507 /* no room in FIFO */
508 CSR_WRITE_2(sc, EP_COMMAND, SET_TX_AVAIL_THRESH | (len + pad + 4));
510 if (CSR_READ_2(sc, EP_W1_FREE_TX) < len + pad + 4) {
511 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
512 IFQ_DRV_PREPEND(&ifp->if_snd, m0);
516 CSR_WRITE_2(sc, EP_COMMAND,
517 SET_TX_AVAIL_THRESH | EP_THRESH_DISABLE);
519 /* XXX 4.x and earlier would splhigh here */
521 CSR_WRITE_2(sc, EP_W1_TX_PIO_WR_1, len);
522 /* Second dword meaningless */
523 CSR_WRITE_2(sc, EP_W1_TX_PIO_WR_1, 0x0);
525 if (EP_FTST(sc, F_ACCESS_32_BITS)) {
526 for (m = m0; m != NULL; m = m->m_next) {
528 CSR_WRITE_MULTI_4(sc, EP_W1_TX_PIO_WR_1,
529 mtod(m, uint32_t *), m->m_len / 4);
531 CSR_WRITE_MULTI_1(sc, EP_W1_TX_PIO_WR_1,
532 mtod(m, uint8_t *)+(m->m_len & (~3)),
536 for (m = m0; m != NULL; m = m->m_next) {
538 CSR_WRITE_MULTI_2(sc, EP_W1_TX_PIO_WR_1,
539 mtod(m, uint16_t *), m->m_len / 2);
541 CSR_WRITE_1(sc, EP_W1_TX_PIO_WR_1,
542 *(mtod(m, uint8_t *)+m->m_len - 1));
547 CSR_WRITE_1(sc, EP_W1_TX_PIO_WR_1, 0); /* Padding */
549 /* XXX and drop splhigh here */
558 * Is another packet coming in? We don't want to overflow
562 if (CSR_READ_2(sc, EP_W1_RX_STATUS) & RX_BYTES_MASK) {
564 * we check if we have packets left, in that case
565 * we prepare to come back later
567 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
568 CSR_WRITE_2(sc, EP_COMMAND, SET_TX_AVAIL_THRESH | 8);
583 sc = (struct ep_softc *) arg;
585 /* XXX 4.x splbio'd here to reduce interruptability */
588 * quick fix: Try to detect an interrupt when the card goes away.
590 if (sc->gone || CSR_READ_2(sc, EP_STATUS) == 0xffff) {
596 CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK); /* disable all Ints */
600 while ((status = CSR_READ_2(sc, EP_STATUS)) & S_5_INTS) {
602 /* first acknowledge all interrupt sources */
603 CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | (status & S_MASK));
605 if (status & (S_RX_COMPLETE | S_RX_EARLY))
607 if (status & S_TX_AVAIL) {
610 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
612 CSR_READ_2(sc, EP_W1_FREE_TX);
615 if (status & S_CARD_FAILURE) {
617 #ifdef EP_LOCAL_STATS
618 device_printf(sc->dev, "\n\tStatus: %x\n", status);
620 printf("\tFIFO Diagnostic: %x\n",
621 CSR_READ_2(sc, EP_W4_FIFO_DIAG));
622 printf("\tStat: %x\n", sc->stat);
623 printf("\tIpackets=%d, Opackets=%d\n",
624 ifp->if_ipackets, ifp->if_opackets);
625 printf("\tNOF=%d, NOMB=%d, RXOF=%d, RXOL=%d, TXU=%d\n",
626 sc->rx_no_first, sc->rx_no_mbuf, sc->rx_overrunf,
627 sc->rx_overrunl, sc->tx_underrun);
631 device_printf(sc->dev,
632 "Status: %x (input buffer overflow)\n", status);
642 if (status & S_TX_COMPLETE) {
645 * We need ACK. We do it at the end.
647 * We need to read TX_STATUS until we get a
648 * 0 status in order to turn off the interrupt flag.
650 while ((status = CSR_READ_1(sc, EP_W1_TX_STATUS)) &
652 if (status & TXS_SUCCES_INTR_REQ)
655 (TXS_UNDERRUN | TXS_JABBER |
656 TXS_MAX_COLLISION)) {
657 CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
658 if (status & TXS_UNDERRUN) {
659 #ifdef EP_LOCAL_STATS
663 if (status & TXS_JABBER);
665 ++ifp->if_collisions;
672 CSR_WRITE_2(sc, EP_COMMAND, TX_ENABLE);
674 * To have a tx_avail_int but giving
675 * the chance to the Reception
677 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
678 CSR_WRITE_2(sc, EP_COMMAND,
679 SET_TX_AVAIL_THRESH | 8);
681 /* pops up the next status */
682 CSR_WRITE_1(sc, EP_W1_TX_STATUS, 0x0);
684 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
686 CSR_READ_2(sc, EP_W1_FREE_TX);
688 } /* end TX_COMPLETE */
691 CSR_WRITE_2(sc, EP_COMMAND, C_INTR_LATCH); /* ACK int Latch */
693 if ((status = CSR_READ_2(sc, EP_STATUS)) & S_5_INTS)
697 CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK | S_5_INTS);
702 epread(struct ep_softc *sc)
704 struct mbuf *top, *mcur, *m;
707 short rx_fifo2, status;
710 /* XXX Must be called with sc locked */
713 status = CSR_READ_2(sc, EP_W1_RX_STATUS);
717 if (status & ERR_RX) {
719 if (status & ERR_RX_OVERRUN) {
721 * We can think the rx latency is actually
722 * greather than we expect
724 #ifdef EP_LOCAL_STATS
725 if (EP_FTST(sc, F_RX_FIRST))
733 rx_fifo = rx_fifo2 = status & RX_BYTES_MASK;
735 if (EP_FTST(sc, F_RX_FIRST)) {
736 MGETHDR(m, M_DONTWAIT, MT_DATA);
739 if (rx_fifo >= MINCLSIZE)
740 MCLGET(m, M_DONTWAIT);
741 sc->top = sc->mcur = top = m;
742 #define EROUND ((sizeof(struct ether_header) + 3) & ~3)
743 #define EOFF (EROUND - sizeof(struct ether_header))
746 /* Read what should be the header. */
747 CSR_READ_MULTI_2(sc, EP_W1_RX_PIO_RD_1,
748 mtod(top, uint16_t *), sizeof(struct ether_header) / 2);
749 top->m_len = sizeof(struct ether_header);
750 rx_fifo -= sizeof(struct ether_header);
751 sc->cur_len = rx_fifo2;
753 /* come here if we didn't have a complete packet last time */
756 sc->cur_len += rx_fifo2;
759 /* Reads what is left in the RX FIFO */
760 while (rx_fifo > 0) {
761 lenthisone = min(rx_fifo, M_TRAILINGSPACE(m));
762 if (lenthisone == 0) { /* no room in this one */
764 MGET(m, M_DONTWAIT, MT_DATA);
767 if (rx_fifo >= MINCLSIZE)
768 MCLGET(m, M_DONTWAIT);
771 lenthisone = min(rx_fifo, M_TRAILINGSPACE(m));
773 if (EP_FTST(sc, F_ACCESS_32_BITS)) {
774 /* default for EISA configured cards */
775 CSR_READ_MULTI_4(sc, EP_W1_RX_PIO_RD_1,
776 (uint32_t *)(mtod(m, caddr_t)+m->m_len),
778 m->m_len += (lenthisone & ~3);
780 CSR_READ_MULTI_1(sc, EP_W1_RX_PIO_RD_1,
781 mtod(m, caddr_t)+m->m_len, lenthisone & 3);
782 m->m_len += (lenthisone & 3);
784 CSR_READ_MULTI_2(sc, EP_W1_RX_PIO_RD_1,
785 (uint16_t *)(mtod(m, caddr_t)+m->m_len),
787 m->m_len += lenthisone;
789 *(mtod(m, caddr_t)+m->m_len - 1) =
790 CSR_READ_1(sc, EP_W1_RX_PIO_RD_1);
792 rx_fifo -= lenthisone;
795 if (status & ERR_RX_INCOMPLETE) {
796 /* we haven't received the complete packet */
798 #ifdef EP_LOCAL_STATS
799 /* to know how often we come here */
802 EP_FRST(sc, F_RX_FIRST);
803 status = CSR_READ_2(sc, EP_W1_RX_STATUS);
804 if (!status & ERR_RX_INCOMPLETE) {
806 * We see if by now, the packet has completly
811 CSR_WRITE_2(sc, EP_COMMAND,
812 SET_RX_EARLY_THRESH | RX_NEXT_EARLY_THRESH);
815 CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);
817 EP_FSET(sc, F_RX_FIRST);
818 top->m_pkthdr.rcvif = sc->ifp;
819 top->m_pkthdr.len = sc->cur_len;
822 * Drop locks before calling if_input() since it may re-enter
823 * ep_start() in the netisr case. This would result in a
824 * lock reversal. Better performance might be obtained by
825 * chaining all packets received, dropping the lock, and then
826 * calling if_input() on each one.
829 (*ifp->if_input) (ifp, top);
833 CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
837 CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);
841 #ifdef EP_LOCAL_STATS
845 EP_FSET(sc, F_RX_FIRST);
847 CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
851 ep_ifmedia_upd(struct ifnet *ifp)
853 struct ep_softc *sc = ifp->if_softc;
857 CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
859 CSR_WRITE_2(sc, EP_W4_MEDIA_TYPE, DISABLE_UTP);
862 switch (IFM_SUBTYPE(sc->ifmedia.ifm_media)) {
864 if (sc->ep_connectors & UTP) {
865 i = ACF_CONNECTOR_UTP;
867 CSR_WRITE_2(sc, EP_W4_MEDIA_TYPE, ENABLE_UTP);
871 if (sc->ep_connectors & BNC) {
872 i = ACF_CONNECTOR_BNC;
873 CSR_WRITE_2(sc, EP_COMMAND, START_TRANSCEIVER);
874 DELAY(DELAY_MULTIPLE * 1000);
878 if (sc->ep_connectors & AUI)
879 i = ACF_CONNECTOR_AUI;
882 i = sc->ep_connector;
883 device_printf(sc->dev,
884 "strange connector type in EEPROM: assuming AUI\n");
888 j = CSR_READ_2(sc, EP_W0_ADDRESS_CFG) & 0x3fff;
889 CSR_WRITE_2(sc, EP_W0_ADDRESS_CFG, j | (i << ACF_CONNECTOR_BITS));
895 ep_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
897 struct ep_softc *sc = ifp->if_softc;
899 ifmr->ifm_active = sc->ifmedia.ifm_media;
903 epioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
905 struct ep_softc *sc = ifp->if_softc;
906 struct ifreq *ifr = (struct ifreq *) data;
912 if (((ifp->if_flags & IFF_UP) == 0) &&
913 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
914 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
917 /* reinitialize card on any parameter change */
924 * The Etherlink III has no programmable multicast
925 * filter. We always initialize the card to be
926 * promiscuous to multicast, since we're always a
927 * member of the ALL-SYSTEMS group, so there's no
928 * need to process SIOC*MULTI requests.
934 if (!sc->epb.mii_trans)
935 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, cmd);
940 error = ether_ioctl(ifp, cmd, data);
947 epwatchdog(struct ifnet *ifp)
949 struct ep_softc *sc = ifp->if_softc;
953 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
955 ep_intr(ifp->if_softc);
959 epstop(struct ep_softc *sc)
961 CSR_WRITE_2(sc, EP_COMMAND, RX_DISABLE);
962 CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);
965 CSR_WRITE_2(sc, EP_COMMAND, TX_DISABLE);
966 CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
969 CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);
971 CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
974 CSR_WRITE_2(sc, EP_COMMAND, C_INTR_LATCH);
975 CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK);
976 CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK);
977 CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER);