sys/dev/firewire/fwohci.c

   1 /*-
   2  * Copyright (c) 2003 Hidetoshi Shimokawa
   3  * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the acknowledgement as bellow:
  16  *
  17  *    This product includes software developed by K. Kobayashi and H. Shimokawa
  18  *
  19  * 4. The name of the author may not be used to endorse or promote products
  20  *    derived from this software without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  26  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  27  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  30  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  31  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  * $FreeBSD$
  35  *
  36  */
  37
  38 #define ATRQ_CH 0
  39 #define ATRS_CH 1
  40 #define ARRQ_CH 2
  41 #define ARRS_CH 3
  42 #define ITX_CH 4
  43 #define IRX_CH 0x24
  44
  45 #include <sys/param.h>
  46 #include <sys/systm.h>
  47 #include <sys/mbuf.h>
  48 #include <sys/malloc.h>
  49 #include <sys/sockio.h>
  50 #include <sys/sysctl.h>
  51 #include <sys/bus.h>
  52 #include <sys/kernel.h>
  53 #include <sys/conf.h>
  54 #include <sys/endian.h>
  55 #include <sys/kdb.h>
  56
  57 #include <machine/bus.h>
  58
  59 #if defined(__DragonFly__) || __FreeBSD_version < 500000
  60 #include <machine/clock.h>              /* for DELAY() */
  61 #endif
  62
  63 #ifdef __DragonFly__
  64 #include "firewire.h"
  65 #include "firewirereg.h"
  66 #include "fwdma.h"
  67 #include "fwohcireg.h"
  68 #include "fwohcivar.h"
  69 #include "firewire_phy.h"
  70 #else
  71 #include <dev/firewire/firewire.h>
  72 #include <dev/firewire/firewirereg.h>
  73 #include <dev/firewire/fwdma.h>
  74 #include <dev/firewire/fwohcireg.h>
  75 #include <dev/firewire/fwohcivar.h>
  76 #include <dev/firewire/firewire_phy.h>
  77 #endif
  78
  79 #undef OHCI_DEBUG
  80
  81 static int nocyclemaster = 0;
  82 int firewire_phydma_enable = 1;
  83 SYSCTL_DECL(_hw_firewire);
  84 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0,
  85         "Do not send cycle start packets");
  86 SYSCTL_INT(_hw_firewire, OID_AUTO, phydma_enable, CTLFLAG_RW,
  87         &firewire_phydma_enable, 1, "Allow physical request DMA from firewire");
  88 TUNABLE_INT("hw.firewire.phydma_enable", &firewire_phydma_enable);
  89
  90 static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
  91                 "STOR","LOAD","NOP ","STOP",};
  92
  93 static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
  94                 "UNDEF","REG","SYS","DEV"};
  95 static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
  96 char fwohcicode[32][0x20]={
  97         "No stat","Undef","long","miss Ack err",
  98         "FIFO underrun","FIFO overrun","desc err", "data read err",
  99         "data write err","bus reset","timeout","tcode err",
 100         "Undef","Undef","unknown event","flushed",
 101         "Undef","ack complete","ack pend","Undef",
 102         "ack busy_X","ack busy_A","ack busy_B","Undef",
 103         "Undef","Undef","Undef","ack tardy",
 104         "Undef","ack data_err","ack type_err",""};
 105
 106 #define MAX_SPEED 3
 107 extern char *linkspeed[];
 108 uint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
 109
 110 static struct tcode_info tinfo[] = {
 111 /*              hdr_len block   flag    valid_response */
 112 /* 0 WREQQ  */ {16,     FWTI_REQ | FWTI_TLABEL, FWTCODE_WRES},
 113 /* 1 WREQB  */ {16,     FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_WRES},
 114 /* 2 WRES   */ {12,     FWTI_RES, 0xff},
 115 /* 3 XXX    */ { 0,     0, 0xff},
 116 /* 4 RREQQ  */ {12,     FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESQ},
 117 /* 5 RREQB  */ {16,     FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESB},
 118 /* 6 RRESQ  */ {16,     FWTI_RES, 0xff},
 119 /* 7 RRESB  */ {16,     FWTI_RES | FWTI_BLOCK_ASY, 0xff},
 120 /* 8 CYCS   */ { 0,     0, 0xff},
 121 /* 9 LREQ   */ {16,     FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_LRES},
 122 /* a STREAM */ { 4,     FWTI_REQ | FWTI_BLOCK_STR, 0xff},
 123 /* b LRES   */ {16,     FWTI_RES | FWTI_BLOCK_ASY, 0xff},
 124 /* c XXX    */ { 0,     0, 0xff},
 125 /* d XXX    */ { 0,     0, 0xff},
 126 /* e PHY    */ {12,     FWTI_REQ, 0xff},
 127 /* f XXX    */ { 0,     0, 0xff}
 128 };
 129
 130 #define OHCI_WRITE_SIGMASK 0xffff0000
 131 #define OHCI_READ_SIGMASK 0xffff0000
 132
 133 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
 134 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
 135
 136 static void fwohci_ibr (struct firewire_comm *);
 137 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *);
 138 static void fwohci_db_free (struct fwohci_dbch *);
 139 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int);
 140 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *);
 141 static void fwohci_start_atq (struct firewire_comm *);
 142 static void fwohci_start_ats (struct firewire_comm *);
 143 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *);
 144 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t);
 145 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t);
 146 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *);
 147 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *);
 148 static int fwohci_irx_enable (struct firewire_comm *, int);
 149 static int fwohci_irx_disable (struct firewire_comm *, int);
 150 #if BYTE_ORDER == BIG_ENDIAN
 151 static void fwohci_irx_post (struct firewire_comm *, uint32_t *);
 152 #endif
 153 static int fwohci_itxbuf_enable (struct firewire_comm *, int);
 154 static int fwohci_itx_disable (struct firewire_comm *, int);
 155 static void fwohci_timeout (void *);
 156 static void fwohci_set_intr (struct firewire_comm *, int);
 157
 158 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *);
 159 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int);
 160 static void     dump_db (struct fwohci_softc *, uint32_t);
 161 static void     print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t);
 162 static void     dump_dma (struct fwohci_softc *, uint32_t);
 163 static uint32_t fwohci_cyctimer (struct firewire_comm *);
 164 static void fwohci_rbuf_update (struct fwohci_softc *, int);
 165 static void fwohci_tbuf_update (struct fwohci_softc *, int);
 166 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *);
 167 static void fwohci_task_busreset(void *, int);
 168 static void fwohci_task_sid(void *, int);
 169 static void fwohci_task_dma(void *, int);
 170
 171 /*
 172  * memory allocated for DMA programs
 173  */
 174 #define DMA_PROG_ALLOC          (8 * PAGE_SIZE)
 175
 176 #define NDB FWMAXQUEUE
 177
 178 #define OHCI_VERSION            0x00
 179 #define OHCI_ATRETRY            0x08
 180 #define OHCI_CROMHDR            0x18
 181 #define OHCI_BUS_OPT            0x20
 182 #define OHCI_BUSIRMC            (1 << 31)
 183 #define OHCI_BUSCMC             (1 << 30)
 184 #define OHCI_BUSISC             (1 << 29)
 185 #define OHCI_BUSBMC             (1 << 28)
 186 #define OHCI_BUSPMC             (1 << 27)
 187 #define OHCI_BUSFNC             OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
 188                                 OHCI_BUSBMC | OHCI_BUSPMC
 189
 190 #define OHCI_EUID_HI            0x24
 191 #define OHCI_EUID_LO            0x28
 192
 193 #define OHCI_CROMPTR            0x34
 194 #define OHCI_HCCCTL             0x50
 195 #define OHCI_HCCCTLCLR          0x54
 196 #define OHCI_AREQHI             0x100
 197 #define OHCI_AREQHICLR          0x104
 198 #define OHCI_AREQLO             0x108
 199 #define OHCI_AREQLOCLR          0x10c
 200 #define OHCI_PREQHI             0x110
 201 #define OHCI_PREQHICLR          0x114
 202 #define OHCI_PREQLO             0x118
 203 #define OHCI_PREQLOCLR          0x11c
 204 #define OHCI_PREQUPPER          0x120
 205
 206 #define OHCI_SID_BUF            0x64
 207 #define OHCI_SID_CNT            0x68
 208 #define OHCI_SID_ERR            (1 << 31)
 209 #define OHCI_SID_CNT_MASK       0xffc
 210
 211 #define OHCI_IT_STAT            0x90
 212 #define OHCI_IT_STATCLR         0x94
 213 #define OHCI_IT_MASK            0x98
 214 #define OHCI_IT_MASKCLR         0x9c
 215
 216 #define OHCI_IR_STAT            0xa0
 217 #define OHCI_IR_STATCLR         0xa4
 218 #define OHCI_IR_MASK            0xa8
 219 #define OHCI_IR_MASKCLR         0xac
 220
 221 #define OHCI_LNKCTL             0xe0
 222 #define OHCI_LNKCTLCLR          0xe4
 223
 224 #define OHCI_PHYACCESS          0xec
 225 #define OHCI_CYCLETIMER         0xf0
 226
 227 #define OHCI_DMACTL(off)        (off)
 228 #define OHCI_DMACTLCLR(off)     (off + 4)
 229 #define OHCI_DMACMD(off)        (off + 0xc)
 230 #define OHCI_DMAMATCH(off)      (off + 0x10)
 231
 232 #define OHCI_ATQOFF             0x180
 233 #define OHCI_ATQCTL             OHCI_ATQOFF
 234 #define OHCI_ATQCTLCLR          (OHCI_ATQOFF + 4)
 235 #define OHCI_ATQCMD             (OHCI_ATQOFF + 0xc)
 236 #define OHCI_ATQMATCH           (OHCI_ATQOFF + 0x10)
 237
 238 #define OHCI_ATSOFF             0x1a0
 239 #define OHCI_ATSCTL             OHCI_ATSOFF
 240 #define OHCI_ATSCTLCLR          (OHCI_ATSOFF + 4)
 241 #define OHCI_ATSCMD             (OHCI_ATSOFF + 0xc)
 242 #define OHCI_ATSMATCH           (OHCI_ATSOFF + 0x10)
 243
 244 #define OHCI_ARQOFF             0x1c0
 245 #define OHCI_ARQCTL             OHCI_ARQOFF
 246 #define OHCI_ARQCTLCLR          (OHCI_ARQOFF + 4)
 247 #define OHCI_ARQCMD             (OHCI_ARQOFF + 0xc)
 248 #define OHCI_ARQMATCH           (OHCI_ARQOFF + 0x10)
 249
 250 #define OHCI_ARSOFF             0x1e0
 251 #define OHCI_ARSCTL             OHCI_ARSOFF
 252 #define OHCI_ARSCTLCLR          (OHCI_ARSOFF + 4)
 253 #define OHCI_ARSCMD             (OHCI_ARSOFF + 0xc)
 254 #define OHCI_ARSMATCH           (OHCI_ARSOFF + 0x10)
 255
 256 #define OHCI_ITOFF(CH)          (0x200 + 0x10 * (CH))
 257 #define OHCI_ITCTL(CH)          (OHCI_ITOFF(CH))
 258 #define OHCI_ITCTLCLR(CH)       (OHCI_ITOFF(CH) + 4)
 259 #define OHCI_ITCMD(CH)          (OHCI_ITOFF(CH) + 0xc)
 260
 261 #define OHCI_IROFF(CH)          (0x400 + 0x20 * (CH))
 262 #define OHCI_IRCTL(CH)          (OHCI_IROFF(CH))
 263 #define OHCI_IRCTLCLR(CH)       (OHCI_IROFF(CH) + 4)
 264 #define OHCI_IRCMD(CH)          (OHCI_IROFF(CH) + 0xc)
 265 #define OHCI_IRMATCH(CH)        (OHCI_IROFF(CH) + 0x10)
 266
 267 d_ioctl_t fwohci_ioctl;
 268
 269 /*
 270  * Communication with PHY device
 271  */
 272 /* XXX need lock for phy access */
 273 static uint32_t
 274 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data)
 275 {
 276         uint32_t fun;
 277
 278         addr &= 0xf;
 279         data &= 0xff;
 280
 281         fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
 282         OWRITE(sc, OHCI_PHYACCESS, fun);
 283         DELAY(100);
 284
 285         return(fwphy_rddata( sc, addr));
 286 }
 287
 288 static uint32_t
 289 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
 290 {
 291         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
 292         int i;
 293         uint32_t bm;
 294
 295 #define OHCI_CSR_DATA   0x0c
 296 #define OHCI_CSR_COMP   0x10
 297 #define OHCI_CSR_CONT   0x14
 298 #define OHCI_BUS_MANAGER_ID     0
 299
 300         OWRITE(sc, OHCI_CSR_DATA, node);
 301         OWRITE(sc, OHCI_CSR_COMP, 0x3f);
 302         OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
 303         for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
 304                 DELAY(10);
 305         bm = OREAD(sc, OHCI_CSR_DATA);
 306         if((bm & 0x3f) == 0x3f)
 307                 bm = node;
 308         if (firewire_debug)
 309                 device_printf(sc->fc.dev,
 310                         "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
 311
 312         return(bm);
 313 }
 314
 315 static uint32_t
 316 fwphy_rddata(struct fwohci_softc *sc,  u_int addr)
 317 {
 318         uint32_t fun, stat;
 319         u_int i, retry = 0;
 320
 321         addr &= 0xf;
 322 #define MAX_RETRY 100
 323 again:
 324         OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
 325         fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
 326         OWRITE(sc, OHCI_PHYACCESS, fun);
 327         for ( i = 0 ; i < MAX_RETRY ; i ++ ){
 328                 fun = OREAD(sc, OHCI_PHYACCESS);
 329                 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
 330                         break;
 331                 DELAY(100);
 332         }
 333         if(i >= MAX_RETRY) {
 334                 if (firewire_debug)
 335                         device_printf(sc->fc.dev, "phy read failed(1).\n");
 336                 if (++retry < MAX_RETRY) {
 337                         DELAY(100);
 338                         goto again;
 339                 }
 340         }
 341         /* Make sure that SCLK is started */
 342         stat = OREAD(sc, FWOHCI_INTSTAT);
 343         if ((stat & OHCI_INT_REG_FAIL) != 0 ||
 344                         ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
 345                 if (firewire_debug)
 346                         device_printf(sc->fc.dev, "phy read failed(2).\n");
 347                 if (++retry < MAX_RETRY) {
 348                         DELAY(100);
 349                         goto again;
 350                 }
 351         }
 352         if (firewire_debug || retry >= MAX_RETRY)
 353                 device_printf(sc->fc.dev,
 354                     "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry);
 355 #undef MAX_RETRY
 356         return((fun >> PHYDEV_RDDATA )& 0xff);
 357 }
 358 /* Device specific ioctl. */
 359 int
 360 fwohci_ioctl (struct cdev *dev, u_long cmd, caddr_t data, int flag, fw_proc *td)
 361 {
 362         struct firewire_softc *sc;
 363         struct fwohci_softc *fc;
 364         int unit = DEV2UNIT(dev);
 365         int err = 0;
 366         struct fw_reg_req_t *reg  = (struct fw_reg_req_t *) data;
 367         uint32_t *dmach = (uint32_t *) data;
 368
 369         sc = devclass_get_softc(firewire_devclass, unit);
 370         if(sc == NULL){
 371                 return(EINVAL);
 372         }
 373         fc = (struct fwohci_softc *)sc->fc;
 374
 375         if (!data)
 376                 return(EINVAL);
 377
 378         switch (cmd) {
 379         case FWOHCI_WRREG:
 380 #define OHCI_MAX_REG 0x800
 381                 if(reg->addr <= OHCI_MAX_REG){
 382                         OWRITE(fc, reg->addr, reg->data);
 383                         reg->data = OREAD(fc, reg->addr);
 384                 }else{
 385                         err = EINVAL;
 386                 }
 387                 break;
 388         case FWOHCI_RDREG:
 389                 if(reg->addr <= OHCI_MAX_REG){
 390                         reg->data = OREAD(fc, reg->addr);
 391                 }else{
 392                         err = EINVAL;
 393                 }
 394                 break;
 395 /* Read DMA descriptors for debug  */
 396         case DUMPDMA:
 397                 if(*dmach <= OHCI_MAX_DMA_CH ){
 398                         dump_dma(fc, *dmach);
 399                         dump_db(fc, *dmach);
 400                 }else{
 401                         err = EINVAL;
 402                 }
 403                 break;
 404 /* Read/Write Phy registers */
 405 #define OHCI_MAX_PHY_REG 0xf
 406         case FWOHCI_RDPHYREG:
 407                 if (reg->addr <= OHCI_MAX_PHY_REG)
 408                         reg->data = fwphy_rddata(fc, reg->addr);
 409                 else
 410                         err = EINVAL;
 411                 break;
 412         case FWOHCI_WRPHYREG:
 413                 if (reg->addr <= OHCI_MAX_PHY_REG)
 414                         reg->data = fwphy_wrdata(fc, reg->addr, reg->data);
 415                 else
 416                         err = EINVAL;
 417                 break;
 418         default:
 419                 err = EINVAL;
 420                 break;
 421         }
 422         return err;
 423 }
 424
 425 static int
 426 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
 427 {
 428         uint32_t reg, reg2;
 429         int e1394a = 1;
 430 /*
 431  * probe PHY parameters
 432  * 0. to prove PHY version, whether compliance of 1394a.
 433  * 1. to probe maximum speed supported by the PHY and
 434  *    number of port supported by core-logic.
 435  *    It is not actually available port on your PC .
 436  */
 437         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
 438         DELAY(500);
 439
 440         reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
 441
 442         if((reg >> 5) != 7 ){
 443                 sc->fc.mode &= ~FWPHYASYST;
 444                 sc->fc.nport = reg & FW_PHY_NP;
 445                 sc->fc.speed = reg & FW_PHY_SPD >> 6;
 446                 if (sc->fc.speed > MAX_SPEED) {
 447                         device_printf(dev, "invalid speed %d (fixed to %d).\n",
 448                                 sc->fc.speed, MAX_SPEED);
 449                         sc->fc.speed = MAX_SPEED;
 450                 }
 451                 device_printf(dev,
 452                         "Phy 1394 only %s, %d ports.\n",
 453                         linkspeed[sc->fc.speed], sc->fc.nport);
 454         }else{
 455                 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
 456                 sc->fc.mode |= FWPHYASYST;
 457                 sc->fc.nport = reg & FW_PHY_NP;
 458                 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
 459                 if (sc->fc.speed > MAX_SPEED) {
 460                         device_printf(dev, "invalid speed %d (fixed to %d).\n",
 461                                 sc->fc.speed, MAX_SPEED);
 462                         sc->fc.speed = MAX_SPEED;
 463                 }
 464                 device_printf(dev,
 465                         "Phy 1394a available %s, %d ports.\n",
 466                         linkspeed[sc->fc.speed], sc->fc.nport);
 467
 468                 /* check programPhyEnable */
 469                 reg2 = fwphy_rddata(sc, 5);
 470 #if 0
 471                 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
 472 #else   /* XXX force to enable 1394a */
 473                 if (e1394a) {
 474 #endif
 475                         if (firewire_debug)
 476                                 device_printf(dev,
 477                                         "Enable 1394a Enhancements\n");
 478                         /* enable EAA EMC */
 479                         reg2 |= 0x03;
 480                         /* set aPhyEnhanceEnable */
 481                         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
 482                         OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
 483                 } else {
 484                         /* for safe */
 485                         reg2 &= ~0x83;
 486                 }
 487                 reg2 = fwphy_wrdata(sc, 5, reg2);
 488         }
 489
 490         reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
 491         if((reg >> 5) == 7 ){
 492                 reg = fwphy_rddata(sc, 4);
 493                 reg |= 1 << 6;
 494                 fwphy_wrdata(sc, 4, reg);
 495                 reg = fwphy_rddata(sc, 4);
 496         }
 497         return 0;
 498 }
 499
 500
 501 void
 502 fwohci_reset(struct fwohci_softc *sc, device_t dev)
 503 {
 504         int i, max_rec, speed;
 505         uint32_t reg, reg2;
 506         struct fwohcidb_tr *db_tr;
 507
 508         /* Disable interrupts */
 509         OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
 510
 511         /* Now stopping all DMA channels */
 512         OWRITE(sc,  OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
 513         OWRITE(sc,  OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
 514         OWRITE(sc,  OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
 515         OWRITE(sc,  OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
 516
 517         OWRITE(sc,  OHCI_IR_MASKCLR, ~0);
 518         for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
 519                 OWRITE(sc,  OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
 520                 OWRITE(sc,  OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
 521         }
 522
 523         /* FLUSH FIFO and reset Transmitter/Reciever */
 524         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
 525         if (firewire_debug)
 526                 device_printf(dev, "resetting OHCI...");
 527         i = 0;
 528         while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
 529                 if (i++ > 100) break;
 530                 DELAY(1000);
 531         }
 532         if (firewire_debug)
 533                 printf("done (loop=%d)\n", i);
 534
 535         /* Probe phy */
 536         fwohci_probe_phy(sc, dev);
 537
 538         /* Probe link */
 539         reg = OREAD(sc,  OHCI_BUS_OPT);
 540         reg2 = reg | OHCI_BUSFNC;
 541         max_rec = (reg & 0x0000f000) >> 12;
 542         speed = (reg & 0x00000007);
 543         device_printf(dev, "Link %s, max_rec %d bytes.\n",
 544                         linkspeed[speed], MAXREC(max_rec));
 545         /* XXX fix max_rec */
 546         sc->fc.maxrec = sc->fc.speed + 8;
 547         if (max_rec != sc->fc.maxrec) {
 548                 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12);
 549                 device_printf(dev, "max_rec %d -> %d\n",
 550                                 MAXREC(max_rec), MAXREC(sc->fc.maxrec));
 551         }
 552         if (firewire_debug)
 553                 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
 554         OWRITE(sc,  OHCI_BUS_OPT, reg2);
 555
 556         /* Initialize registers */
 557         OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
 558         OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr);
 559         OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
 560         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
 561         OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
 562         OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
 563
 564         /* Enable link */
 565         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
 566
 567         /* Force to start async RX DMA */
 568         sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
 569         sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
 570         fwohci_rx_enable(sc, &sc->arrq);
 571         fwohci_rx_enable(sc, &sc->arrs);
 572
 573         /* Initialize async TX */
 574         OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
 575         OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
 576
 577         /* AT Retries */
 578         OWRITE(sc, FWOHCI_RETRY,
 579                 /* CycleLimit   PhyRespRetries ATRespRetries ATReqRetries */
 580                 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
 581
 582         sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq);
 583         sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq);
 584         sc->atrq.bottom = sc->atrq.top;
 585         sc->atrs.bottom = sc->atrs.top;
 586
 587         for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
 588                                 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
 589                 db_tr->xfer = NULL;
 590         }
 591         for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
 592                                 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
 593                 db_tr->xfer = NULL;
 594         }
 595
 596
 597         /* Enable interrupts */
 598         sc->intmask =  (OHCI_INT_ERR  | OHCI_INT_PHY_SID
 599                         | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
 600                         | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
 601                         | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
 602         sc->intmask |=  OHCI_INT_DMA_IR | OHCI_INT_DMA_IT;
 603         sc->intmask |=  OHCI_INT_CYC_LOST | OHCI_INT_PHY_INT;
 604         OWRITE(sc, FWOHCI_INTMASK, sc->intmask);
 605         fwohci_set_intr(&sc->fc, 1);
 606
 607 }
 608
 609 int
 610 fwohci_init(struct fwohci_softc *sc, device_t dev)
 611 {
 612         int i, mver;
 613         uint32_t reg;
 614         uint8_t ui[8];
 615
 616 /* OHCI version */
 617         reg = OREAD(sc, OHCI_VERSION);
 618         mver = (reg >> 16) & 0xff;
 619         device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
 620                         mver, reg & 0xff, (reg>>24) & 1);
 621         if (mver < 1 || mver > 9) {
 622                 device_printf(dev, "invalid OHCI version\n");
 623                 return (ENXIO);
 624         }
 625
 626 /* Available Isochronous DMA channel probe */
 627         OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
 628         OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
 629         reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
 630         OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
 631         OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
 632         for (i = 0; i < 0x20; i++)
 633                 if ((reg & (1 << i)) == 0)
 634                         break;
 635         sc->fc.nisodma = i;
 636         device_printf(dev, "No. of Isochronous channels is %d.\n", i);
 637         if (i == 0)
 638                 return (ENXIO);
 639
 640         sc->fc.arq = &sc->arrq.xferq;
 641         sc->fc.ars = &sc->arrs.xferq;
 642         sc->fc.atq = &sc->atrq.xferq;
 643         sc->fc.ats = &sc->atrs.xferq;
 644
 645         sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
 646         sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
 647         sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
 648         sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
 649
 650         sc->arrq.xferq.start = NULL;
 651         sc->arrs.xferq.start = NULL;
 652         sc->atrq.xferq.start = fwohci_start_atq;
 653         sc->atrs.xferq.start = fwohci_start_ats;
 654
 655         sc->arrq.xferq.buf = NULL;
 656         sc->arrs.xferq.buf = NULL;
 657         sc->atrq.xferq.buf = NULL;
 658         sc->atrs.xferq.buf = NULL;
 659
 660         sc->arrq.xferq.dmach = -1;
 661         sc->arrs.xferq.dmach = -1;
 662         sc->atrq.xferq.dmach = -1;
 663         sc->atrs.xferq.dmach = -1;
 664
 665         sc->arrq.ndesc = 1;
 666         sc->arrs.ndesc = 1;
 667         sc->atrq.ndesc = 8;     /* equal to maximum of mbuf chains */
 668         sc->atrs.ndesc = 2;
 669
 670         sc->arrq.ndb = NDB;
 671         sc->arrs.ndb = NDB / 2;
 672         sc->atrq.ndb = NDB;
 673         sc->atrs.ndb = NDB / 2;
 674
 675         for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
 676                 sc->fc.it[i] = &sc->it[i].xferq;
 677                 sc->fc.ir[i] = &sc->ir[i].xferq;
 678                 sc->it[i].xferq.dmach = i;
 679                 sc->ir[i].xferq.dmach = i;
 680                 sc->it[i].ndb = 0;
 681                 sc->ir[i].ndb = 0;
 682         }
 683
 684         sc->fc.tcode = tinfo;
 685         sc->fc.dev = dev;
 686
 687         sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE,
 688                                                 &sc->crom_dma, BUS_DMA_WAITOK);
 689         if(sc->fc.config_rom == NULL){
 690                 device_printf(dev, "config_rom alloc failed.");
 691                 return ENOMEM;
 692         }
 693
 694 #if 0
 695         bzero(&sc->fc.config_rom[0], CROMSIZE);
 696         sc->fc.config_rom[1] = 0x31333934;
 697         sc->fc.config_rom[2] = 0xf000a002;
 698         sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
 699         sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
 700         sc->fc.config_rom[5] = 0;
 701         sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
 702
 703         sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
 704 #endif
 705
 706
 707 /* SID recieve buffer must align 2^11 */
 708 #define OHCI_SIDSIZE    (1 << 11)
 709         sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
 710                                                 &sc->sid_dma, BUS_DMA_WAITOK);
 711         if (sc->sid_buf == NULL) {
 712                 device_printf(dev, "sid_buf alloc failed.");
 713                 return ENOMEM;
 714         }
 715
 716         fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t),
 717                                         &sc->dummy_dma, BUS_DMA_WAITOK);
 718
 719         if (sc->dummy_dma.v_addr == NULL) {
 720                 device_printf(dev, "dummy_dma alloc failed.");
 721                 return ENOMEM;
 722         }
 723
 724         fwohci_db_init(sc, &sc->arrq);
 725         if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0)
 726                 return ENOMEM;
 727
 728         fwohci_db_init(sc, &sc->arrs);
 729         if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0)
 730                 return ENOMEM;
 731
 732         fwohci_db_init(sc, &sc->atrq);
 733         if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0)
 734                 return ENOMEM;
 735
 736         fwohci_db_init(sc, &sc->atrs);
 737         if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0)
 738                 return ENOMEM;
 739
 740         sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H);
 741         sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L);
 742         for( i = 0 ; i < 8 ; i ++)
 743                 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i);
 744         device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
 745                 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
 746
 747         sc->fc.ioctl = fwohci_ioctl;
 748         sc->fc.cyctimer = fwohci_cyctimer;
 749         sc->fc.set_bmr = fwohci_set_bus_manager;
 750         sc->fc.ibr = fwohci_ibr;
 751         sc->fc.irx_enable = fwohci_irx_enable;
 752         sc->fc.irx_disable = fwohci_irx_disable;
 753
 754         sc->fc.itx_enable = fwohci_itxbuf_enable;
 755         sc->fc.itx_disable = fwohci_itx_disable;
 756 #if BYTE_ORDER == BIG_ENDIAN
 757         sc->fc.irx_post = fwohci_irx_post;
 758 #else
 759         sc->fc.irx_post = NULL;
 760 #endif
 761         sc->fc.itx_post = NULL;
 762         sc->fc.timeout = fwohci_timeout;
 763         sc->fc.poll = fwohci_poll;
 764         sc->fc.set_intr = fwohci_set_intr;
 765
 766         sc->intmask = sc->irstat = sc->itstat = 0;
 767
 768         /* Init task queue */
 769         sc->fc.taskqueue = taskqueue_create_fast("fw_taskq", M_WAITOK,
 770                 taskqueue_thread_enqueue, &sc->fc.taskqueue);
 771         taskqueue_start_threads(&sc->fc.taskqueue, 1, PI_NET, "fw%d_taskq",
 772                                         device_get_unit(dev));
 773         TASK_INIT(&sc->fwohci_task_busreset, 2, fwohci_task_busreset, sc);
 774         TASK_INIT(&sc->fwohci_task_sid, 1, fwohci_task_sid, sc);
 775         TASK_INIT(&sc->fwohci_task_dma, 0, fwohci_task_dma, sc);
 776
 777         fw_init(&sc->fc);
 778         fwohci_reset(sc, dev);
 779
 780         return 0;
 781 }
 782
 783 void
 784 fwohci_timeout(void *arg)
 785 {
 786         struct fwohci_softc *sc;
 787
 788         sc = (struct fwohci_softc *)arg;
 789 }
 790
 791 uint32_t
 792 fwohci_cyctimer(struct firewire_comm *fc)
 793 {
 794         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
 795         return(OREAD(sc, OHCI_CYCLETIMER));
 796 }
 797
 798 int
 799 fwohci_detach(struct fwohci_softc *sc, device_t dev)
 800 {
 801         int i;
 802
 803         if (sc->sid_buf != NULL)
 804                 fwdma_free(&sc->fc, &sc->sid_dma);
 805         if (sc->fc.config_rom != NULL)
 806                 fwdma_free(&sc->fc, &sc->crom_dma);
 807
 808         fwohci_db_free(&sc->arrq);
 809         fwohci_db_free(&sc->arrs);
 810
 811         fwohci_db_free(&sc->atrq);
 812         fwohci_db_free(&sc->atrs);
 813
 814         for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
 815                 fwohci_db_free(&sc->it[i]);
 816                 fwohci_db_free(&sc->ir[i]);
 817         }
 818         if (sc->fc.taskqueue != NULL) {
 819                 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_busreset);
 820                 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_sid);
 821                 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_dma);
 822                 taskqueue_drain(sc->fc.taskqueue, &sc->fc.task_timeout);
 823                 taskqueue_free(sc->fc.taskqueue);
 824                 sc->fc.taskqueue = NULL;
 825         }
 826
 827         return 0;
 828 }
 829
 830 #define LAST_DB(dbtr, db) do {                                          \
 831         struct fwohcidb_tr *_dbtr = (dbtr);                             \
 832         int _cnt = _dbtr->dbcnt;                                        \
 833         db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0];                   \
 834 } while (0)
 835
 836 static void
 837 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 838 {
 839         struct fwohcidb_tr *db_tr;
 840         struct fwohcidb *db;
 841         bus_dma_segment_t *s;
 842         int i;
 843
 844         db_tr = (struct fwohcidb_tr *)arg;
 845         db = &db_tr->db[db_tr->dbcnt];
 846         if (error) {
 847                 if (firewire_debug || error != EFBIG)
 848                         printf("fwohci_execute_db: error=%d\n", error);
 849                 return;
 850         }
 851         for (i = 0; i < nseg; i++) {
 852                 s = &segs[i];
 853                 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr);
 854                 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len);
 855                 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
 856                 db++;
 857                 db_tr->dbcnt++;
 858         }
 859 }
 860
 861 static void
 862 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg,
 863                                                 bus_size_t size, int error)
 864 {
 865         fwohci_execute_db(arg, segs, nseg, error);
 866 }
 867
 868 static void
 869 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
 870 {
 871         int i, s;
 872         int tcode, hdr_len, pl_off;
 873         int fsegment = -1;
 874         uint32_t off;
 875         struct fw_xfer *xfer;
 876         struct fw_pkt *fp;
 877         struct fwohci_txpkthdr *ohcifp;
 878         struct fwohcidb_tr *db_tr;
 879         struct fwohcidb *db;
 880         uint32_t *ld;
 881         struct tcode_info *info;
 882         static int maxdesc=0;
 883
 884         FW_GLOCK_ASSERT(&sc->fc);
 885
 886         if(&sc->atrq == dbch){
 887                 off = OHCI_ATQOFF;
 888         }else if(&sc->atrs == dbch){
 889                 off = OHCI_ATSOFF;
 890         }else{
 891                 return;
 892         }
 893
 894         if (dbch->flags & FWOHCI_DBCH_FULL)
 895                 return;
 896
 897         s = splfw();
 898         db_tr = dbch->top;
 899 txloop:
 900         xfer = STAILQ_FIRST(&dbch->xferq.q);
 901         if(xfer == NULL){
 902                 goto kick;
 903         }
 904 #if 0
 905         if(dbch->xferq.queued == 0 ){
 906                 device_printf(sc->fc.dev, "TX queue empty\n");
 907         }
 908 #endif
 909         STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
 910         db_tr->xfer = xfer;
 911         xfer->flag = FWXF_START;
 912
 913         fp = &xfer->send.hdr;
 914         tcode = fp->mode.common.tcode;
 915
 916         ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
 917         info = &tinfo[tcode];
 918         hdr_len = pl_off = info->hdr_len;
 919
 920         ld = &ohcifp->mode.ld[0];
 921         ld[0] = ld[1] = ld[2] = ld[3] = 0;
 922         for( i = 0 ; i < pl_off ; i+= 4)
 923                 ld[i/4] = fp->mode.ld[i/4];
 924
 925         ohcifp->mode.common.spd = xfer->send.spd & 0x7;
 926         if (tcode == FWTCODE_STREAM ){
 927                 hdr_len = 8;
 928                 ohcifp->mode.stream.len = fp->mode.stream.len;
 929         } else if (tcode == FWTCODE_PHY) {
 930                 hdr_len = 12;
 931                 ld[1] = fp->mode.ld[1];
 932                 ld[2] = fp->mode.ld[2];
 933                 ohcifp->mode.common.spd = 0;
 934                 ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
 935         } else {
 936                 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst;
 937                 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
 938                 ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
 939         }
 940         db = &db_tr->db[0];
 941         FWOHCI_DMA_WRITE(db->db.desc.cmd,
 942                         OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len);
 943         FWOHCI_DMA_WRITE(db->db.desc.addr, 0);
 944         FWOHCI_DMA_WRITE(db->db.desc.res, 0);
 945 /* Specify bound timer of asy. responce */
 946         if(&sc->atrs == dbch){
 947                 FWOHCI_DMA_WRITE(db->db.desc.res,
 948                          (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13));
 949         }
 950 #if BYTE_ORDER == BIG_ENDIAN
 951         if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ)
 952                 hdr_len = 12;
 953         for (i = 0; i < hdr_len/4; i ++)
 954                 FWOHCI_DMA_WRITE(ld[i], ld[i]);
 955 #endif
 956
 957 again:
 958         db_tr->dbcnt = 2;
 959         db = &db_tr->db[db_tr->dbcnt];
 960         if (xfer->send.pay_len > 0) {
 961                 int err;
 962                 /* handle payload */
 963                 if (xfer->mbuf == NULL) {
 964                         err = bus_dmamap_load(dbch->dmat, db_tr->dma_map,
 965                                 &xfer->send.payload[0], xfer->send.pay_len,
 966                                 fwohci_execute_db, db_tr,
 967                                 /*flags*/0);
 968                 } else {
 969                         /* XXX we can handle only 6 (=8-2) mbuf chains */
 970                         err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
 971                                 xfer->mbuf,
 972                                 fwohci_execute_db2, db_tr,
 973                                 /* flags */0);
 974                         if (err == EFBIG) {
 975                                 struct mbuf *m0;
 976
 977                                 if (firewire_debug)
 978                                         device_printf(sc->fc.dev, "EFBIG.\n");
 979                                 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 980                                 if (m0 != NULL) {
 981                                         m_copydata(xfer->mbuf, 0,
 982                                                 xfer->mbuf->m_pkthdr.len,
 983                                                 mtod(m0, caddr_t));
 984                                         m0->m_len = m0->m_pkthdr.len =
 985                                                 xfer->mbuf->m_pkthdr.len;
 986                                         m_freem(xfer->mbuf);
 987                                         xfer->mbuf = m0;
 988                                         goto again;
 989                                 }
 990                                 device_printf(sc->fc.dev, "m_getcl failed.\n");
 991                         }
 992                 }
 993                 if (err)
 994                         printf("dmamap_load: err=%d\n", err);
 995                 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
 996                                                 BUS_DMASYNC_PREWRITE);
 997 #if 0 /* OHCI_OUTPUT_MODE == 0 */
 998                 for (i = 2; i < db_tr->dbcnt; i++)
 999                         FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
1000                                                 OHCI_OUTPUT_MORE);
1001 #endif
1002         }
1003         if (maxdesc < db_tr->dbcnt) {
1004                 maxdesc = db_tr->dbcnt;
1005                 if (firewire_debug)
1006                         device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc);
1007         }
1008         /* last db */
1009         LAST_DB(db_tr, db);
1010         FWOHCI_DMA_SET(db->db.desc.cmd,
1011                 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1012         FWOHCI_DMA_WRITE(db->db.desc.depend,
1013                         STAILQ_NEXT(db_tr, link)->bus_addr);
1014
1015         if(fsegment == -1 )
1016                 fsegment = db_tr->dbcnt;
1017         if (dbch->pdb_tr != NULL) {
1018                 LAST_DB(dbch->pdb_tr, db);
1019                 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
1020         }
1021         dbch->xferq.queued ++;
1022         dbch->pdb_tr = db_tr;
1023         db_tr = STAILQ_NEXT(db_tr, link);
1024         if(db_tr != dbch->bottom){
1025                 goto txloop;
1026         } else {
1027                 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
1028                 dbch->flags |= FWOHCI_DBCH_FULL;
1029         }
1030 kick:
1031         /* kick asy q */
1032         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1033         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1034
1035         if(dbch->xferq.flag & FWXFERQ_RUNNING) {
1036                 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
1037         } else {
1038                 if (firewire_debug)
1039                         device_printf(sc->fc.dev, "start AT DMA status=%x\n",
1040                                         OREAD(sc, OHCI_DMACTL(off)));
1041                 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment);
1042                 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1043                 dbch->xferq.flag |= FWXFERQ_RUNNING;
1044         }
1045
1046         dbch->top = db_tr;
1047         splx(s);
1048         return;
1049 }
1050
1051 static void
1052 fwohci_start_atq(struct firewire_comm *fc)
1053 {
1054         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1055         FW_GLOCK(&sc->fc);
1056         fwohci_start( sc, &(sc->atrq));
1057         FW_GUNLOCK(&sc->fc);
1058         return;
1059 }
1060
1061 static void
1062 fwohci_start_ats(struct firewire_comm *fc)
1063 {
1064         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1065         FW_GLOCK(&sc->fc);
1066         fwohci_start( sc, &(sc->atrs));
1067         FW_GUNLOCK(&sc->fc);
1068         return;
1069 }
1070
1071 void
1072 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1073 {
1074         int s, ch, err = 0;
1075         struct fwohcidb_tr *tr;
1076         struct fwohcidb *db;
1077         struct fw_xfer *xfer;
1078         uint32_t off;
1079         u_int stat, status;
1080         int     packets;
1081         struct firewire_comm *fc = (struct firewire_comm *)sc;
1082
1083         if(&sc->atrq == dbch){
1084                 off = OHCI_ATQOFF;
1085                 ch = ATRQ_CH;
1086         }else if(&sc->atrs == dbch){
1087                 off = OHCI_ATSOFF;
1088                 ch = ATRS_CH;
1089         }else{
1090                 return;
1091         }
1092         s = splfw();
1093         tr = dbch->bottom;
1094         packets = 0;
1095         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
1096         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
1097         while(dbch->xferq.queued > 0){
1098                 LAST_DB(tr, db);
1099                 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT;
1100                 if(!(status & OHCI_CNTL_DMA_ACTIVE)){
1101                         if (fc->status != FWBUSINIT)
1102                                 /* maybe out of order?? */
1103                                 goto out;
1104                 }
1105                 bus_dmamap_sync(dbch->dmat, tr->dma_map,
1106                         BUS_DMASYNC_POSTWRITE);
1107                 bus_dmamap_unload(dbch->dmat, tr->dma_map);
1108 #if 1
1109                 if (firewire_debug > 1)
1110                         dump_db(sc, ch);
1111 #endif
1112                 if(status & OHCI_CNTL_DMA_DEAD) {
1113                         /* Stop DMA */
1114                         OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1115                         device_printf(sc->fc.dev, "force reset AT FIFO\n");
1116                         OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
1117                         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
1118                         OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1119                 }
1120                 stat = status & FWOHCIEV_MASK;
1121                 switch(stat){
1122                 case FWOHCIEV_ACKPEND:
1123                 case FWOHCIEV_ACKCOMPL:
1124                         err = 0;
1125                         break;
1126                 case FWOHCIEV_ACKBSA:
1127                 case FWOHCIEV_ACKBSB:
1128                 case FWOHCIEV_ACKBSX:
1129                         device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1130                         err = EBUSY;
1131                         break;
1132                 case FWOHCIEV_FLUSHED:
1133                 case FWOHCIEV_ACKTARD:
1134                         device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1135                         err = EAGAIN;
1136                         break;
1137                 case FWOHCIEV_MISSACK:
1138                 case FWOHCIEV_UNDRRUN:
1139                 case FWOHCIEV_OVRRUN:
1140                 case FWOHCIEV_DESCERR:
1141                 case FWOHCIEV_DTRDERR:
1142                 case FWOHCIEV_TIMEOUT:
1143                 case FWOHCIEV_TCODERR:
1144                 case FWOHCIEV_UNKNOWN:
1145                 case FWOHCIEV_ACKDERR:
1146                 case FWOHCIEV_ACKTERR:
1147                 default:
1148                         device_printf(sc->fc.dev, "txd err=%2x %s\n",
1149                                                         stat, fwohcicode[stat]);
1150                         err = EINVAL;
1151                         break;
1152                 }
1153                 if (tr->xfer != NULL) {
1154                         xfer = tr->xfer;
1155                         if (xfer->flag & FWXF_RCVD) {
1156 #if 0
1157                                 if (firewire_debug)
1158                                         printf("already rcvd\n");
1159 #endif
1160                                 fw_xfer_done(xfer);
1161                         } else {
1162                                 microtime(&xfer->tv);
1163                                 xfer->flag = FWXF_SENT;
1164                                 if (err == EBUSY) {
1165                                         xfer->flag = FWXF_BUSY;
1166                                         xfer->resp = err;
1167                                         xfer->recv.pay_len = 0;
1168                                         fw_xfer_done(xfer);
1169                                 } else if (stat != FWOHCIEV_ACKPEND) {
1170                                         if (stat != FWOHCIEV_ACKCOMPL)
1171                                                 xfer->flag = FWXF_SENTERR;
1172                                         xfer->resp = err;
1173                                         xfer->recv.pay_len = 0;
1174                                         fw_xfer_done(xfer);
1175                                 }
1176                         }
1177                         /*
1178                          * The watchdog timer takes care of split
1179                          * transcation timeout for ACKPEND case.
1180                          */
1181                 } else {
1182                         printf("this shouldn't happen\n");
1183                 }
1184                 FW_GLOCK(fc);
1185                 dbch->xferq.queued --;
1186                 FW_GUNLOCK(fc);
1187                 tr->xfer = NULL;
1188
1189                 packets ++;
1190                 tr = STAILQ_NEXT(tr, link);
1191                 dbch->bottom = tr;
1192                 if (dbch->bottom == dbch->top) {
1193                         /* we reaches the end of context program */
1194                         if (firewire_debug && dbch->xferq.queued > 0)
1195                                 printf("queued > 0\n");
1196                         break;
1197                 }
1198         }
1199 out:
1200         if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1201                 printf("make free slot\n");
1202                 dbch->flags &= ~FWOHCI_DBCH_FULL;
1203                 FW_GLOCK(fc);
1204                 fwohci_start(sc, dbch);
1205                 FW_GUNLOCK(fc);
1206         }
1207         splx(s);
1208 }
1209
1210 static void
1211 fwohci_db_free(struct fwohci_dbch *dbch)
1212 {
1213         struct fwohcidb_tr *db_tr;
1214         int idb;
1215
1216         if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1217                 return;
1218
1219         for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb;
1220                         db_tr = STAILQ_NEXT(db_tr, link), idb++){
1221                 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 &&
1222                                         db_tr->buf != NULL) {
1223                         fwdma_free_size(dbch->dmat, db_tr->dma_map,
1224                                         db_tr->buf, dbch->xferq.psize);
1225                         db_tr->buf = NULL;
1226                 } else if (db_tr->dma_map != NULL)
1227                         bus_dmamap_destroy(dbch->dmat, db_tr->dma_map);
1228         }
1229         dbch->ndb = 0;
1230         db_tr = STAILQ_FIRST(&dbch->db_trq);
1231         fwdma_free_multiseg(dbch->am);
1232         free(db_tr, M_FW);
1233         STAILQ_INIT(&dbch->db_trq);
1234         dbch->flags &= ~FWOHCI_DBCH_INIT;
1235 }
1236
1237 static void
1238 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1239 {
1240         int     idb;
1241         struct fwohcidb_tr *db_tr;
1242
1243         if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1244                 goto out;
1245
1246         /* create dma_tag for buffers */
1247 #define MAX_REQCOUNT    0xffff
1248         if (bus_dma_tag_create(/*parent*/ sc->fc.dmat,
1249                         /*alignment*/ 1, /*boundary*/ 0,
1250                         /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
1251                         /*highaddr*/ BUS_SPACE_MAXADDR,
1252                         /*filter*/NULL, /*filterarg*/NULL,
1253                         /*maxsize*/ dbch->xferq.psize,
1254                         /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1,
1255                         /*maxsegsz*/ MAX_REQCOUNT,
1256                         /*flags*/ 0,
1257 #if defined(__FreeBSD__) && __FreeBSD_version >= 501102
1258                         /*lockfunc*/busdma_lock_mutex,
1259                         /*lockarg*/FW_GMTX(&sc->fc),
1260 #endif
1261                         &dbch->dmat))
1262                 return;
1263
1264         /* allocate DB entries and attach one to each DMA channels */
1265         /* DB entry must start at 16 bytes bounary. */
1266         STAILQ_INIT(&dbch->db_trq);
1267         db_tr = (struct fwohcidb_tr *)
1268                 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1269                 M_FW, M_WAITOK | M_ZERO);
1270         if(db_tr == NULL){
1271                 printf("fwohci_db_init: malloc(1) failed\n");
1272                 return;
1273         }
1274
1275 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc)
1276         dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch),
1277                 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK);
1278         if (dbch->am == NULL) {
1279                 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n");
1280                 free(db_tr, M_FW);
1281                 return;
1282         }
1283         /* Attach DB to DMA ch. */
1284         for(idb = 0 ; idb < dbch->ndb ; idb++){
1285                 db_tr->dbcnt = 0;
1286                 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1287                 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1288                 /* create dmamap for buffers */
1289                 /* XXX do we need 4bytes alignment tag? */
1290                 /* XXX don't alloc dma_map for AR */
1291                 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) {
1292                         printf("bus_dmamap_create failed\n");
1293                         dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */
1294                         fwohci_db_free(dbch);
1295                         return;
1296                 }
1297                 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1298                 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1299                         if (idb % dbch->xferq.bnpacket == 0)
1300                                 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1301                                                 ].start = (caddr_t)db_tr;
1302                         if ((idb + 1) % dbch->xferq.bnpacket == 0)
1303                                 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1304                                                 ].end = (caddr_t)db_tr;
1305                 }
1306                 db_tr++;
1307         }
1308         STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1309                         = STAILQ_FIRST(&dbch->db_trq);
1310 out:
1311         dbch->xferq.queued = 0;
1312         dbch->pdb_tr = NULL;
1313         dbch->top = STAILQ_FIRST(&dbch->db_trq);
1314         dbch->bottom = dbch->top;
1315         dbch->flags = FWOHCI_DBCH_INIT;
1316 }
1317
1318 static int
1319 fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1320 {
1321         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1322
1323         OWRITE(sc, OHCI_ITCTLCLR(dmach),
1324                         OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S);
1325         OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1326         OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1327         /* XXX we cannot free buffers until the DMA really stops */
1328         pause("fwitxd", hz);
1329         fwohci_db_free(&sc->it[dmach]);
1330         sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1331         return 0;
1332 }
1333
1334 static int
1335 fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1336 {
1337         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1338
1339         OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1340         OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1341         OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1342         /* XXX we cannot free buffers until the DMA really stops */
1343         pause("fwirxd", hz);
1344         fwohci_db_free(&sc->ir[dmach]);
1345         sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1346         return 0;
1347 }
1348
1349 #if BYTE_ORDER == BIG_ENDIAN
1350 static void
1351 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld)
1352 {
1353         qld[0] = FWOHCI_DMA_READ(qld[0]);
1354         return;
1355 }
1356 #endif
1357
1358 static int
1359 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1360 {
1361         int err = 0;
1362         int idb, z, i, dmach = 0, ldesc;
1363         uint32_t off = 0;
1364         struct fwohcidb_tr *db_tr;
1365         struct fwohcidb *db;
1366
1367         if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1368                 err = EINVAL;
1369                 return err;
1370         }
1371         z = dbch->ndesc;
1372         for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1373                 if( &sc->it[dmach] == dbch){
1374                         off = OHCI_ITOFF(dmach);
1375                         break;
1376                 }
1377         }
1378         if(off == 0){
1379                 err = EINVAL;
1380                 return err;
1381         }
1382         if(dbch->xferq.flag & FWXFERQ_RUNNING)
1383                 return err;
1384         dbch->xferq.flag |= FWXFERQ_RUNNING;
1385         for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1386                 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1387         }
1388         db_tr = dbch->top;
1389         for (idb = 0; idb < dbch->ndb; idb ++) {
1390                 fwohci_add_tx_buf(dbch, db_tr, idb);
1391                 if(STAILQ_NEXT(db_tr, link) == NULL){
1392                         break;
1393                 }
1394                 db = db_tr->db;
1395                 ldesc = db_tr->dbcnt - 1;
1396                 FWOHCI_DMA_WRITE(db[0].db.desc.depend,
1397                                 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1398                 db[ldesc].db.desc.depend = db[0].db.desc.depend;
1399                 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1400                         if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1401                                 FWOHCI_DMA_SET(
1402                                         db[ldesc].db.desc.cmd,
1403                                         OHCI_INTERRUPT_ALWAYS);
1404                                 /* OHCI 1.1 and above */
1405                                 FWOHCI_DMA_SET(
1406                                         db[0].db.desc.cmd,
1407                                         OHCI_INTERRUPT_ALWAYS);
1408                         }
1409                 }
1410                 db_tr = STAILQ_NEXT(db_tr, link);
1411         }
1412         FWOHCI_DMA_CLEAR(
1413                 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf);
1414         return err;
1415 }
1416
1417 static int
1418 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1419 {
1420         int err = 0;
1421         int idb, z, i, dmach = 0, ldesc;
1422         uint32_t off = 0;
1423         struct fwohcidb_tr *db_tr;
1424         struct fwohcidb *db;
1425
1426         z = dbch->ndesc;
1427         if(&sc->arrq == dbch){
1428                 off = OHCI_ARQOFF;
1429         }else if(&sc->arrs == dbch){
1430                 off = OHCI_ARSOFF;
1431         }else{
1432                 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1433                         if( &sc->ir[dmach] == dbch){
1434                                 off = OHCI_IROFF(dmach);
1435                                 break;
1436                         }
1437                 }
1438         }
1439         if(off == 0){
1440                 err = EINVAL;
1441                 return err;
1442         }
1443         if(dbch->xferq.flag & FWXFERQ_STREAM){
1444                 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1445                         return err;
1446         }else{
1447                 if(dbch->xferq.flag & FWXFERQ_RUNNING){
1448                         err = EBUSY;
1449                         return err;
1450                 }
1451         }
1452         dbch->xferq.flag |= FWXFERQ_RUNNING;
1453         dbch->top = STAILQ_FIRST(&dbch->db_trq);
1454         for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1455                 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1456         }
1457         db_tr = dbch->top;
1458         for (idb = 0; idb < dbch->ndb; idb ++) {
1459                 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1460                 if (STAILQ_NEXT(db_tr, link) == NULL)
1461                         break;
1462                 db = db_tr->db;
1463                 ldesc = db_tr->dbcnt - 1;
1464                 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend,
1465                         STAILQ_NEXT(db_tr, link)->bus_addr | z);
1466                 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1467                         if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1468                                 FWOHCI_DMA_SET(
1469                                         db[ldesc].db.desc.cmd,
1470                                         OHCI_INTERRUPT_ALWAYS);
1471                                 FWOHCI_DMA_CLEAR(
1472                                         db[ldesc].db.desc.depend,
1473                                         0xf);
1474                         }
1475                 }
1476                 db_tr = STAILQ_NEXT(db_tr, link);
1477         }
1478         FWOHCI_DMA_CLEAR(
1479                 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1480         dbch->buf_offset = 0;
1481         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1482         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1483         if(dbch->xferq.flag & FWXFERQ_STREAM){
1484                 return err;
1485         }else{
1486                 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z);
1487         }
1488         OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1489         return err;
1490 }
1491
1492 static int
1493 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now)
1494 {
1495         int sec, cycle, cycle_match;
1496
1497         cycle = cycle_now & 0x1fff;
1498         sec = cycle_now >> 13;
1499 #define CYCLE_MOD       0x10
1500 #if 1
1501 #define CYCLE_DELAY     8       /* min delay to start DMA */
1502 #else
1503 #define CYCLE_DELAY     7000    /* min delay to start DMA */
1504 #endif
1505         cycle = cycle + CYCLE_DELAY;
1506         if (cycle >= 8000) {
1507                 sec ++;
1508                 cycle -= 8000;
1509         }
1510         cycle = roundup2(cycle, CYCLE_MOD);
1511         if (cycle >= 8000) {
1512                 sec ++;
1513                 if (cycle == 8000)
1514                         cycle = 0;
1515                 else
1516                         cycle = CYCLE_MOD;
1517         }
1518         cycle_match = ((sec << 13) | cycle) & 0x7ffff;
1519
1520         return(cycle_match);
1521 }
1522
1523 static int
1524 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1525 {
1526         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1527         int err = 0;
1528         unsigned short tag, ich;
1529         struct fwohci_dbch *dbch;
1530         int cycle_match, cycle_now, s, ldesc;
1531         uint32_t stat;
1532         struct fw_bulkxfer *first, *chunk, *prev;
1533         struct fw_xferq *it;
1534
1535         dbch = &sc->it[dmach];
1536         it = &dbch->xferq;
1537
1538         tag = (it->flag >> 6) & 3;
1539         ich = it->flag & 0x3f;
1540         if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1541                 dbch->ndb = it->bnpacket * it->bnchunk;
1542                 dbch->ndesc = 3;
1543                 fwohci_db_init(sc, dbch);
1544                 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1545                         return ENOMEM;
1546
1547                 err = fwohci_tx_enable(sc, dbch);
1548         }
1549         if(err)
1550                 return err;
1551
1552         ldesc = dbch->ndesc - 1;
1553         s = splfw();
1554         FW_GLOCK(fc);
1555         prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link);
1556         while  ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) {
1557                 struct fwohcidb *db;
1558
1559                 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket,
1560                                         BUS_DMASYNC_PREWRITE);
1561                 fwohci_txbufdb(sc, dmach, chunk);
1562                 if (prev != NULL) {
1563                         db = ((struct fwohcidb_tr *)(prev->end))->db;
1564 #if 0 /* XXX necessary? */
1565                         FWOHCI_DMA_SET(db[ldesc].db.desc.cmd,
1566                                                 OHCI_BRANCH_ALWAYS);
1567 #endif
1568 #if 0 /* if bulkxfer->npacket changes */
1569                         db[ldesc].db.desc.depend = db[0].db.desc.depend =
1570                                 ((struct fwohcidb_tr *)
1571                                 (chunk->start))->bus_addr | dbch->ndesc;
1572 #else
1573                         FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
1574                         FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1575 #endif
1576                 }
1577                 STAILQ_REMOVE_HEAD(&it->stvalid, link);
1578                 STAILQ_INSERT_TAIL(&it->stdma, chunk, link);
1579                 prev = chunk;
1580         }
1581         FW_GUNLOCK(fc);
1582         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1583         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1584         splx(s);
1585         stat = OREAD(sc, OHCI_ITCTL(dmach));
1586         if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S))
1587                 printf("stat 0x%x\n", stat);
1588
1589         if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S))
1590                 return 0;
1591
1592 #if 0
1593         OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1594 #endif
1595         OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1596         OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1597         OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1598         OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1599
1600         first = STAILQ_FIRST(&it->stdma);
1601         OWRITE(sc, OHCI_ITCMD(dmach),
1602                 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc);
1603         if (firewire_debug > 1) {
1604                 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat);
1605 #if 1
1606                 dump_dma(sc, ITX_CH + dmach);
1607 #endif
1608         }
1609         if ((stat & OHCI_CNTL_DMA_RUN) == 0) {
1610 #if 1
1611                 /* Don't start until all chunks are buffered */
1612                 if (STAILQ_FIRST(&it->stfree) != NULL)
1613                         goto out;
1614 #endif
1615 #if 1
1616                 /* Clear cycle match counter bits */
1617                 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000);
1618
1619                 /* 2bit second + 13bit cycle */
1620                 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff;
1621                 cycle_match = fwohci_next_cycle(fc, cycle_now);
1622
1623                 OWRITE(sc, OHCI_ITCTL(dmach),
1624                                 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16)
1625                                 | OHCI_CNTL_DMA_RUN);
1626 #else
1627                 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1628 #endif
1629                 if (firewire_debug > 1) {
1630                         printf("cycle_match: 0x%04x->0x%04x\n",
1631                                                 cycle_now, cycle_match);
1632                         dump_dma(sc, ITX_CH + dmach);
1633                         dump_db(sc, ITX_CH + dmach);
1634                 }
1635         } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) {
1636                 device_printf(sc->fc.dev,
1637                         "IT DMA underrun (0x%08x)\n", stat);
1638                 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE);
1639         }
1640 out:
1641         return err;
1642 }
1643
1644 static int
1645 fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1646 {
1647         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1648         int err = 0, s, ldesc;
1649         unsigned short tag, ich;
1650         uint32_t stat;
1651         struct fwohci_dbch *dbch;
1652         struct fwohcidb_tr *db_tr;
1653         struct fw_bulkxfer *first, *prev, *chunk;
1654         struct fw_xferq *ir;
1655
1656         dbch = &sc->ir[dmach];
1657         ir = &dbch->xferq;
1658
1659         if ((ir->flag & FWXFERQ_RUNNING) == 0) {
1660                 tag = (ir->flag >> 6) & 3;
1661                 ich = ir->flag & 0x3f;
1662                 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1663
1664                 ir->queued = 0;
1665                 dbch->ndb = ir->bnpacket * ir->bnchunk;
1666                 dbch->ndesc = 2;
1667                 fwohci_db_init(sc, dbch);
1668                 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1669                         return ENOMEM;
1670                 err = fwohci_rx_enable(sc, dbch);
1671         }
1672         if(err)
1673                 return err;
1674
1675         first = STAILQ_FIRST(&ir->stfree);
1676         if (first == NULL) {
1677                 device_printf(fc->dev, "IR DMA no free chunk\n");
1678                 return 0;
1679         }
1680
1681         ldesc = dbch->ndesc - 1;
1682         s = splfw();
1683         if ((ir->flag & FWXFERQ_HANDLER) == 0)
1684                 FW_GLOCK(fc);
1685         prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link);
1686         while  ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) {
1687                 struct fwohcidb *db;
1688
1689 #if 1 /* XXX for if_fwe */
1690                 if (chunk->mbuf != NULL) {
1691                         db_tr = (struct fwohcidb_tr *)(chunk->start);
1692                         db_tr->dbcnt = 1;
1693                         err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
1694                                         chunk->mbuf, fwohci_execute_db2, db_tr,
1695                                         /* flags */0);
1696                         FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd,
1697                                 OHCI_UPDATE | OHCI_INPUT_LAST |
1698                                 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1699                 }
1700 #endif
1701                 db = ((struct fwohcidb_tr *)(chunk->end))->db;
1702                 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0);
1703                 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf);
1704                 if (prev != NULL) {
1705                         db = ((struct fwohcidb_tr *)(prev->end))->db;
1706                         FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1707                 }
1708                 STAILQ_REMOVE_HEAD(&ir->stfree, link);
1709                 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link);
1710                 prev = chunk;
1711         }
1712         if ((ir->flag & FWXFERQ_HANDLER) == 0)
1713                 FW_GUNLOCK(fc);
1714         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1715         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1716         splx(s);
1717         stat = OREAD(sc, OHCI_IRCTL(dmach));
1718         if (stat & OHCI_CNTL_DMA_ACTIVE)
1719                 return 0;
1720         if (stat & OHCI_CNTL_DMA_RUN) {
1721                 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1722                 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat);
1723         }
1724
1725         if (firewire_debug)
1726                 printf("start IR DMA 0x%x\n", stat);
1727         OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1728         OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1729         OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1730         OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000);
1731         OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1732         OWRITE(sc, OHCI_IRCMD(dmach),
1733                 ((struct fwohcidb_tr *)(first->start))->bus_addr
1734                                                         | dbch->ndesc);
1735         OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1736         OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1737 #if 0
1738         dump_db(sc, IRX_CH + dmach);
1739 #endif
1740         return err;
1741 }
1742
1743 int
1744 fwohci_stop(struct fwohci_softc *sc, device_t dev)
1745 {
1746         u_int i;
1747
1748 /* Now stopping all DMA channel */
1749         OWRITE(sc,  OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1750         OWRITE(sc,  OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1751         OWRITE(sc,  OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1752         OWRITE(sc,  OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1753
1754         for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1755                 OWRITE(sc,  OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1756                 OWRITE(sc,  OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1757         }
1758
1759         if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0)
1760                 fw_drain_txq(&sc->fc);
1761
1762 #if 0 /* Let dcons(4) be accessed */
1763 /* Stop interrupt */
1764         OWRITE(sc, FWOHCI_INTMASKCLR,
1765                         OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1766                         | OHCI_INT_PHY_INT
1767                         | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1768                         | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1769                         | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1770                         | OHCI_INT_PHY_BUS_R);
1771
1772 /* FLUSH FIFO and reset Transmitter/Reciever */
1773         OWRITE(sc,  OHCI_HCCCTL, OHCI_HCC_RESET);
1774 #endif
1775
1776 /* XXX Link down?  Bus reset? */
1777         return 0;
1778 }
1779
1780 int
1781 fwohci_resume(struct fwohci_softc *sc, device_t dev)
1782 {
1783         int i;
1784         struct fw_xferq *ir;
1785         struct fw_bulkxfer *chunk;
1786
1787         fwohci_reset(sc, dev);
1788         /* XXX resume isochronous receive automatically. (how about TX?) */
1789         for(i = 0; i < sc->fc.nisodma; i ++) {
1790                 ir = &sc->ir[i].xferq;
1791                 if((ir->flag & FWXFERQ_RUNNING) != 0) {
1792                         device_printf(sc->fc.dev,
1793                                 "resume iso receive ch: %d\n", i);
1794                         ir->flag &= ~FWXFERQ_RUNNING;
1795                         /* requeue stdma to stfree */
1796                         while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
1797                                 STAILQ_REMOVE_HEAD(&ir->stdma, link);
1798                                 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link);
1799                         }
1800                         sc->fc.irx_enable(&sc->fc, i);
1801                 }
1802         }
1803
1804         bus_generic_resume(dev);
1805         sc->fc.ibr(&sc->fc);
1806         return 0;
1807 }
1808
1809 #ifdef OHCI_DEBUG
1810 static void
1811 fwohci_dump_intr(struct fwohci_softc *sc, uint32_t stat)
1812 {
1813         if(stat & OREAD(sc, FWOHCI_INTMASK))
1814                 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1815                         stat & OHCI_INT_EN ? "DMA_EN ":"",
1816                         stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1817                         stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1818                         stat & OHCI_INT_ERR ? "INT_ERR ":"",
1819                         stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1820                         stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1821                         stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1822                         stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1823                         stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1824                         stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1825                         stat & OHCI_INT_PHY_SID ? "SID ":"",
1826                         stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1827                         stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1828                         stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1829                         stat & OHCI_INT_DMA_IT  ? "DMA_IT " :"",
1830                         stat & OHCI_INT_DMA_PRRS  ? "DMA_PRRS " :"",
1831                         stat & OHCI_INT_DMA_PRRQ  ? "DMA_PRRQ " :"",
1832                         stat & OHCI_INT_DMA_ARRS  ? "DMA_ARRS " :"",
1833                         stat & OHCI_INT_DMA_ARRQ  ? "DMA_ARRQ " :"",
1834                         stat & OHCI_INT_DMA_ATRS  ? "DMA_ATRS " :"",
1835                         stat & OHCI_INT_DMA_ATRQ  ? "DMA_ATRQ " :"",
1836                         stat, OREAD(sc, FWOHCI_INTMASK)
1837                 );
1838 }
1839 #endif
1840 static void
1841 fwohci_intr_core(struct fwohci_softc *sc, uint32_t stat, int count)
1842 {
1843         struct firewire_comm *fc = (struct firewire_comm *)sc;
1844         uint32_t node_id, plen;
1845
1846         if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) {
1847                 fc->status = FWBUSRESET;
1848                 /* Disable bus reset interrupt until sid recv. */
1849                 OWRITE(sc, FWOHCI_INTMASKCLR,  OHCI_INT_PHY_BUS_R);
1850
1851                 device_printf(fc->dev, "BUS reset\n");
1852                 OWRITE(sc, FWOHCI_INTMASKCLR,  OHCI_INT_CYC_LOST);
1853                 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1854
1855                 OWRITE(sc,  OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1856                 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1857                 OWRITE(sc,  OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1858                 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1859
1860                 if (!kdb_active)
1861                         taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_busreset);
1862         }
1863         if (stat & OHCI_INT_PHY_SID) {
1864                 /* Enable bus reset interrupt */
1865                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1866                 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
1867
1868                 /* Allow async. request to us */
1869                 OWRITE(sc, OHCI_AREQHI, 1 << 31);
1870                 if (firewire_phydma_enable) {
1871                         /* allow from all nodes */
1872                         OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1873                         OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1874                         /* 0 to 4GB region */
1875                         OWRITE(sc, OHCI_PREQUPPER, 0x10000);
1876                 }
1877                 /* Set ATRetries register */
1878                 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
1879
1880                 /*
1881                  * Checking whether the node is root or not. If root, turn on
1882                  * cycle master.
1883                  */
1884                 node_id = OREAD(sc, FWOHCI_NODEID);
1885                 plen = OREAD(sc, OHCI_SID_CNT);
1886
1887                 fc->nodeid = node_id & 0x3f;
1888                 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
1889                         node_id, (plen >> 16) & 0xff);
1890                 if (!(node_id & OHCI_NODE_VALID)) {
1891                         printf("Bus reset failure\n");
1892                         goto sidout;
1893                 }
1894
1895                 /* cycle timer */
1896                 sc->cycle_lost = 0;
1897                 OWRITE(sc, FWOHCI_INTMASK,  OHCI_INT_CYC_LOST);
1898                 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) {
1899                         printf("CYCLEMASTER mode\n");
1900                         OWRITE(sc, OHCI_LNKCTL,
1901                                 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1902                 } else {
1903                         printf("non CYCLEMASTER mode\n");
1904                         OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1905                         OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1906                 }
1907
1908                 fc->status = FWBUSINIT;
1909
1910                 if (!kdb_active)
1911                         taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_sid);
1912         }
1913 sidout:
1914         if ((stat & ~(OHCI_INT_PHY_BUS_R | OHCI_INT_PHY_SID)) && (!kdb_active))
1915                 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_dma);
1916 }
1917
1918 static void
1919 fwohci_intr_dma(struct fwohci_softc *sc, uint32_t stat, int count)
1920 {
1921         uint32_t irstat, itstat;
1922         u_int i;
1923         struct firewire_comm *fc = (struct firewire_comm *)sc;
1924
1925         if (stat & OHCI_INT_DMA_IR) {
1926                 irstat = atomic_readandclear_int(&sc->irstat);
1927                 for(i = 0; i < fc->nisodma ; i++){
1928                         struct fwohci_dbch *dbch;
1929
1930                         if((irstat & (1 << i)) != 0){
1931                                 dbch = &sc->ir[i];
1932                                 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
1933                                         device_printf(sc->fc.dev,
1934                                                 "dma(%d) not active\n", i);
1935                                         continue;
1936                                 }
1937                                 fwohci_rbuf_update(sc, i);
1938                         }
1939                 }
1940         }
1941         if (stat & OHCI_INT_DMA_IT) {
1942                 itstat = atomic_readandclear_int(&sc->itstat);
1943                 for(i = 0; i < fc->nisodma ; i++){
1944                         if((itstat & (1 << i)) != 0){
1945                                 fwohci_tbuf_update(sc, i);
1946                         }
1947                 }
1948         }
1949         if (stat & OHCI_INT_DMA_PRRS) {
1950 #if 0
1951                 dump_dma(sc, ARRS_CH);
1952                 dump_db(sc, ARRS_CH);
1953 #endif
1954                 fwohci_arcv(sc, &sc->arrs, count);
1955         }
1956         if (stat & OHCI_INT_DMA_PRRQ) {
1957 #if 0
1958                 dump_dma(sc, ARRQ_CH);
1959                 dump_db(sc, ARRQ_CH);
1960 #endif
1961                 fwohci_arcv(sc, &sc->arrq, count);
1962         }
1963         if (stat & OHCI_INT_CYC_LOST) {
1964                 if (sc->cycle_lost >= 0)
1965                         sc->cycle_lost ++;
1966                 if (sc->cycle_lost > 10) {
1967                         sc->cycle_lost = -1;
1968 #if 0
1969                         OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER);
1970 #endif
1971                         OWRITE(sc, FWOHCI_INTMASKCLR,  OHCI_INT_CYC_LOST);
1972                         device_printf(fc->dev, "too many cycle lost, "
1973                          "no cycle master presents?\n");
1974                 }
1975         }
1976         if (stat & OHCI_INT_DMA_ATRQ) {
1977                 fwohci_txd(sc, &(sc->atrq));
1978         }
1979         if (stat & OHCI_INT_DMA_ATRS) {
1980                 fwohci_txd(sc, &(sc->atrs));
1981         }
1982         if (stat & OHCI_INT_PW_ERR) {
1983                 device_printf(fc->dev, "posted write error\n");
1984         }
1985         if (stat & OHCI_INT_ERR) {
1986                 device_printf(fc->dev, "unrecoverable error\n");
1987         }
1988         if (stat & OHCI_INT_PHY_INT) {
1989                 device_printf(fc->dev, "phy int\n");
1990         }
1991
1992         return;
1993 }
1994
1995 static void
1996 fwohci_task_busreset(void *arg, int pending)
1997 {
1998         struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1999
2000         fw_busreset(&sc->fc, FWBUSRESET);
2001         OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
2002         OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
2003 }
2004
2005 static void
2006 fwohci_task_sid(void *arg, int pending)
2007 {
2008         struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2009         struct firewire_comm *fc = &sc->fc;
2010         uint32_t *buf;
2011         int i, plen;
2012
2013
2014         plen = OREAD(sc, OHCI_SID_CNT);
2015
2016         if (plen & OHCI_SID_ERR) {
2017                 device_printf(fc->dev, "SID Error\n");
2018                 return;
2019         }
2020         plen &= OHCI_SID_CNT_MASK;
2021         if (plen < 4 || plen > OHCI_SIDSIZE) {
2022                 device_printf(fc->dev, "invalid SID len = %d\n", plen);
2023                 return;
2024         }
2025         plen -= 4; /* chop control info */
2026         buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT);
2027         if (buf == NULL) {
2028                 device_printf(fc->dev, "malloc failed\n");
2029                 return;
2030         }
2031         for (i = 0; i < plen / 4; i ++)
2032                 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
2033 #if 1 /* XXX needed?? */
2034         /* pending all pre-bus_reset packets */
2035         fwohci_txd(sc, &sc->atrq);
2036         fwohci_txd(sc, &sc->atrs);
2037         fwohci_arcv(sc, &sc->arrs, -1);
2038         fwohci_arcv(sc, &sc->arrq, -1);
2039         fw_drain_txq(fc);
2040 #endif
2041         fw_sidrcv(fc, buf, plen);
2042         free(buf, M_FW);
2043 }
2044
2045 static void
2046 fwohci_task_dma(void *arg, int pending)
2047 {
2048         struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2049         uint32_t stat;
2050
2051 again:
2052         stat = atomic_readandclear_int(&sc->intstat);
2053         if (stat)
2054                 fwohci_intr_dma(sc, stat, -1);
2055         else
2056                 return;
2057         goto again;
2058 }
2059
2060 static int
2061 fwohci_check_stat(struct fwohci_softc *sc)
2062 {
2063         uint32_t stat, irstat, itstat;
2064
2065         stat = OREAD(sc, FWOHCI_INTSTAT);
2066         if (stat == 0xffffffff) {
2067                 device_printf(sc->fc.dev,
2068                         "device physically ejected?\n");
2069                 return (FILTER_STRAY);
2070         }
2071         if (stat)
2072                 OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R);
2073
2074         stat &= sc->intmask;
2075         if (stat == 0)
2076                 return (FILTER_STRAY);
2077
2078         atomic_set_int(&sc->intstat, stat);
2079         if (stat & OHCI_INT_DMA_IR) {
2080                 irstat = OREAD(sc, OHCI_IR_STAT);
2081                 OWRITE(sc, OHCI_IR_STATCLR, irstat);
2082                 atomic_set_int(&sc->irstat, irstat);
2083         }
2084         if (stat & OHCI_INT_DMA_IT) {
2085                 itstat = OREAD(sc, OHCI_IT_STAT);
2086                 OWRITE(sc, OHCI_IT_STATCLR, itstat);
2087                 atomic_set_int(&sc->itstat, itstat);
2088         }
2089
2090         fwohci_intr_core(sc, stat, -1);
2091         return (FILTER_HANDLED);
2092 }
2093
2094 int
2095 fwohci_filt(void *arg)
2096 {
2097         struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2098
2099         if (!(sc->intmask & OHCI_INT_EN)) {
2100                 /* polling mode */
2101                 return (FILTER_STRAY);
2102         }
2103         return (fwohci_check_stat(sc));
2104 }
2105
2106 void
2107 fwohci_intr(void *arg)
2108 {
2109         fwohci_filt(arg);
2110 }
2111
2112 void
2113 fwohci_poll(struct firewire_comm *fc, int quick, int count)
2114 {
2115         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
2116         fwohci_check_stat(sc);
2117 }
2118
2119 static void
2120 fwohci_set_intr(struct firewire_comm *fc, int enable)
2121 {
2122         struct fwohci_softc *sc;
2123
2124         sc = (struct fwohci_softc *)fc;
2125         if (firewire_debug)
2126                 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
2127         if (enable) {
2128                 sc->intmask |= OHCI_INT_EN;
2129                 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
2130         } else {
2131                 sc->intmask &= ~OHCI_INT_EN;
2132                 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
2133         }
2134 }
2135
2136 static void
2137 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
2138 {
2139         struct firewire_comm *fc = &sc->fc;
2140         struct fwohcidb *db;
2141         struct fw_bulkxfer *chunk;
2142         struct fw_xferq *it;
2143         uint32_t stat, count;
2144         int s, w=0, ldesc;
2145
2146         it = fc->it[dmach];
2147         ldesc = sc->it[dmach].ndesc - 1;
2148         s = splfw(); /* unnecessary ? */
2149         FW_GLOCK(fc);
2150         fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
2151         if (firewire_debug)
2152                 dump_db(sc, ITX_CH + dmach);
2153         while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) {
2154                 db = ((struct fwohcidb_tr *)(chunk->end))->db;
2155                 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2156                                 >> OHCI_STATUS_SHIFT;
2157                 db = ((struct fwohcidb_tr *)(chunk->start))->db;
2158                 /* timestamp */
2159                 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2160                                 & OHCI_COUNT_MASK;
2161                 if (stat == 0)
2162                         break;
2163                 STAILQ_REMOVE_HEAD(&it->stdma, link);
2164                 switch (stat & FWOHCIEV_MASK){
2165                 case FWOHCIEV_ACKCOMPL:
2166 #if 0
2167                         device_printf(fc->dev, "0x%08x\n", count);
2168 #endif
2169                         break;
2170                 default:
2171                         device_printf(fc->dev,
2172                                 "Isochronous transmit err %02x(%s)\n",
2173                                         stat, fwohcicode[stat & 0x1f]);
2174                 }
2175                 STAILQ_INSERT_TAIL(&it->stfree, chunk, link);
2176                 w++;
2177         }
2178         FW_GUNLOCK(fc);
2179         splx(s);
2180         if (w)
2181                 wakeup(it);
2182 }
2183
2184 static void
2185 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2186 {
2187         struct firewire_comm *fc = &sc->fc;
2188         struct fwohcidb_tr *db_tr;
2189         struct fw_bulkxfer *chunk;
2190         struct fw_xferq *ir;
2191         uint32_t stat;
2192         int s, w = 0, ldesc;
2193
2194         ir = fc->ir[dmach];
2195         ldesc = sc->ir[dmach].ndesc - 1;
2196
2197 #if 0
2198         dump_db(sc, dmach);
2199 #endif
2200         s = splfw();
2201         if ((ir->flag & FWXFERQ_HANDLER) == 0)
2202                 FW_GLOCK(fc);
2203         fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD);
2204         while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
2205                 db_tr = (struct fwohcidb_tr *)chunk->end;
2206                 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2207                                 >> OHCI_STATUS_SHIFT;
2208                 if (stat == 0)
2209                         break;
2210
2211                 if (chunk->mbuf != NULL) {
2212                         bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map,
2213                                                 BUS_DMASYNC_POSTREAD);
2214                         bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map);
2215                 } else if (ir->buf != NULL) {
2216                         fwdma_sync_multiseg(ir->buf, chunk->poffset,
2217                                 ir->bnpacket, BUS_DMASYNC_POSTREAD);
2218                 } else {
2219                         /* XXX */
2220                         printf("fwohci_rbuf_update: this shouldn't happend\n");
2221                 }
2222
2223                 STAILQ_REMOVE_HEAD(&ir->stdma, link);
2224                 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link);
2225                 switch (stat & FWOHCIEV_MASK) {
2226                 case FWOHCIEV_ACKCOMPL:
2227                         chunk->resp = 0;
2228                         break;
2229                 default:
2230                         chunk->resp = EINVAL;
2231                         device_printf(fc->dev,
2232                                 "Isochronous receive err %02x(%s)\n",
2233                                         stat, fwohcicode[stat & 0x1f]);
2234                 }
2235                 w++;
2236         }
2237         if ((ir->flag & FWXFERQ_HANDLER) == 0)
2238                 FW_GUNLOCK(fc);
2239         splx(s);
2240         if (w == 0)
2241                 return;
2242
2243         if (ir->flag & FWXFERQ_HANDLER)
2244                 ir->hand(ir);
2245         else
2246                 wakeup(ir);
2247 }
2248
2249 void
2250 dump_dma(struct fwohci_softc *sc, uint32_t ch)
2251 {
2252         uint32_t off, cntl, stat, cmd, match;
2253
2254         if(ch == 0){
2255                 off = OHCI_ATQOFF;
2256         }else if(ch == 1){
2257                 off = OHCI_ATSOFF;
2258         }else if(ch == 2){
2259                 off = OHCI_ARQOFF;
2260         }else if(ch == 3){
2261                 off = OHCI_ARSOFF;
2262         }else if(ch < IRX_CH){
2263                 off = OHCI_ITCTL(ch - ITX_CH);
2264         }else{
2265                 off = OHCI_IRCTL(ch - IRX_CH);
2266         }
2267         cntl = stat = OREAD(sc, off);
2268         cmd = OREAD(sc, off + 0xc);
2269         match = OREAD(sc, off + 0x10);
2270
2271         device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n",
2272                 ch,
2273                 cntl,
2274                 cmd,
2275                 match);
2276         stat &= 0xffff ;
2277         if (stat) {
2278                 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
2279                         ch,
2280                         stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2281                         stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2282                         stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2283                         stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2284                         stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2285                         stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2286                         fwohcicode[stat & 0x1f],
2287                         stat & 0x1f
2288                 );
2289         }else{
2290                 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
2291         }
2292 }
2293
2294 void
2295 dump_db(struct fwohci_softc *sc, uint32_t ch)
2296 {
2297         struct fwohci_dbch *dbch;
2298         struct fwohcidb_tr *cp = NULL, *pp, *np = NULL;
2299         struct fwohcidb *curr = NULL, *prev, *next = NULL;
2300         int idb, jdb;
2301         uint32_t cmd, off;
2302         if(ch == 0){
2303                 off = OHCI_ATQOFF;
2304                 dbch = &sc->atrq;
2305         }else if(ch == 1){
2306                 off = OHCI_ATSOFF;
2307                 dbch = &sc->atrs;
2308         }else if(ch == 2){
2309                 off = OHCI_ARQOFF;
2310                 dbch = &sc->arrq;
2311         }else if(ch == 3){
2312                 off = OHCI_ARSOFF;
2313                 dbch = &sc->arrs;
2314         }else if(ch < IRX_CH){
2315                 off = OHCI_ITCTL(ch - ITX_CH);
2316                 dbch = &sc->it[ch - ITX_CH];
2317         }else {
2318                 off = OHCI_IRCTL(ch - IRX_CH);
2319                 dbch = &sc->ir[ch - IRX_CH];
2320         }
2321         cmd = OREAD(sc, off + 0xc);
2322
2323         if( dbch->ndb == 0 ){
2324                 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
2325                 return;
2326         }
2327         pp = dbch->top;
2328         prev = pp->db;
2329         for(idb = 0 ; idb < dbch->ndb ; idb ++ ){
2330                 cp = STAILQ_NEXT(pp, link);
2331                 if(cp == NULL){
2332                         curr = NULL;
2333                         goto outdb;
2334                 }
2335                 np = STAILQ_NEXT(cp, link);
2336                 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){
2337                         if ((cmd  & 0xfffffff0) == cp->bus_addr) {
2338                                 curr = cp->db;
2339                                 if(np != NULL){
2340                                         next = np->db;
2341                                 }else{
2342                                         next = NULL;
2343                                 }
2344                                 goto outdb;
2345                         }
2346                 }
2347                 pp = STAILQ_NEXT(pp, link);
2348                 if(pp == NULL){
2349                         curr = NULL;
2350                         goto outdb;
2351                 }
2352                 prev = pp->db;
2353         }
2354 outdb:
2355         if( curr != NULL){
2356 #if 0
2357                 printf("Prev DB %d\n", ch);
2358                 print_db(pp, prev, ch, dbch->ndesc);
2359 #endif
2360                 printf("Current DB %d\n", ch);
2361                 print_db(cp, curr, ch, dbch->ndesc);
2362 #if 0
2363                 printf("Next DB %d\n", ch);
2364                 print_db(np, next, ch, dbch->ndesc);
2365 #endif
2366         }else{
2367                 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2368         }
2369         return;
2370 }
2371
2372 void
2373 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db,
2374                 uint32_t ch, uint32_t max)
2375 {
2376         fwohcireg_t stat;
2377         int i, key;
2378         uint32_t cmd, res;
2379
2380         if(db == NULL){
2381                 printf("No Descriptor is found\n");
2382                 return;
2383         }
2384
2385         printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2386                 ch,
2387                 "Current",
2388                 "OP  ",
2389                 "KEY",
2390                 "INT",
2391                 "BR ",
2392                 "len",
2393                 "Addr",
2394                 "Depend",
2395                 "Stat",
2396                 "Cnt");
2397         for( i = 0 ; i <= max ; i ++){
2398                 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd);
2399                 res = FWOHCI_DMA_READ(db[i].db.desc.res);
2400                 key = cmd & OHCI_KEY_MASK;
2401                 stat = res >> OHCI_STATUS_SHIFT;
2402 #if defined(__DragonFly__) || __FreeBSD_version < 500000
2403                 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x",
2404                                 db_tr->bus_addr,
2405 #else
2406                 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x",
2407                                 (uintmax_t)db_tr->bus_addr,
2408 #endif
2409                                 dbcode[(cmd >> 28) & 0xf],
2410                                 dbkey[(cmd >> 24) & 0x7],
2411                                 dbcond[(cmd >> 20) & 0x3],
2412                                 dbcond[(cmd >> 18) & 0x3],
2413                                 cmd & OHCI_COUNT_MASK,
2414                                 FWOHCI_DMA_READ(db[i].db.desc.addr),
2415                                 FWOHCI_DMA_READ(db[i].db.desc.depend),
2416                                 stat,
2417                                 res & OHCI_COUNT_MASK);
2418                 if(stat & 0xff00){
2419                         printf(" %s%s%s%s%s%s %s(%x)\n",
2420                                 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2421                                 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2422                                 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2423                                 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2424                                 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2425                                 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2426                                 fwohcicode[stat & 0x1f],
2427                                 stat & 0x1f
2428                         );
2429                 }else{
2430                         printf(" Nostat\n");
2431                 }
2432                 if(key == OHCI_KEY_ST2 ){
2433                         printf("0x%08x 0x%08x 0x%08x 0x%08x\n",
2434                                 FWOHCI_DMA_READ(db[i+1].db.immed[0]),
2435                                 FWOHCI_DMA_READ(db[i+1].db.immed[1]),
2436                                 FWOHCI_DMA_READ(db[i+1].db.immed[2]),
2437                                 FWOHCI_DMA_READ(db[i+1].db.immed[3]));
2438                 }
2439                 if(key == OHCI_KEY_DEVICE){
2440                         return;
2441                 }
2442                 if((cmd & OHCI_BRANCH_MASK)
2443                                 == OHCI_BRANCH_ALWAYS){
2444                         return;
2445                 }
2446                 if((cmd & OHCI_CMD_MASK)
2447                                 == OHCI_OUTPUT_LAST){
2448                         return;
2449                 }
2450                 if((cmd & OHCI_CMD_MASK)
2451                                 == OHCI_INPUT_LAST){
2452                         return;
2453                 }
2454                 if(key == OHCI_KEY_ST2 ){
2455                         i++;
2456                 }
2457         }
2458         return;
2459 }
2460
2461 void
2462 fwohci_ibr(struct firewire_comm *fc)
2463 {
2464         struct fwohci_softc *sc;
2465         uint32_t fun;
2466
2467         device_printf(fc->dev, "Initiate bus reset\n");
2468         sc = (struct fwohci_softc *)fc;
2469
2470         /*
2471          * Make sure our cached values from the config rom are
2472          * initialised.
2473          */
2474         OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
2475         OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
2476
2477         /*
2478          * Set root hold-off bit so that non cyclemaster capable node
2479          * shouldn't became the root node.
2480          */
2481 #if 1
2482         fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2483         fun |= FW_PHY_IBR | FW_PHY_RHB;
2484         fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2485 #else   /* Short bus reset */
2486         fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2487         fun |= FW_PHY_ISBR | FW_PHY_RHB;
2488         fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2489 #endif
2490 }
2491
2492 void
2493 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2494 {
2495         struct fwohcidb_tr *db_tr, *fdb_tr;
2496         struct fwohci_dbch *dbch;
2497         struct fwohcidb *db;
2498         struct fw_pkt *fp;
2499         struct fwohci_txpkthdr *ohcifp;
2500         unsigned short chtag;
2501         int idb;
2502
2503         FW_GLOCK_ASSERT(&sc->fc);
2504
2505         dbch = &sc->it[dmach];
2506         chtag = sc->it[dmach].xferq.flag & 0xff;
2507
2508         db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2509         fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2510 /*
2511 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2512 */
2513         for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) {
2514                 db = db_tr->db;
2515                 fp = (struct fw_pkt *)db_tr->buf;
2516                 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed;
2517                 ohcifp->mode.ld[0] = fp->mode.ld[0];
2518                 ohcifp->mode.common.spd = 0 & 0x7;
2519                 ohcifp->mode.stream.len = fp->mode.stream.len;
2520                 ohcifp->mode.stream.chtag = chtag;
2521                 ohcifp->mode.stream.tcode = 0xa;
2522 #if BYTE_ORDER == BIG_ENDIAN
2523                 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]);
2524                 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]);
2525 #endif
2526
2527                 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK);
2528                 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len);
2529                 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2530 #if 0 /* if bulkxfer->npackets changes */
2531                 db[2].db.desc.cmd = OHCI_OUTPUT_LAST
2532                         | OHCI_UPDATE
2533                         | OHCI_BRANCH_ALWAYS;
2534                 db[0].db.desc.depend =
2535                         = db[dbch->ndesc - 1].db.desc.depend
2536                         = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2537 #else
2538                 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
2539                 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc);
2540 #endif
2541                 bulkxfer->end = (caddr_t)db_tr;
2542                 db_tr = STAILQ_NEXT(db_tr, link);
2543         }
2544         db = ((struct fwohcidb_tr *)bulkxfer->end)->db;
2545         FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf);
2546         FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf);
2547 #if 0 /* if bulkxfer->npackets changes */
2548         db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2549         /* OHCI 1.1 and above */
2550         db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2551 #endif
2552 /*
2553         db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2554         fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
2555 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr);
2556 */
2557         return;
2558 }
2559
2560 static int
2561 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2562                                                                 int poffset)
2563 {
2564         struct fwohcidb *db = db_tr->db;
2565         struct fw_xferq *it;
2566         int err = 0;
2567
2568         it = &dbch->xferq;
2569         if(it->buf == 0){
2570                 err = EINVAL;
2571                 return err;
2572         }
2573         db_tr->buf = fwdma_v_addr(it->buf, poffset);
2574         db_tr->dbcnt = 3;
2575
2576         FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2577                 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8);
2578         FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0);
2579         bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed));
2580         FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2581         fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t));
2582
2583         FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2584                 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS);
2585 #if 1
2586         FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2587         FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2588 #endif
2589         return 0;
2590 }
2591
2592 int
2593 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2594                 int poffset, struct fwdma_alloc *dummy_dma)
2595 {
2596         struct fwohcidb *db = db_tr->db;
2597         struct fw_xferq *ir;
2598         int i, ldesc;
2599         bus_addr_t dbuf[2];
2600         int dsiz[2];
2601
2602         ir = &dbch->xferq;
2603         if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) {
2604                 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map,
2605                         ir->psize, &dbuf[0], BUS_DMA_NOWAIT);
2606                 if (db_tr->buf == NULL)
2607                         return(ENOMEM);
2608                 db_tr->dbcnt = 1;
2609                 dsiz[0] = ir->psize;
2610                 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2611                         BUS_DMASYNC_PREREAD);
2612         } else {
2613                 db_tr->dbcnt = 0;
2614                 if (dummy_dma != NULL) {
2615                         dsiz[db_tr->dbcnt] = sizeof(uint32_t);
2616                         dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr;
2617                 }
2618                 dsiz[db_tr->dbcnt] = ir->psize;
2619                 if (ir->buf != NULL) {
2620                         db_tr->buf = fwdma_v_addr(ir->buf, poffset);
2621                         dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset);
2622                 }
2623                 db_tr->dbcnt++;
2624         }
2625         for(i = 0 ; i < db_tr->dbcnt ; i++){
2626                 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]);
2627                 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]);
2628                 if (ir->flag & FWXFERQ_STREAM) {
2629                         FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE);
2630                 }
2631                 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]);
2632         }
2633         ldesc = db_tr->dbcnt - 1;
2634         if (ir->flag & FWXFERQ_STREAM) {
2635                 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST);
2636         }
2637         FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS);
2638         return 0;
2639 }
2640
2641
2642 static int
2643 fwohci_arcv_swap(struct fw_pkt *fp, int len)
2644 {
2645         struct fw_pkt *fp0;
2646         uint32_t ld0;
2647         int slen, hlen;
2648 #if BYTE_ORDER == BIG_ENDIAN
2649         int i;
2650 #endif
2651
2652         ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]);
2653 #if 0
2654         printf("ld0: x%08x\n", ld0);
2655 #endif
2656         fp0 = (struct fw_pkt *)&ld0;
2657         /* determine length to swap */
2658         switch (fp0->mode.common.tcode) {
2659         case FWTCODE_RREQQ:
2660         case FWTCODE_WRES:
2661         case FWTCODE_WREQQ:
2662         case FWTCODE_RRESQ:
2663         case FWOHCITCODE_PHY:
2664                 slen = 12;
2665                 break;
2666         case FWTCODE_RREQB:
2667         case FWTCODE_WREQB:
2668         case FWTCODE_LREQ:
2669         case FWTCODE_RRESB:
2670         case FWTCODE_LRES:
2671                 slen = 16;
2672                 break;
2673         default:
2674                 printf("Unknown tcode %d\n", fp0->mode.common.tcode);
2675                 return(0);
2676         }
2677         hlen = tinfo[fp0->mode.common.tcode].hdr_len;
2678         if (hlen > len) {
2679                 if (firewire_debug)
2680                         printf("splitted header\n");
2681                 return(-hlen);
2682         }
2683 #if BYTE_ORDER == BIG_ENDIAN
2684         for(i = 0; i < slen/4; i ++)
2685                 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]);
2686 #endif
2687         return(hlen);
2688 }
2689
2690 static int
2691 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp)
2692 {
2693         struct tcode_info *info;
2694         int r;
2695
2696         info = &tinfo[fp->mode.common.tcode];
2697         r = info->hdr_len + sizeof(uint32_t);
2698         if ((info->flag & FWTI_BLOCK_ASY) != 0)
2699                 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t));
2700
2701         if (r == sizeof(uint32_t)) {
2702                 /* XXX */
2703                 device_printf(sc->fc.dev, "Unknown tcode %d\n",
2704                                                 fp->mode.common.tcode);
2705                 return (-1);
2706         }
2707
2708         if (r > dbch->xferq.psize) {
2709                 device_printf(sc->fc.dev, "Invalid packet length %d\n", r);
2710                 return (-1);
2711                 /* panic ? */
2712         }
2713
2714         return r;
2715 }
2716
2717 static void
2718 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch,
2719     struct fwohcidb_tr *db_tr, uint32_t off, int wake)
2720 {
2721         struct fwohcidb *db = &db_tr->db[0];
2722
2723         FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf);
2724         FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize);
2725         FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1);
2726         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
2727         dbch->bottom = db_tr;
2728
2729         if (wake)
2730                 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
2731 }
2732
2733 static void
2734 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2735 {
2736         struct fwohcidb_tr *db_tr;
2737         struct iovec vec[2];
2738         struct fw_pkt pktbuf;
2739         int nvec;
2740         struct fw_pkt *fp;
2741         uint8_t *ld;
2742         uint32_t stat, off, status, event;
2743         u_int spd;
2744         int len, plen, hlen, pcnt, offset;
2745         int s;
2746         caddr_t buf;
2747         int resCount;
2748
2749         if(&sc->arrq == dbch){
2750                 off = OHCI_ARQOFF;
2751         }else if(&sc->arrs == dbch){
2752                 off = OHCI_ARSOFF;
2753         }else{
2754                 return;
2755         }
2756
2757         s = splfw();
2758         db_tr = dbch->top;
2759         pcnt = 0;
2760         /* XXX we cannot handle a packet which lies in more than two buf */
2761         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
2762         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
2763         status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2764         resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2765         while (status & OHCI_CNTL_DMA_ACTIVE) {
2766 #if 0
2767
2768                 if (off == OHCI_ARQOFF)
2769                         printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n",
2770                             db_tr->bus_addr, status, resCount);
2771 #endif
2772                 len = dbch->xferq.psize - resCount;
2773                 ld = (uint8_t *)db_tr->buf;
2774                 if (dbch->pdb_tr == NULL) {
2775                         len -= dbch->buf_offset;
2776                         ld += dbch->buf_offset;
2777                 }
2778                 if (len > 0)
2779                         bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2780                                         BUS_DMASYNC_POSTREAD);
2781                 while (len > 0 ) {
2782                         if (count >= 0 && count-- == 0)
2783                                 goto out;
2784                         if(dbch->pdb_tr != NULL){
2785                                 /* we have a fragment in previous buffer */
2786                                 int rlen;
2787
2788                                 offset = dbch->buf_offset;
2789                                 if (offset < 0)
2790                                         offset = - offset;
2791                                 buf = dbch->pdb_tr->buf + offset;
2792                                 rlen = dbch->xferq.psize - offset;
2793                                 if (firewire_debug)
2794                                         printf("rlen=%d, offset=%d\n",
2795                                                 rlen, dbch->buf_offset);
2796                                 if (dbch->buf_offset < 0) {
2797                                         /* splitted in header, pull up */
2798                                         char *p;
2799
2800                                         p = (char *)&pktbuf;
2801                                         bcopy(buf, p, rlen);
2802                                         p += rlen;
2803                                         /* this must be too long but harmless */
2804                                         rlen = sizeof(pktbuf) - rlen;
2805                                         if (rlen < 0)
2806                                                 printf("why rlen < 0\n");
2807                                         bcopy(db_tr->buf, p, rlen);
2808                                         ld += rlen;
2809                                         len -= rlen;
2810                                         hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf));
2811                                         if (hlen <= 0) {
2812                                                 printf("hlen should be positive.");
2813                                                 goto err;
2814                                         }
2815                                         offset = sizeof(pktbuf);
2816                                         vec[0].iov_base = (char *)&pktbuf;
2817                                         vec[0].iov_len = offset;
2818                                 } else {
2819                                         /* splitted in payload */
2820                                         offset = rlen;
2821                                         vec[0].iov_base = buf;
2822                                         vec[0].iov_len = rlen;
2823                                 }
2824                                 fp=(struct fw_pkt *)vec[0].iov_base;
2825                                 nvec = 1;
2826                         } else {
2827                                 /* no fragment in previous buffer */
2828                                 fp=(struct fw_pkt *)ld;
2829                                 hlen = fwohci_arcv_swap(fp, len);
2830                                 if (hlen == 0)
2831                                         goto err;
2832                                 if (hlen < 0) {
2833                                         dbch->pdb_tr = db_tr;
2834                                         dbch->buf_offset = - dbch->buf_offset;
2835                                         /* sanity check */
2836                                         if (resCount != 0)  {
2837                                                 printf("resCount=%d hlen=%d\n",
2838                                                     resCount, hlen);
2839                                                     goto err;
2840                                         }
2841                                         goto out;
2842                                 }
2843                                 offset = 0;
2844                                 nvec = 0;
2845                         }
2846                         plen = fwohci_get_plen(sc, dbch, fp) - offset;
2847                         if (plen < 0) {
2848                                 /* minimum header size + trailer
2849                                 = sizeof(fw_pkt) so this shouldn't happens */
2850                                 printf("plen(%d) is negative! offset=%d\n",
2851                                     plen, offset);
2852                                 goto err;
2853                         }
2854                         if (plen > 0) {
2855                                 len -= plen;
2856                                 if (len < 0) {
2857                                         dbch->pdb_tr = db_tr;
2858                                         if (firewire_debug)
2859                                                 printf("splitted payload\n");
2860                                         /* sanity check */
2861                                         if (resCount != 0)  {
2862                                                 printf("resCount=%d plen=%d"
2863                                                     " len=%d\n",
2864                                                     resCount, plen, len);
2865                                                 goto err;
2866                                         }
2867                                         goto out;
2868                                 }
2869                                 vec[nvec].iov_base = ld;
2870                                 vec[nvec].iov_len = plen;
2871                                 nvec ++;
2872                                 ld += plen;
2873                         }
2874                         dbch->buf_offset = ld - (uint8_t *)db_tr->buf;
2875                         if (nvec == 0)
2876                                 printf("nvec == 0\n");
2877
2878 /* DMA result-code will be written at the tail of packet */
2879                         stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer)));
2880 #if 0
2881                         printf("plen: %d, stat %x\n",
2882                             plen ,stat);
2883 #endif
2884                         spd = (stat >> 21) & 0x3;
2885                         event = (stat >> 16) & 0x1f;
2886                         switch (event) {
2887                         case FWOHCIEV_ACKPEND:
2888 #if 0
2889                                 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode);
2890 #endif
2891                                 /* fall through */
2892                         case FWOHCIEV_ACKCOMPL:
2893                         {
2894                                 struct fw_rcv_buf rb;
2895
2896                                 if ((vec[nvec-1].iov_len -=
2897                                         sizeof(struct fwohci_trailer)) == 0)
2898                                         nvec--;
2899                                 rb.fc = &sc->fc;
2900                                 rb.vec = vec;
2901                                 rb.nvec = nvec;
2902                                 rb.spd = spd;
2903                                 fw_rcv(&rb);
2904                                 break;
2905                         }
2906                         case FWOHCIEV_BUSRST:
2907                                 if ((sc->fc.status != FWBUSRESET) &&
2908                                     (sc->fc.status != FWBUSINIT))
2909                                         printf("got BUSRST packet!?\n");
2910                                 break;
2911                         default:
2912                                 device_printf(sc->fc.dev,
2913                                     "Async DMA Receive error err=%02x %s"
2914                                     " plen=%d offset=%d len=%d status=0x%08x"
2915                                     " tcode=0x%x, stat=0x%08x\n",
2916                                     event, fwohcicode[event], plen,
2917                                     dbch->buf_offset, len,
2918                                     OREAD(sc, OHCI_DMACTL(off)),
2919                                     fp->mode.common.tcode, stat);
2920 #if 1 /* XXX */
2921                                 goto err;
2922 #endif
2923                                 break;
2924                         }
2925                         pcnt ++;
2926                         if (dbch->pdb_tr != NULL) {
2927                                 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr,
2928                                     off, 1);
2929                                 dbch->pdb_tr = NULL;
2930                         }
2931
2932                 }
2933 out:
2934                 if (resCount == 0) {
2935                         /* done on this buffer */
2936                         if (dbch->pdb_tr == NULL) {
2937                                 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1);
2938                                 dbch->buf_offset = 0;
2939                         } else
2940                                 if (dbch->pdb_tr != db_tr)
2941                                         printf("pdb_tr != db_tr\n");
2942                         db_tr = STAILQ_NEXT(db_tr, link);
2943                         status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2944                                                 >> OHCI_STATUS_SHIFT;
2945                         resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2946                                                 & OHCI_COUNT_MASK;
2947                         /* XXX check buffer overrun */
2948                         dbch->top = db_tr;
2949                 } else {
2950                         dbch->buf_offset = dbch->xferq.psize - resCount;
2951                         break;
2952                 }
2953                 /* XXX make sure DMA is not dead */
2954         }
2955 #if 0
2956         if (pcnt < 1)
2957                 printf("fwohci_arcv: no packets\n");
2958 #endif
2959         splx(s);
2960         return;
2961
2962 err:
2963         device_printf(sc->fc.dev, "AR DMA status=%x, ",
2964                                         OREAD(sc, OHCI_DMACTL(off)));
2965         dbch->pdb_tr = NULL;
2966         /* skip until resCount != 0 */
2967         printf(" skip buffer");
2968         while (resCount == 0) {
2969                 printf(" #");
2970                 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0);
2971                 db_tr = STAILQ_NEXT(db_tr, link);
2972                 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2973                                                 & OHCI_COUNT_MASK;
2974         } while (resCount == 0)
2975         printf(" done\n");
2976         dbch->top = db_tr;
2977         dbch->buf_offset = dbch->xferq.psize - resCount;
2978         OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
2979         splx(s);
2980 }