2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
37 #ifdef HAVE_KERNEL_OPTION_HEADERS
38 #include "opt_device_polling.h"
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/endian.h>
45 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/mutex.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
56 #include <net/ethernet.h>
58 #include <net/if_arp.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_vlan_var.h>
64 #include <netinet/in.h>
65 #include <netinet/in_systm.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
70 #include <machine/bus.h>
71 #include <machine/in_cksum.h>
72 #include <machine/resource.h>
74 #include <dev/pci/pcivar.h>
75 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */
77 #include <dev/mii/mii.h>
78 #include <dev/mii/miivar.h>
80 #include <dev/fxp/if_fxpreg.h>
81 #include <dev/fxp/if_fxpvar.h>
82 #include <dev/fxp/rcvbundl.h>
84 MODULE_DEPEND(fxp, pci, 1, 1, 1);
85 MODULE_DEPEND(fxp, ether, 1, 1, 1);
86 MODULE_DEPEND(fxp, miibus, 1, 1, 1);
87 #include "miibus_if.h"
90 * NOTE! On the Alpha, we have an alignment constraint. The
91 * card DMAs the packet immediately following the RFA. However,
92 * the first thing in the packet is a 14-byte Ethernet header.
93 * This means that the packet is misaligned. To compensate,
94 * we actually offset the RFA 2 bytes into the cluster. This
95 * alignes the packet after the Ethernet header at a 32-bit
96 * boundary. HOWEVER! This means that the RFA is misaligned!
98 #define RFA_ALIGNMENT_FUDGE 2
101 * Set initial transmit threshold at 64 (512 bytes). This is
102 * increased by 64 (512 bytes) at a time, to maximum of 192
103 * (1536 bytes), if an underrun occurs.
105 static int tx_threshold = 64;
108 * The configuration byte map has several undefined fields which
109 * must be one or must be zero. Set up a template for these bits
110 * only, (assuming a 82557 chip) leaving the actual configuration
113 * See struct fxp_cb_config for the bit definitions.
115 static u_char fxp_cb_config_template[] = {
116 0x0, 0x0, /* cb_status */
117 0x0, 0x0, /* cb_command */
118 0x0, 0x0, 0x0, 0x0, /* link_addr */
145 int16_t revid; /* -1 matches anything */
150 * Claim various Intel PCI device identifiers for this driver. The
151 * sub-vendor and sub-device field are extensively used to identify
152 * particular variants, but we don't currently differentiate between
155 static struct fxp_ident fxp_ident_table[] = {
156 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" },
157 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" },
158 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
159 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
160 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
161 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
162 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
163 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
164 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
165 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
166 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
167 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
168 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
169 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
170 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
171 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
172 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
173 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
174 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" },
175 { 0x1064, -1, "Intel 82562EZ (ICH6)" },
176 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
177 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
178 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
179 { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" },
180 { 0x1092, -1, "Intel Pro/100 VE Network Connection" },
181 { 0x1093, -1, "Intel Pro/100 VM Network Connection" },
182 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" },
183 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" },
184 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" },
185 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" },
186 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" },
187 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" },
188 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" },
189 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" },
190 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" },
191 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" },
192 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" },
193 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" },
194 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" },
195 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" },
196 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" },
197 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" },
198 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" },
199 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
200 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" },
204 #ifdef FXP_IP_CSUM_WAR
205 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
207 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
210 static int fxp_probe(device_t dev);
211 static int fxp_attach(device_t dev);
212 static int fxp_detach(device_t dev);
213 static int fxp_shutdown(device_t dev);
214 static int fxp_suspend(device_t dev);
215 static int fxp_resume(device_t dev);
217 static void fxp_intr(void *xsc);
218 static void fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp,
219 struct mbuf *m, uint16_t status, int pos);
220 static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp,
221 uint8_t statack, int count);
222 static void fxp_init(void *xsc);
223 static void fxp_init_body(struct fxp_softc *sc);
224 static void fxp_tick(void *xsc);
225 static void fxp_start(struct ifnet *ifp);
226 static void fxp_start_body(struct ifnet *ifp);
227 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head);
228 static void fxp_txeof(struct fxp_softc *sc);
229 static void fxp_stop(struct fxp_softc *sc);
230 static void fxp_release(struct fxp_softc *sc);
231 static int fxp_ioctl(struct ifnet *ifp, u_long command,
233 static void fxp_watchdog(struct fxp_softc *sc);
234 static void fxp_add_rfabuf(struct fxp_softc *sc,
236 static void fxp_discard_rfabuf(struct fxp_softc *sc,
238 static int fxp_new_rfabuf(struct fxp_softc *sc,
240 static int fxp_mc_addrs(struct fxp_softc *sc);
241 static void fxp_mc_setup(struct fxp_softc *sc);
242 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
244 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
246 static void fxp_autosize_eeprom(struct fxp_softc *sc);
247 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
248 int offset, int words);
249 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
250 int offset, int words);
251 static int fxp_ifmedia_upd(struct ifnet *ifp);
252 static void fxp_ifmedia_sts(struct ifnet *ifp,
253 struct ifmediareq *ifmr);
254 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
255 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
256 struct ifmediareq *ifmr);
257 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
258 static void fxp_miibus_writereg(device_t dev, int phy, int reg,
260 static void fxp_load_ucode(struct fxp_softc *sc);
261 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
263 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
264 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
265 static void fxp_scb_wait(struct fxp_softc *sc);
266 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
267 static void fxp_dma_wait(struct fxp_softc *sc,
268 volatile uint16_t *status, bus_dma_tag_t dmat,
271 static device_method_t fxp_methods[] = {
272 /* Device interface */
273 DEVMETHOD(device_probe, fxp_probe),
274 DEVMETHOD(device_attach, fxp_attach),
275 DEVMETHOD(device_detach, fxp_detach),
276 DEVMETHOD(device_shutdown, fxp_shutdown),
277 DEVMETHOD(device_suspend, fxp_suspend),
278 DEVMETHOD(device_resume, fxp_resume),
281 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
282 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
287 static driver_t fxp_driver = {
290 sizeof(struct fxp_softc),
293 static devclass_t fxp_devclass;
295 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0);
296 DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0);
297 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
299 static struct resource_spec fxp_res_spec_mem[] = {
300 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE },
301 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
305 static struct resource_spec fxp_res_spec_io[] = {
306 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE },
307 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
312 * Wait for the previous command to be accepted (but not necessarily
316 fxp_scb_wait(struct fxp_softc *sc)
324 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
327 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL);
328 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1);
329 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
330 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
331 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
332 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
337 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
340 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
341 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
344 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
348 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status,
349 bus_dma_tag_t dmat, bus_dmamap_t map)
353 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD);
354 while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) {
356 bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD);
359 device_printf(sc->dev, "DMA timeout\n");
363 * Return identification string if this device is ours.
366 fxp_probe(device_t dev)
370 struct fxp_ident *ident;
372 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
373 devid = pci_get_device(dev);
374 revid = pci_get_revid(dev);
375 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
376 if (ident->devid == devid &&
377 (ident->revid == revid || ident->revid == -1)) {
378 device_set_desc(dev, ident->name);
379 return (BUS_PROBE_DEFAULT);
387 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
394 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
396 *addr = segs->ds_addr;
400 fxp_attach(device_t dev)
402 struct fxp_softc *sc;
403 struct fxp_cb_tx *tcbp;
408 uint16_t data, myea[ETHER_ADDR_LEN / 2];
409 u_char eaddr[ETHER_ADDR_LEN];
410 int i, pmc, prefer_iomap;
414 sc = device_get_softc(dev);
416 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
418 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
419 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
420 fxp_serial_ifmedia_sts);
422 ifp = sc->ifp = if_alloc(IFT_ETHER);
424 device_printf(dev, "can not if_alloc()\n");
430 * Enable bus mastering.
432 pci_enable_busmaster(dev);
433 val = pci_read_config(dev, PCIR_COMMAND, 2);
436 * Figure out which we should try first - memory mapping or i/o mapping?
437 * We default to memory mapping. Then we accept an override from the
438 * command line. Then we check to see which one is enabled.
441 resource_int_value(device_get_name(dev), device_get_unit(dev),
442 "prefer_iomap", &prefer_iomap);
444 sc->fxp_spec = fxp_res_spec_io;
446 sc->fxp_spec = fxp_res_spec_mem;
448 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
450 if (sc->fxp_spec == fxp_res_spec_mem)
451 sc->fxp_spec = fxp_res_spec_io;
453 sc->fxp_spec = fxp_res_spec_mem;
454 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
457 device_printf(dev, "could not allocate resources\n");
463 device_printf(dev, "using %s space register mapping\n",
464 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O");
468 * Reset to a stable state.
470 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
474 * Find out how large of an SEEPROM we have.
476 fxp_autosize_eeprom(sc);
479 * Find out the chip revision; lump all 82557 revs together.
481 fxp_read_eeprom(sc, &data, 5, 1);
482 if ((data >> 8) == 1)
483 sc->revision = FXP_REV_82557;
485 sc->revision = pci_get_revid(dev);
488 * Check availability of WOL. 82559ER does not support WOL.
490 if (sc->revision >= FXP_REV_82558_A4 &&
491 sc->revision != FXP_REV_82559S_A) {
492 fxp_read_eeprom(sc, &data, 10, 1);
493 if ((data & 0x20) != 0 &&
494 pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0)
495 sc->flags |= FXP_FLAG_WOLCAP;
499 * Determine whether we must use the 503 serial interface.
501 fxp_read_eeprom(sc, &data, 6, 1);
502 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
503 && (data & FXP_PHY_SERIAL_ONLY))
504 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
506 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
507 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
508 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW,
509 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
510 "FXP driver receive interrupt microcode bundling delay");
511 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
512 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
513 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW,
514 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
515 "FXP driver receive interrupt microcode bundle size limit");
516 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
517 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
518 OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
520 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
521 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
522 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0,
523 "FXP flow control disabled");
526 * Pull in device tunables.
528 sc->tunable_int_delay = TUNABLE_INT_DELAY;
529 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
530 sc->tunable_noflow = 1;
531 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
532 "int_delay", &sc->tunable_int_delay);
533 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
534 "bundle_max", &sc->tunable_bundle_max);
535 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
536 "noflow", &sc->tunable_noflow);
540 * Enable workarounds for certain chip revision deficiencies.
542 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
543 * some systems based a normal 82559 design, have a defect where
544 * the chip can cause a PCI protocol violation if it receives
545 * a CU_RESUME command when it is entering the IDLE state. The
546 * workaround is to disable Dynamic Standby Mode, so the chip never
547 * deasserts CLKRUN#, and always remains in an active state.
549 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
551 i = pci_get_device(dev);
552 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
553 sc->revision >= FXP_REV_82559_A0) {
554 fxp_read_eeprom(sc, &data, 10, 1);
555 if (data & 0x02) { /* STB enable */
560 "Disabling dynamic standby mode in EEPROM\n");
562 fxp_write_eeprom(sc, &data, 10, 1);
563 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
565 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
566 fxp_read_eeprom(sc, &data, i, 1);
569 i = (1 << sc->eeprom_size) - 1;
570 cksum = 0xBABA - cksum;
571 fxp_read_eeprom(sc, &data, i, 1);
572 fxp_write_eeprom(sc, &cksum, i, 1);
574 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
578 * If the user elects to continue, try the software
579 * workaround, as it is better than nothing.
581 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
587 * If we are not a 82557 chip, we can enable extended features.
589 if (sc->revision != FXP_REV_82557) {
591 * If MWI is enabled in the PCI configuration, and there
592 * is a valid cacheline size (8 or 16 dwords), then tell
593 * the board to turn on MWI.
595 if (val & PCIM_CMD_MWRICEN &&
596 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
597 sc->flags |= FXP_FLAG_MWI_ENABLE;
599 /* turn on the extended TxCB feature */
600 sc->flags |= FXP_FLAG_EXT_TXCB;
602 /* enable reception of long frames for VLAN */
603 sc->flags |= FXP_FLAG_LONG_PKT_EN;
605 /* a hack to get long VLAN frames on a 82557 */
606 sc->flags |= FXP_FLAG_SAVE_BAD;
609 /* For 82559 or later chips, Rx checksum offload is supported. */
610 if (sc->revision >= FXP_REV_82559_A0)
611 sc->flags |= FXP_FLAG_82559_RXCSUM;
613 * Enable use of extended RFDs and TCBs for 82550
614 * and later chips. Note: we need extended TXCB support
615 * too, but that's already enabled by the code above.
616 * Be careful to do this only on the right devices.
618 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C ||
619 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F
620 || sc->revision == FXP_REV_82551_10) {
621 sc->rfa_size = sizeof (struct fxp_rfa);
622 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
623 sc->flags |= FXP_FLAG_EXT_RFA;
624 /* Use extended RFA instead of 82559 checksum mode. */
625 sc->flags &= ~FXP_FLAG_82559_RXCSUM;
627 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
628 sc->tx_cmd = FXP_CB_COMMAND_XMIT;
632 * Allocate DMA tags and DMA safe memory.
634 sc->maxtxseg = FXP_NTXSEG;
635 sc->maxsegsize = MCLBYTES;
636 if (sc->flags & FXP_FLAG_EXT_RFA) {
638 sc->maxsegsize = FXP_TSO_SEGSIZE;
640 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
641 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
642 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header),
643 sc->maxtxseg, sc->maxsegsize, 0,
644 busdma_lock_mutex, &Giant, &sc->fxp_mtag);
646 device_printf(dev, "could not allocate dma tag\n");
650 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
651 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
652 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
653 busdma_lock_mutex, &Giant, &sc->fxp_stag);
655 device_printf(dev, "could not allocate dma tag\n");
659 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
660 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap);
663 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
664 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0);
666 device_printf(dev, "could not map the stats buffer\n");
670 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
671 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
672 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0,
673 busdma_lock_mutex, &Giant, &sc->cbl_tag);
675 device_printf(dev, "could not allocate dma tag\n");
679 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
680 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map);
684 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
685 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
686 &sc->fxp_desc.cbl_addr, 0);
688 device_printf(dev, "could not map DMA memory\n");
692 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
693 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
694 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
695 busdma_lock_mutex, &Giant, &sc->mcs_tag);
697 device_printf(dev, "could not allocate dma tag\n");
701 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
702 BUS_DMA_NOWAIT, &sc->mcs_map);
705 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
706 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0);
708 device_printf(dev, "can't map the multicast setup command\n");
713 * Pre-allocate the TX DMA maps and setup the pointers to
714 * the TX command blocks.
716 txp = sc->fxp_desc.tx_list;
717 tcbp = sc->fxp_desc.cbl_list;
718 for (i = 0; i < FXP_NTXCB; i++) {
719 txp[i].tx_cb = tcbp + i;
720 error = bus_dmamap_create(sc->fxp_mtag, 0, &txp[i].tx_map);
722 device_printf(dev, "can't create DMA map for TX\n");
726 error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map);
728 device_printf(dev, "can't create spare DMA map\n");
733 * Pre-allocate our receive buffers.
735 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
736 for (i = 0; i < FXP_NRFABUFS; i++) {
737 rxp = &sc->fxp_desc.rx_list[i];
738 error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map);
740 device_printf(dev, "can't create DMA map for RX\n");
743 if (fxp_new_rfabuf(sc, rxp) != 0) {
747 fxp_add_rfabuf(sc, rxp);
753 fxp_read_eeprom(sc, myea, 0, 3);
754 eaddr[0] = myea[0] & 0xff;
755 eaddr[1] = myea[0] >> 8;
756 eaddr[2] = myea[1] & 0xff;
757 eaddr[3] = myea[1] >> 8;
758 eaddr[4] = myea[2] & 0xff;
759 eaddr[5] = myea[2] >> 8;
761 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
762 pci_get_vendor(dev), pci_get_device(dev),
763 pci_get_subvendor(dev), pci_get_subdevice(dev),
765 fxp_read_eeprom(sc, &data, 10, 1);
766 device_printf(dev, "Dynamic Standby mode is %s\n",
767 data & 0x02 ? "enabled" : "disabled");
771 * If this is only a 10Mbps device, then there is no MII, and
772 * the PHY will use a serial interface instead.
774 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
775 * doesn't have a programming interface of any sort. The
776 * media is sensed automatically based on how the link partner
777 * is configured. This is, in essence, manual configuration.
779 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
780 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
781 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
783 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
785 device_printf(dev, "MII without any PHY!\n");
791 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
792 ifp->if_init = fxp_init;
794 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
795 ifp->if_ioctl = fxp_ioctl;
796 ifp->if_start = fxp_start;
798 ifp->if_capabilities = ifp->if_capenable = 0;
800 /* Enable checksum offload/TSO for 82550 or better chips */
801 if (sc->flags & FXP_FLAG_EXT_RFA) {
802 ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO;
803 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4;
804 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4;
807 if (sc->flags & FXP_FLAG_82559_RXCSUM) {
808 ifp->if_capabilities |= IFCAP_RXCSUM;
809 ifp->if_capenable |= IFCAP_RXCSUM;
812 if (sc->flags & FXP_FLAG_WOLCAP) {
813 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
814 ifp->if_capenable |= IFCAP_WOL_MAGIC;
817 #ifdef DEVICE_POLLING
818 /* Inform the world we support polling. */
819 ifp->if_capabilities |= IFCAP_POLLING;
823 * Attach the interface.
825 ether_ifattach(ifp, eaddr);
828 * Tell the upper layer(s) we support long frames.
829 * Must appear after the call to ether_ifattach() because
830 * ether_ifattach() sets ifi_hdrlen to the default value.
832 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
833 ifp->if_capabilities |= IFCAP_VLAN_MTU;
834 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */
835 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) {
836 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING |
838 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING |
843 * Let the system queue as many packets as we have available
846 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1);
847 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1;
848 IFQ_SET_READY(&ifp->if_snd);
851 * Hook our interrupt after all initialization is complete.
853 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE,
854 NULL, fxp_intr, sc, &sc->ih);
856 device_printf(dev, "could not setup irq\n");
857 ether_ifdetach(sc->ifp);
862 * Configure hardware to reject magic frames otherwise
863 * system will hang on recipt of magic frames.
865 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) {
867 /* Clear wakeup events. */
868 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
881 * Release all resources. The softc lock should not be held and the
882 * interrupt should already be torn down.
885 fxp_release(struct fxp_softc *sc)
891 FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
892 KASSERT(sc->ih == NULL,
893 ("fxp_release() called with intr handle still active"));
895 device_delete_child(sc->dev, sc->miibus);
896 bus_generic_detach(sc->dev);
897 ifmedia_removeall(&sc->sc_media);
898 if (sc->fxp_desc.cbl_list) {
899 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
900 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
904 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
905 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
908 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
909 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
911 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res);
913 for (i = 0; i < FXP_NRFABUFS; i++) {
914 rxp = &sc->fxp_desc.rx_list[i];
915 if (rxp->rx_mbuf != NULL) {
916 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
917 BUS_DMASYNC_POSTREAD);
918 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map);
919 m_freem(rxp->rx_mbuf);
921 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map);
923 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map);
924 for (i = 0; i < FXP_NTXCB; i++) {
925 txp = &sc->fxp_desc.tx_list[i];
926 if (txp->tx_mbuf != NULL) {
927 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
928 BUS_DMASYNC_POSTWRITE);
929 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map);
930 m_freem(txp->tx_mbuf);
932 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map);
934 bus_dma_tag_destroy(sc->fxp_mtag);
937 bus_dma_tag_destroy(sc->fxp_stag);
939 bus_dma_tag_destroy(sc->cbl_tag);
941 bus_dma_tag_destroy(sc->mcs_tag);
945 mtx_destroy(&sc->sc_mtx);
952 fxp_detach(device_t dev)
954 struct fxp_softc *sc = device_get_softc(dev);
956 #ifdef DEVICE_POLLING
957 if (sc->ifp->if_capenable & IFCAP_POLLING)
958 ether_poll_deregister(sc->ifp);
962 sc->suspended = 1; /* Do same thing as we do for suspend */
964 * Stop DMA and drop transmit queue, but disable interrupts first.
966 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
969 callout_drain(&sc->stat_ch);
972 * Close down routes etc.
974 ether_ifdetach(sc->ifp);
977 * Unhook interrupt before dropping lock. This is to prevent
978 * races with fxp_intr().
980 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih);
983 /* Release our allocated resources. */
989 * Device shutdown routine. Called at system shutdown after sync. The
990 * main purpose of this routine is to shut off receiver DMA so that
991 * kernel memory doesn't get clobbered during warmboot.
994 fxp_shutdown(device_t dev)
998 * Make sure that DMA is disabled prior to reboot. Not doing
999 * do could allow DMA to corrupt kernel memory during the
1000 * reboot before the driver initializes.
1002 return (fxp_suspend(dev));
1006 * Device suspend routine. Stop the interface and save some PCI
1007 * settings in case the BIOS doesn't restore them properly on
1011 fxp_suspend(device_t dev)
1013 struct fxp_softc *sc = device_get_softc(dev);
1021 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) {
1022 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1023 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1024 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1026 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1027 sc->flags |= FXP_FLAG_WOL;
1028 /* Reconfigure hardware to accept magic frames. */
1031 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1042 * Device resume routine. re-enable busmastering, and restart the interface if
1046 fxp_resume(device_t dev)
1048 struct fxp_softc *sc = device_get_softc(dev);
1049 struct ifnet *ifp = sc->ifp;
1055 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) {
1056 sc->flags &= ~FXP_FLAG_WOL;
1057 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1058 /* Disable PME and clear PME status. */
1059 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1060 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1061 if ((sc->flags & FXP_FLAG_WOLCAP) != 0)
1062 CSR_WRITE_1(sc, FXP_CSR_PMDR,
1063 CSR_READ_1(sc, FXP_CSR_PMDR));
1066 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1069 /* reinitialize interface if necessary */
1070 if (ifp->if_flags & IFF_UP)
1080 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1088 for (x = 1 << (length - 1); x; x >>= 1) {
1090 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1092 reg = FXP_EEPROM_EECS;
1093 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1095 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1097 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1103 * Read from the serial EEPROM. Basically, you manually shift in
1104 * the read opcode (one bit at a time) and then shift in the address,
1105 * and then you shift out the data (all of this one bit at a time).
1106 * The word size is 16 bits, so you have to provide the address for
1107 * every 16 bits of data.
1110 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1115 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1117 * Shift in read opcode.
1119 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1124 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1126 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1128 reg = FXP_EEPROM_EECS;
1129 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1131 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1133 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1135 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1137 if (autosize && reg == 0) {
1138 sc->eeprom_size = data;
1146 reg = FXP_EEPROM_EECS;
1147 for (x = 1 << 15; x; x >>= 1) {
1148 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1150 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1152 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1155 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1162 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data)
1167 * Erase/write enable.
1169 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1170 fxp_eeprom_shiftin(sc, 0x4, 3);
1171 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1172 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1175 * Shift in write opcode, address, data.
1177 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1178 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1179 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1180 fxp_eeprom_shiftin(sc, data, 16);
1181 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1184 * Wait for EEPROM to finish up.
1186 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1188 for (i = 0; i < 1000; i++) {
1189 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1193 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1196 * Erase/write disable.
1198 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1199 fxp_eeprom_shiftin(sc, 0x4, 3);
1200 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1201 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1208 * Figure out EEPROM size.
1210 * 559's can have either 64-word or 256-word EEPROMs, the 558
1211 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1212 * talks about the existance of 16 to 256 word EEPROMs.
1214 * The only known sizes are 64 and 256, where the 256 version is used
1215 * by CardBus cards to store CIS information.
1217 * The address is shifted in msb-to-lsb, and after the last
1218 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1219 * after which follows the actual data. We try to detect this zero, by
1220 * probing the data-out bit in the EEPROM control register just after
1221 * having shifted in a bit. If the bit is zero, we assume we've
1222 * shifted enough address bits. The data-out should be tri-state,
1223 * before this, which should translate to a logical one.
1226 fxp_autosize_eeprom(struct fxp_softc *sc)
1229 /* guess maximum size of 256 words */
1230 sc->eeprom_size = 8;
1233 (void) fxp_eeprom_getword(sc, 0, 1);
1237 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1241 for (i = 0; i < words; i++)
1242 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1246 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1250 for (i = 0; i < words; i++)
1251 fxp_eeprom_putword(sc, offset + i, data[i]);
1255 * Grab the softc lock and call the real fxp_start_body() routine
1258 fxp_start(struct ifnet *ifp)
1260 struct fxp_softc *sc = ifp->if_softc;
1263 fxp_start_body(ifp);
1268 * Start packet transmission on the interface.
1269 * This routine must be called with the softc lock held, and is an
1270 * internal entry point only.
1273 fxp_start_body(struct ifnet *ifp)
1275 struct fxp_softc *sc = ifp->if_softc;
1276 struct mbuf *mb_head;
1279 FXP_LOCK_ASSERT(sc, MA_OWNED);
1282 * See if we need to suspend xmit until the multicast filter
1283 * has been reprogrammed (which can only be done at the head
1284 * of the command chain).
1286 if (sc->need_mcsetup)
1289 if (sc->tx_queued > FXP_NTXCB_HIWAT)
1292 * We're finished if there is nothing more to add to the list or if
1293 * we're all filled up with buffers to transmit.
1294 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1295 * a NOP command when needed.
1298 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1299 sc->tx_queued < FXP_NTXCB - 1) {
1302 * Grab a packet to transmit.
1304 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
1305 if (mb_head == NULL)
1308 if (fxp_encap(sc, &mb_head)) {
1309 if (mb_head == NULL)
1311 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head);
1312 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1316 * Pass packet to bpf if there is a listener.
1318 BPF_MTAP(ifp, mb_head);
1322 * We're finished. If we added to the list, issue a RESUME to get DMA
1323 * going again if suspended.
1326 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1328 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1330 * Set a 5 second timer just in case we don't hear
1331 * from the card again.
1333 sc->watchdog_timer = 5;
1338 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head)
1343 struct fxp_cb_tx *cbp;
1345 bus_dma_segment_t segs[FXP_NTXSEG];
1346 int error, i, nseg, tcp_payload;
1348 FXP_LOCK_ASSERT(sc, MA_OWNED);
1354 * Get pointer to next available tx desc.
1356 txp = sc->fxp_desc.tx_last->tx_next;
1359 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1360 * Ethernet Controller Family Open Source Software
1361 * Developer Manual says:
1362 * Using software parsing is only allowed with legal
1363 * TCP/IP or UDP/IP packets.
1365 * For all other datagrams, hardware parsing must
1367 * Software parsing appears to truncate ICMP and
1368 * fragmented UDP packets that contain one to three
1369 * bytes in the second (and final) mbuf of the packet.
1371 if (sc->flags & FXP_FLAG_EXT_RFA)
1372 txp->tx_cb->ipcb_ip_activation_high =
1373 FXP_IPCB_HARDWAREPARSING_ENABLE;
1377 * Deal with TCP/IP checksum offload. Note that
1378 * in order for TCP checksum offload to work,
1379 * the pseudo header checksum must have already
1380 * been computed and stored in the checksum field
1381 * in the TCP header. The stack should have
1382 * already done this for us.
1384 if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) {
1385 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1386 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1387 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET;
1389 #ifdef FXP_IP_CSUM_WAR
1391 * XXX The 82550 chip appears to have trouble
1392 * dealing with IP header checksums in very small
1393 * datagrams, namely fragments from 1 to 3 bytes
1394 * in size. For example, say you want to transmit
1395 * a UDP packet of 1473 bytes. The packet will be
1396 * fragmented over two IP datagrams, the latter
1397 * containing only one byte of data. The 82550 will
1398 * botch the header checksum on the 1-byte fragment.
1399 * As long as the datagram contains 4 or more bytes
1400 * of data, you're ok.
1402 * The following code attempts to work around this
1403 * problem: if the datagram is less than 38 bytes
1404 * in size (14 bytes ether header, 20 bytes IP header,
1405 * plus 4 bytes of data), we punt and compute the IP
1406 * header checksum by hand. This workaround doesn't
1407 * work very well, however, since it can be fooled
1408 * by things like VLAN tags and IP options that make
1409 * the header sizes/offsets vary.
1412 if (m->m_pkthdr.csum_flags & CSUM_IP) {
1413 if (m->m_pkthdr.len < 38) {
1415 m->m_data += ETHER_HDR_LEN;
1416 ip = mtod(m, struct ip *);
1417 ip->ip_sum = in_cksum(m, ip->ip_hl << 2);
1418 m->m_data -= ETHER_HDR_LEN;
1419 m->m_pkthdr.csum_flags &= ~CSUM_IP;
1421 txp->tx_cb->ipcb_ip_activation_high =
1422 FXP_IPCB_HARDWAREPARSING_ENABLE;
1423 txp->tx_cb->ipcb_ip_schedule |=
1424 FXP_IPCB_IP_CHECKSUM_ENABLE;
1430 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1432 * 82550/82551 requires ethernet/IP/TCP headers must be
1433 * contained in the first active transmit buffer.
1435 struct ether_header *eh;
1437 uint32_t ip_off, poff;
1439 if (M_WRITABLE(*m_head) == 0) {
1440 /* Get a writable copy. */
1441 m = m_dup(*m_head, M_DONTWAIT);
1449 ip_off = sizeof(struct ether_header);
1450 m = m_pullup(*m_head, ip_off);
1455 eh = mtod(m, struct ether_header *);
1456 /* Check the existence of VLAN tag. */
1457 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1458 ip_off = sizeof(struct ether_vlan_header);
1459 m = m_pullup(m, ip_off);
1465 m = m_pullup(m, ip_off + sizeof(struct ip));
1470 ip = (struct ip *)(mtod(m, char *) + ip_off);
1471 poff = ip_off + (ip->ip_hl << 2);
1472 m = m_pullup(m, poff + sizeof(struct tcphdr));
1477 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1478 m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off);
1485 * Since 82550/82551 doesn't modify IP length and pseudo
1486 * checksum in the first frame driver should compute it.
1489 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) +
1490 (tcp->th_off << 2));
1491 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1492 htons(IPPROTO_TCP + (tcp->th_off << 2) +
1493 m->m_pkthdr.tso_segsz));
1494 /* Compute total TCP payload. */
1495 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2);
1496 tcp_payload -= tcp->th_off << 2;
1500 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map, *m_head,
1502 if (error == EFBIG) {
1503 m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg);
1510 error = bus_dmamap_load_mbuf_sg(sc->fxp_mtag, txp->tx_map,
1511 *m_head, segs, &nseg, 0);
1517 } else if (error != 0)
1525 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments"));
1526 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE);
1529 for (i = 0; i < nseg; i++) {
1531 * If this is an 82550/82551, then we're using extended
1532 * TxCBs _and_ we're using checksum offload. This means
1533 * that the TxCB is really an IPCB. One major difference
1534 * between the two is that with plain extended TxCBs,
1535 * the bottom half of the TxCB contains two entries from
1536 * the TBD array, whereas IPCBs contain just one entry:
1537 * one entry (8 bytes) has been sacrificed for the TCP/IP
1538 * checksum offload control bits. So to make things work
1539 * right, we have to start filling in the TBD array
1540 * starting from a different place depending on whether
1541 * the chip is an 82550/82551 or not.
1543 if (sc->flags & FXP_FLAG_EXT_RFA) {
1544 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1545 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1547 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1548 cbp->tbd[i].tb_size = htole32(segs[i].ds_len);
1551 if (sc->flags & FXP_FLAG_EXT_RFA) {
1552 /* Configure dynamic TBD for 82550/82551. */
1553 cbp->tbd_number = 0xFF;
1554 cbp->tbd[nseg].tb_size |= htole32(0x8000);
1556 cbp->tbd_number = nseg;
1557 /* Configure TSO. */
1558 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1559 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16);
1560 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16);
1561 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE |
1562 FXP_IPCB_IP_CHECKSUM_ENABLE |
1563 FXP_IPCB_TCP_PACKET |
1564 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1566 /* Configure VLAN hardware tag insertion. */
1567 if ((m->m_flags & M_VLANTAG) != 0) {
1568 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag);
1569 txp->tx_cb->ipcb_ip_activation_high |=
1570 FXP_IPCB_INSERTVLAN_ENABLE;
1574 txp->tx_cb->cb_status = 0;
1575 txp->tx_cb->byte_count = 0;
1576 if (sc->tx_queued != FXP_CXINT_THRESH - 1)
1577 txp->tx_cb->cb_command =
1578 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1581 txp->tx_cb->cb_command =
1582 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1583 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1584 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0)
1585 txp->tx_cb->tx_threshold = tx_threshold;
1588 * Advance the end of list forward.
1593 * On platforms which can't access memory in 16-bit
1594 * granularities, we must prevent the card from DMA'ing
1595 * up the status while we update the command field.
1596 * This could cause us to overwrite the completion status.
1597 * XXX This is probably bogus and we're _not_ looking
1598 * for atomicity here.
1600 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command,
1601 htole16(FXP_CB_COMMAND_S));
1603 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S);
1604 #endif /*__alpha__*/
1605 sc->fxp_desc.tx_last = txp;
1608 * Advance the beginning of the list forward if there are
1609 * no other packets queued (when nothing is queued, tx_first
1610 * sits on the last TxCB that was sent out).
1612 if (sc->tx_queued == 0)
1613 sc->fxp_desc.tx_first = txp;
1620 #ifdef DEVICE_POLLING
1621 static poll_handler_t fxp_poll;
1624 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1626 struct fxp_softc *sc = ifp->if_softc;
1630 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1635 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1637 if (cmd == POLL_AND_CHECK_STATUS) {
1640 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1641 if (tmp == 0xff || tmp == 0) {
1643 return; /* nothing to do */
1646 /* ack what we can */
1648 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1651 fxp_intr_body(sc, ifp, statack, count);
1654 #endif /* DEVICE_POLLING */
1657 * Process interface interrupts.
1662 struct fxp_softc *sc = xsc;
1663 struct ifnet *ifp = sc->ifp;
1667 if (sc->suspended) {
1672 #ifdef DEVICE_POLLING
1673 if (ifp->if_capenable & IFCAP_POLLING) {
1678 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1680 * It should not be possible to have all bits set; the
1681 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1682 * all bits are set, this may indicate that the card has
1683 * been physically ejected, so ignore it.
1685 if (statack == 0xff) {
1691 * First ACK all the interrupts in this pass.
1693 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1694 fxp_intr_body(sc, ifp, statack, -1);
1700 fxp_txeof(struct fxp_softc *sc)
1706 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD);
1707 for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1708 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1709 txp = txp->tx_next) {
1710 if (txp->tx_mbuf != NULL) {
1711 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map,
1712 BUS_DMASYNC_POSTWRITE);
1713 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map);
1714 m_freem(txp->tx_mbuf);
1715 txp->tx_mbuf = NULL;
1716 /* clear this to reset csum offload bits */
1717 txp->tx_cb->tbd[0].tb_addr = 0;
1720 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1722 sc->fxp_desc.tx_first = txp;
1723 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
1724 if (sc->tx_queued == 0) {
1725 sc->watchdog_timer = 0;
1726 if (sc->need_mcsetup)
1732 fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m,
1733 uint16_t status, int pos)
1735 struct ether_header *eh;
1738 int32_t hlen, len, pktlen, temp32;
1739 uint16_t csum, *opts;
1741 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) {
1742 if ((status & FXP_RFA_STATUS_PARSE) != 0) {
1743 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1744 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1745 if (status & FXP_RFDX_CS_IP_CSUM_VALID)
1746 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1747 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1748 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1749 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1751 m->m_pkthdr.csum_data = 0xffff;
1757 pktlen = m->m_pkthdr.len;
1758 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
1760 eh = mtod(m, struct ether_header *);
1761 if (eh->ether_type != htons(ETHERTYPE_IP))
1763 ip = (struct ip *)(eh + 1);
1764 if (ip->ip_v != IPVERSION)
1767 hlen = ip->ip_hl << 2;
1768 pktlen -= sizeof(struct ether_header);
1769 if (hlen < sizeof(struct ip))
1771 if (ntohs(ip->ip_len) < hlen)
1773 if (ntohs(ip->ip_len) != pktlen)
1775 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1776 return; /* can't handle fragmented packet */
1780 if (pktlen < (hlen + sizeof(struct tcphdr)))
1784 if (pktlen < (hlen + sizeof(struct udphdr)))
1786 uh = (struct udphdr *)((caddr_t)ip + hlen);
1787 if (uh->uh_sum == 0)
1788 return; /* no checksum */
1793 /* Extract computed checksum. */
1794 csum = be16dec(mtod(m, char *) + pos);
1795 /* checksum fixup for IP options */
1796 len = hlen - sizeof(struct ip);
1798 opts = (uint16_t *)(ip + 1);
1799 for (; len > 0; len -= sizeof(uint16_t), opts++) {
1800 temp32 = csum - *opts;
1801 temp32 = (temp32 >> 16) + (temp32 & 65535);
1802 csum = temp32 & 65535;
1805 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1806 m->m_pkthdr.csum_data = csum;
1810 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack,
1815 struct fxp_rfa *rfa;
1816 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1819 FXP_LOCK_ASSERT(sc, MA_OWNED);
1822 #ifdef DEVICE_POLLING
1823 /* Pick up a deferred RNR condition if `count' ran out last time. */
1824 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1825 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1831 * Free any finished transmit mbuf chains.
1833 * Handle the CNA event likt a CXTNO event. It used to
1834 * be that this event (control unit not ready) was not
1835 * encountered, but it is now with the SMPng modifications.
1836 * The exact sequence of events that occur when the interface
1837 * is brought up are different now, and if this event
1838 * goes unhandled, the configuration/rxfilter setup sequence
1839 * can stall for several seconds. The result is that no
1840 * packets go out onto the wire for about 5 to 10 seconds
1841 * after the interface is ifconfig'ed for the first time.
1843 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA))
1847 * Try to start more packets transmitting.
1849 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1850 fxp_start_body(ifp);
1853 * Just return if nothing happened on the receive side.
1855 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1859 * Process receiver interrupts. If a no-resource (RNR)
1860 * condition exists, get whatever packets we can and
1861 * re-start the receiver.
1863 * When using polling, we do not process the list to completion,
1864 * so when we get an RNR interrupt we must defer the restart
1865 * until we hit the last buffer with the C bit set.
1866 * If we run out of cycles and rfa_headm has the C bit set,
1867 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1868 * that the info will be used in the subsequent polling cycle.
1871 rxp = sc->fxp_desc.rx_head;
1873 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1874 RFA_ALIGNMENT_FUDGE);
1875 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
1876 BUS_DMASYNC_POSTREAD);
1878 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1879 if (count >= 0 && count-- == 0) {
1881 /* Defer RNR processing until the next time. */
1882 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1887 #endif /* DEVICE_POLLING */
1889 status = le16toh(rfa->rfa_status);
1890 if ((status & FXP_RFA_STATUS_C) == 0)
1894 * Advance head forward.
1896 sc->fxp_desc.rx_head = rxp->rx_next;
1899 * Add a new buffer to the receive chain.
1900 * If this fails, the old buffer is recycled
1903 if (fxp_new_rfabuf(sc, rxp) == 0) {
1907 * Fetch packet length (the top 2 bits of
1908 * actual_size are flags set by the controller
1909 * upon completion), and drop the packet in case
1910 * of bogus length or CRC errors.
1912 total_len = le16toh(rfa->actual_size) & 0x3fff;
1913 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
1914 (ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1915 /* Adjust for appended checksum bytes. */
1918 if (total_len < sizeof(struct ether_header) ||
1919 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1920 sc->rfa_size || status & FXP_RFA_STATUS_CRC) {
1925 m->m_pkthdr.len = m->m_len = total_len;
1926 m->m_pkthdr.rcvif = ifp;
1928 /* Do IP checksum checking. */
1929 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1930 fxp_rxcsum(sc, ifp, m, status, total_len);
1931 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
1932 (status & FXP_RFA_STATUS_VLAN) != 0) {
1933 m->m_pkthdr.ether_vtag =
1934 ntohs(rfa->rfax_vlan_id);
1935 m->m_flags |= M_VLANTAG;
1938 * Drop locks before calling if_input() since it
1939 * may re-enter fxp_start() in the netisr case.
1940 * This would result in a lock reversal. Better
1941 * performance might be obtained by chaining all
1942 * packets received, dropping the lock, and then
1943 * calling if_input() on each one.
1946 (*ifp->if_input)(ifp, m);
1949 /* Reuse RFA and loaded DMA map. */
1951 fxp_discard_rfabuf(sc, rxp);
1953 fxp_add_rfabuf(sc, rxp);
1957 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1958 sc->fxp_desc.rx_head->rx_addr);
1959 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1964 * Update packet in/out/collision statistics. The i82557 doesn't
1965 * allow you to access these counters without doing a fairly
1966 * expensive DMA to get _all_ of the statistics it maintains, so
1967 * we do this operation here only once per second. The statistics
1968 * counters in the kernel are updated from the previous dump-stats
1969 * DMA and then a new dump-stats DMA is started. The on-chip
1970 * counters are zeroed when the DMA completes. If we can't start
1971 * the DMA immediately, we don't wait - we just prepare to read
1972 * them again next time.
1977 struct fxp_softc *sc = xsc;
1978 struct ifnet *ifp = sc->ifp;
1979 struct fxp_stats *sp = sc->fxp_stats;
1981 FXP_LOCK_ASSERT(sc, MA_OWNED);
1982 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD);
1983 ifp->if_opackets += le32toh(sp->tx_good);
1984 ifp->if_collisions += le32toh(sp->tx_total_collisions);
1986 ifp->if_ipackets += le32toh(sp->rx_good);
1987 sc->rx_idle_secs = 0;
1990 * Receiver's been idle for another second.
1995 le32toh(sp->rx_crc_errors) +
1996 le32toh(sp->rx_alignment_errors) +
1997 le32toh(sp->rx_rnr_errors) +
1998 le32toh(sp->rx_overrun_errors);
2000 * If any transmit underruns occured, bump up the transmit
2001 * threshold by another 512 bytes (64 * 8).
2003 if (sp->tx_underruns) {
2004 ifp->if_oerrors += le32toh(sp->tx_underruns);
2005 if (tx_threshold < 192)
2010 * Release any xmit buffers that have completed DMA. This isn't
2011 * strictly necessary to do here, but it's advantagous for mbufs
2012 * with external storage to be released in a timely manner rather
2013 * than being defered for a potentially long time. This limits
2014 * the delay to a maximum of one second.
2019 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
2020 * then assume the receiver has locked up and attempt to clear
2021 * the condition by reprogramming the multicast filter. This is
2022 * a work-around for a bug in the 82557 where the receiver locks
2023 * up if it gets certain types of garbage in the syncronization
2024 * bits prior to the packet header. This bug is supposed to only
2025 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
2026 * mode as well (perhaps due to a 10/100 speed transition).
2028 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
2029 sc->rx_idle_secs = 0;
2033 * If there is no pending command, start another stats
2034 * dump. Otherwise punt for now.
2036 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2038 * Start another stats dump.
2040 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2041 BUS_DMASYNC_PREREAD);
2042 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
2045 * A previous command is still waiting to be accepted.
2046 * Just zero our copy of the stats and wait for the
2047 * next timer event to update them.
2050 sp->tx_underruns = 0;
2051 sp->tx_total_collisions = 0;
2054 sp->rx_crc_errors = 0;
2055 sp->rx_alignment_errors = 0;
2056 sp->rx_rnr_errors = 0;
2057 sp->rx_overrun_errors = 0;
2059 if (sc->miibus != NULL)
2060 mii_tick(device_get_softc(sc->miibus));
2063 * Check that chip hasn't hung.
2068 * Schedule another timeout one second from now.
2070 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2074 * Stop the interface. Cancels the statistics updater and resets
2078 fxp_stop(struct fxp_softc *sc)
2080 struct ifnet *ifp = sc->ifp;
2084 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2085 sc->watchdog_timer = 0;
2088 * Cancel stats updater.
2090 callout_stop(&sc->stat_ch);
2093 * Preserve PCI configuration, configure, IA/multicast
2094 * setup and put RU and CU into idle state.
2096 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
2098 /* Disable interrupts. */
2099 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2102 * Release any xmit buffers.
2104 txp = sc->fxp_desc.tx_list;
2106 for (i = 0; i < FXP_NTXCB; i++) {
2107 if (txp[i].tx_mbuf != NULL) {
2108 bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map,
2109 BUS_DMASYNC_POSTWRITE);
2110 bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map);
2111 m_freem(txp[i].tx_mbuf);
2112 txp[i].tx_mbuf = NULL;
2113 /* clear this to reset csum offload bits */
2114 txp[i].tx_cb->tbd[0].tb_addr = 0;
2118 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2123 * Watchdog/transmission transmit timeout handler. Called when a
2124 * transmission is started on the interface, but no interrupt is
2125 * received before the timeout. This usually indicates that the
2126 * card has wedged for some reason.
2129 fxp_watchdog(struct fxp_softc *sc)
2132 FXP_LOCK_ASSERT(sc, MA_OWNED);
2134 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
2137 device_printf(sc->dev, "device timeout\n");
2138 sc->ifp->if_oerrors++;
2144 * Acquire locks and then call the real initialization function. This
2145 * is necessary because ether_ioctl() calls if_init() and this would
2146 * result in mutex recursion if the mutex was held.
2151 struct fxp_softc *sc = xsc;
2159 * Perform device initialization. This routine must be called with the
2163 fxp_init_body(struct fxp_softc *sc)
2165 struct ifnet *ifp = sc->ifp;
2166 struct fxp_cb_config *cbp;
2167 struct fxp_cb_ias *cb_ias;
2168 struct fxp_cb_tx *tcbp;
2170 struct fxp_cb_mcs *mcsp;
2173 FXP_LOCK_ASSERT(sc, MA_OWNED);
2175 * Cancel any pending I/O
2180 * Issue software reset, which also unloads the microcode.
2182 sc->flags &= ~FXP_FLAG_UCODE;
2183 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
2186 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
2189 * Initialize base of CBL and RFA memory. Loading with zero
2190 * sets it up for regular linear addressing.
2192 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2193 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2196 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2199 * Initialize base of dump-stats buffer.
2202 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD);
2203 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2204 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2207 * Attempt to load microcode if requested.
2209 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
2213 * Initialize the multicast address list.
2215 if (fxp_mc_addrs(sc)) {
2217 mcsp->cb_status = 0;
2219 htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
2220 mcsp->link_addr = 0xffffffff;
2222 * Start the multicast setup command.
2225 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE);
2226 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
2227 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2228 /* ...and wait for it to complete. */
2229 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
2230 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
2231 BUS_DMASYNC_POSTWRITE);
2235 * We temporarily use memory that contains the TxCB list to
2236 * construct the config CB. The TxCB list memory is rebuilt
2239 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2242 * This bcopy is kind of disgusting, but there are a bunch of must be
2243 * zero and must be one bits in this structure and this is the easiest
2244 * way to initialize them all to proper values.
2246 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2249 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG |
2251 cbp->link_addr = 0xffffffff; /* (no) next command */
2252 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2253 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
2254 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2255 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2256 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2257 cbp->type_enable = 0; /* actually reserved */
2258 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2259 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2260 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2261 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2262 cbp->dma_mbce = 0; /* (disable) dma max counters */
2263 cbp->late_scb = 0; /* (don't) defer SCB update */
2264 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
2265 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2266 cbp->ci_int = 1; /* interrupt on CU idle */
2267 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2268 cbp->ext_stats_dis = 1; /* disable extended counters */
2269 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2270 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2271 cbp->disc_short_rx = !prm; /* discard short packets */
2272 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
2273 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2274 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2275 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2276 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2277 cbp->csma_dis = 0; /* (don't) disable link */
2278 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
2279 (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0;
2280 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2281 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2282 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2283 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2284 cbp->nsai = 1; /* (don't) disable source addr insert */
2285 cbp->preamble_length = 2; /* (7 byte) preamble */
2286 cbp->loopback = 0; /* (don't) loopback */
2287 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2288 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2289 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
2290 cbp->promiscuous = prm; /* promiscuous mode */
2291 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2292 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2293 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2294 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2295 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2297 cbp->stripping = !prm; /* truncate rx packet to byte count */
2298 cbp->padding = 1; /* (do) pad short tx packets */
2299 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2300 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2301 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2302 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1;
2303 cbp->force_fdx = 0; /* (don't) force full duplex */
2304 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
2305 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2306 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
2307 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2308 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 &&
2309 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0;
2311 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) {
2313 * The 82557 has no hardware flow control, the values
2314 * below are the defaults for the chip.
2316 cbp->fc_delay_lsb = 0;
2317 cbp->fc_delay_msb = 0x40;
2318 cbp->pri_fc_thresh = 3;
2320 cbp->rx_fc_restop = 0;
2321 cbp->rx_fc_restart = 0;
2323 cbp->pri_fc_loc = 1;
2325 cbp->fc_delay_lsb = 0x1f;
2326 cbp->fc_delay_msb = 0x01;
2327 cbp->pri_fc_thresh = 3;
2328 cbp->tx_fc_dis = 0; /* enable transmit FC */
2329 cbp->rx_fc_restop = 1; /* enable FC restop frames */
2330 cbp->rx_fc_restart = 1; /* enable FC restart frames */
2331 cbp->fc_filter = !prm; /* drop FC frames to host */
2332 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
2336 * Start the config command/DMA.
2339 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2340 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2341 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2342 /* ...and wait for it to complete. */
2343 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2344 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2347 * Now initialize the station address. Temporarily use the TxCB
2348 * memory area like we did above for the config CB.
2350 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2351 cb_ias->cb_status = 0;
2352 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2353 cb_ias->link_addr = 0xffffffff;
2354 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN);
2357 * Start the IAS (Individual Address Setup) command/DMA.
2360 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2361 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2362 /* ...and wait for it to complete. */
2363 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2364 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
2367 * Initialize transmit control block (TxCB) list.
2369 txp = sc->fxp_desc.tx_list;
2370 tcbp = sc->fxp_desc.cbl_list;
2371 bzero(tcbp, FXP_TXCB_SZ);
2372 for (i = 0; i < FXP_NTXCB; i++) {
2373 txp[i].tx_mbuf = NULL;
2374 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2375 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2376 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2377 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2378 if (sc->flags & FXP_FLAG_EXT_TXCB)
2379 tcbp[i].tbd_array_addr =
2380 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2382 tcbp[i].tbd_array_addr =
2383 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2384 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2387 * Set the suspend flag on the first TxCB and start the control
2388 * unit. It will execute the NOP and then suspend.
2390 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2391 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2392 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2396 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2399 * Initialize receiver buffer area - RFA.
2402 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2403 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2406 * Set current media.
2408 if (sc->miibus != NULL)
2409 mii_mediachg(device_get_softc(sc->miibus));
2411 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2412 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2415 * Enable interrupts.
2417 #ifdef DEVICE_POLLING
2419 * ... but only do that if we are not polling. And because (presumably)
2420 * the default is interrupts on, we need to disable them explicitly!
2422 if (ifp->if_capenable & IFCAP_POLLING )
2423 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2425 #endif /* DEVICE_POLLING */
2426 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2429 * Start stats updater.
2431 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2435 fxp_serial_ifmedia_upd(struct ifnet *ifp)
2442 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2445 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2449 * Change media according to request.
2452 fxp_ifmedia_upd(struct ifnet *ifp)
2454 struct fxp_softc *sc = ifp->if_softc;
2455 struct mii_data *mii;
2457 mii = device_get_softc(sc->miibus);
2459 if (mii->mii_instance) {
2460 struct mii_softc *miisc;
2461 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2462 mii_phy_reset(miisc);
2470 * Notify the world which media we're using.
2473 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2475 struct fxp_softc *sc = ifp->if_softc;
2476 struct mii_data *mii;
2478 mii = device_get_softc(sc->miibus);
2481 ifmr->ifm_active = mii->mii_media_active;
2482 ifmr->ifm_status = mii->mii_media_status;
2484 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T &&
2485 sc->flags & FXP_FLAG_CU_RESUME_BUG)
2486 sc->cu_resume_bug = 1;
2488 sc->cu_resume_bug = 0;
2493 * Add a buffer to the end of the RFA buffer list.
2494 * Return 0 if successful, 1 for failure. A failure results in
2495 * reusing the RFA buffer.
2496 * The RFA struct is stuck at the beginning of mbuf cluster and the
2497 * data pointer is fixed up to point just past it.
2500 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2503 struct fxp_rfa *rfa;
2504 bus_dmamap_t tmp_map;
2507 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2512 * Move the data pointer up so that the incoming data packet
2513 * will be 32-bit aligned.
2515 m->m_data += RFA_ALIGNMENT_FUDGE;
2518 * Get a pointer to the base of the mbuf cluster and move
2519 * data start past it.
2521 rfa = mtod(m, struct fxp_rfa *);
2522 m->m_data += sc->rfa_size;
2523 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2525 rfa->rfa_status = 0;
2526 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2527 rfa->actual_size = 0;
2528 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE -
2532 * Initialize the rest of the RFA. Note that since the RFA
2533 * is misaligned, we cannot store values directly. We're thus
2534 * using the le32enc() function which handles endianness and
2535 * is also alignment-safe.
2537 le32enc(&rfa->link_addr, 0xffffffff);
2538 le32enc(&rfa->rbd_addr, 0xffffffff);
2540 /* Map the RFA into DMA memory. */
2541 error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa,
2542 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2549 if (rxp->rx_mbuf != NULL)
2550 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map);
2551 tmp_map = sc->spare_map;
2552 sc->spare_map = rxp->rx_map;
2553 rxp->rx_map = tmp_map;
2556 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
2557 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2562 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2564 struct fxp_rfa *p_rfa;
2565 struct fxp_rx *p_rx;
2568 * If there are other buffers already on the list, attach this
2569 * one to the end by fixing up the tail to point to this one.
2571 if (sc->fxp_desc.rx_head != NULL) {
2572 p_rx = sc->fxp_desc.rx_tail;
2573 p_rfa = (struct fxp_rfa *)
2574 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2575 p_rx->rx_next = rxp;
2576 le32enc(&p_rfa->link_addr, rxp->rx_addr);
2577 p_rfa->rfa_control = 0;
2578 bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map,
2579 BUS_DMASYNC_PREWRITE);
2581 rxp->rx_next = NULL;
2582 sc->fxp_desc.rx_head = rxp;
2584 sc->fxp_desc.rx_tail = rxp;
2588 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2591 struct fxp_rfa *rfa;
2594 m->m_data = m->m_ext.ext_buf;
2596 * Move the data pointer up so that the incoming data packet
2597 * will be 32-bit aligned.
2599 m->m_data += RFA_ALIGNMENT_FUDGE;
2602 * Get a pointer to the base of the mbuf cluster and move
2603 * data start past it.
2605 rfa = mtod(m, struct fxp_rfa *);
2606 m->m_data += sc->rfa_size;
2607 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2609 rfa->rfa_status = 0;
2610 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2611 rfa->actual_size = 0;
2614 * Initialize the rest of the RFA. Note that since the RFA
2615 * is misaligned, we cannot store values directly. We're thus
2616 * using the le32enc() function which handles endianness and
2617 * is also alignment-safe.
2619 le32enc(&rfa->link_addr, 0xffffffff);
2620 le32enc(&rfa->rbd_addr, 0xffffffff);
2622 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map,
2623 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2627 fxp_miibus_readreg(device_t dev, int phy, int reg)
2629 struct fxp_softc *sc = device_get_softc(dev);
2633 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2634 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2636 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2641 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2643 return (value & 0xffff);
2647 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2649 struct fxp_softc *sc = device_get_softc(dev);
2652 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2653 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2656 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2661 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2665 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2667 struct fxp_softc *sc = ifp->if_softc;
2668 struct ifreq *ifr = (struct ifreq *)data;
2669 struct mii_data *mii;
2670 int flag, mask, error = 0, reinit;
2675 if (ifp->if_flags & IFF_ALLMULTI)
2676 sc->flags |= FXP_FLAG_ALL_MCAST;
2678 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2681 * If interface is marked up and not running, then start it.
2682 * If it is marked down and running, stop it.
2683 * XXX If it's up then re-initialize it. This is so flags
2684 * such as IFF_PROMISC are handled.
2686 if (ifp->if_flags & IFF_UP) {
2689 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2698 if (ifp->if_flags & IFF_ALLMULTI)
2699 sc->flags |= FXP_FLAG_ALL_MCAST;
2701 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2703 * Multicast list has changed; set the hardware filter
2706 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2709 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2710 * again rather than else {}.
2712 if (sc->flags & FXP_FLAG_ALL_MCAST)
2720 if (sc->miibus != NULL) {
2721 mii = device_get_softc(sc->miibus);
2722 error = ifmedia_ioctl(ifp, ifr,
2723 &mii->mii_media, command);
2725 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2731 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
2732 #ifdef DEVICE_POLLING
2733 if (mask & IFCAP_POLLING) {
2734 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2735 error = ether_poll_register(fxp_poll, ifp);
2739 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
2740 FXP_SCB_INTR_DISABLE);
2741 ifp->if_capenable |= IFCAP_POLLING;
2744 error = ether_poll_deregister(ifp);
2745 /* Enable interrupts in any case */
2747 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2748 ifp->if_capenable &= ~IFCAP_POLLING;
2754 if ((mask & IFCAP_TXCSUM) != 0 &&
2755 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2756 ifp->if_capenable ^= IFCAP_TXCSUM;
2757 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2758 ifp->if_hwassist |= FXP_CSUM_FEATURES;
2760 ifp->if_hwassist &= ~FXP_CSUM_FEATURES;
2762 if ((mask & IFCAP_RXCSUM) != 0 &&
2763 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
2764 ifp->if_capenable ^= IFCAP_RXCSUM;
2765 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0)
2768 if ((mask & IFCAP_TSO4) != 0 &&
2769 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2770 ifp->if_capenable ^= IFCAP_TSO4;
2771 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
2772 ifp->if_hwassist |= CSUM_TSO;
2774 ifp->if_hwassist &= ~CSUM_TSO;
2776 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2777 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2778 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2779 if ((mask & IFCAP_VLAN_MTU) != 0 &&
2780 (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) {
2781 ifp->if_capenable ^= IFCAP_VLAN_MTU;
2782 if (sc->revision != FXP_REV_82557)
2783 flag = FXP_FLAG_LONG_PKT_EN;
2784 else /* a hack to get long frames on the old chip */
2785 flag = FXP_FLAG_SAVE_BAD;
2787 if (ifp->if_flags & IFF_UP)
2790 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2791 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2792 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2795 if (reinit > 0 && ifp->if_flags & IFF_UP)
2798 VLAN_CAPABILITIES(ifp);
2802 error = ether_ioctl(ifp, command, data);
2808 * Fill in the multicast address list and return number of entries.
2811 fxp_mc_addrs(struct fxp_softc *sc)
2813 struct fxp_cb_mcs *mcsp = sc->mcsp;
2814 struct ifnet *ifp = sc->ifp;
2815 struct ifmultiaddr *ifma;
2819 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2821 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2822 if (ifma->ifma_addr->sa_family != AF_LINK)
2824 if (nmcasts >= MAXMCADDR) {
2825 sc->flags |= FXP_FLAG_ALL_MCAST;
2829 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2830 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN);
2833 IF_ADDR_UNLOCK(ifp);
2835 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
2840 * Program the multicast filter.
2842 * We have an artificial restriction that the multicast setup command
2843 * must be the first command in the chain, so we take steps to ensure
2844 * this. By requiring this, it allows us to keep up the performance of
2845 * the pre-initialized command ring (esp. link pointers) by not actually
2846 * inserting the mcsetup command in the ring - i.e. its link pointer
2847 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2848 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2849 * lead into the regular TxCB ring when it completes.
2851 * This function must be called at splimp.
2854 fxp_mc_setup(struct fxp_softc *sc)
2856 struct fxp_cb_mcs *mcsp = sc->mcsp;
2860 FXP_LOCK_ASSERT(sc, MA_OWNED);
2862 * If there are queued commands, we must wait until they are all
2863 * completed. If we are already waiting, then add a NOP command
2864 * with interrupt option so that we're notified when all commands
2865 * have been completed - fxp_start() ensures that no additional
2866 * TX commands will be added when need_mcsetup is true.
2868 if (sc->tx_queued) {
2870 * need_mcsetup will be true if we are already waiting for the
2871 * NOP command to be completed (see below). In this case, bail.
2873 if (sc->need_mcsetup)
2875 sc->need_mcsetup = 1;
2878 * Add a NOP command with interrupt so that we are notified
2879 * when all TX commands have been processed.
2881 txp = sc->fxp_desc.tx_last->tx_next;
2882 txp->tx_mbuf = NULL;
2883 txp->tx_cb->cb_status = 0;
2884 txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP |
2885 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
2887 * Advance the end of list forward.
2889 sc->fxp_desc.tx_last->tx_cb->cb_command &=
2890 htole16(~FXP_CB_COMMAND_S);
2891 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
2892 sc->fxp_desc.tx_last = txp;
2895 * Issue a resume in case the CU has just suspended.
2898 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2900 * Set a 5 second timer just in case we don't hear from the
2903 sc->watchdog_timer = 5;
2907 sc->need_mcsetup = 0;
2910 * Initialize multicast setup descriptor.
2912 mcsp->cb_status = 0;
2913 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS |
2914 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
2915 mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr);
2916 txp = &sc->fxp_desc.mcs_tx;
2917 txp->tx_mbuf = NULL;
2918 txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp;
2919 txp->tx_next = sc->fxp_desc.tx_list;
2920 (void) fxp_mc_addrs(sc);
2921 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2925 * Wait until command unit is not active. This should never
2926 * be the case when nothing is queued, but make sure anyway.
2929 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2930 FXP_SCB_CUS_ACTIVE && --count)
2933 device_printf(sc->dev, "command queue timeout\n");
2938 * Start the multicast setup command.
2941 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE);
2942 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
2943 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2945 sc->watchdog_timer = 2;
2949 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2950 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2951 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2952 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2953 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2954 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2955 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE;
2957 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t)
2963 u_short int_delay_offset;
2964 u_short bundle_max_offset;
2966 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2967 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2968 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2969 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2970 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2971 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2972 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2973 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2974 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2975 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2976 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e),
2977 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
2978 { 0, NULL, 0, 0, 0 }
2982 fxp_load_ucode(struct fxp_softc *sc)
2985 struct fxp_cb_ucode *cbp;
2988 for (uc = ucode_table; uc->ucode != NULL; uc++)
2989 if (sc->revision == uc->revision)
2991 if (uc->ucode == NULL)
2993 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
2995 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
2996 cbp->link_addr = 0xffffffff; /* (no) next command */
2997 for (i = 0; i < uc->length; i++)
2998 cbp->ucode[i] = htole32(uc->ucode[i]);
2999 if (uc->int_delay_offset)
3000 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] =
3001 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
3002 if (uc->bundle_max_offset)
3003 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] =
3004 htole16(sc->tunable_bundle_max);
3006 * Download the ucode to the chip.
3009 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE);
3010 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
3011 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3012 /* ...and wait for it to complete. */
3013 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
3014 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
3015 device_printf(sc->dev,
3016 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
3017 sc->tunable_int_delay,
3018 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
3019 sc->flags |= FXP_FLAG_UCODE;
3023 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3027 value = *(int *)arg1;
3028 error = sysctl_handle_int(oidp, &value, 0, req);
3029 if (error || !req->newptr)
3031 if (value < low || value > high)
3033 *(int *)arg1 = value;
3038 * Interrupt delay is expressed in microseconds, a multiplier is used
3039 * to convert this to the appropriate clock ticks before using.
3042 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
3044 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
3048 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
3050 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));