sys/dev/hwpmc/hwpmc_amd.c

   1 /*-
   2  * Copyright (c) 2003-2005 Joseph Koshy
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 /* Support for the AMD K7 and later processors */
  32
  33 #include <sys/param.h>
  34 #include <sys/lock.h>
  35 #include <sys/malloc.h>
  36 #include <sys/mutex.h>
  37 #include <sys/pmc.h>
  38 #include <sys/smp.h>
  39 #include <sys/systm.h>
  40
  41 #include <machine/cpufunc.h>
  42 #include <machine/md_var.h>
  43 #include <machine/pmc_mdep.h>
  44 #include <machine/specialreg.h>
  45
  46 #ifdef  DEBUG
  47 enum pmc_class  amd_pmc_class;
  48 #endif
  49
  50 /* AMD K7 & K8 PMCs */
  51 struct amd_descr {
  52         struct pmc_descr pm_descr;  /* "base class" */
  53         uint32_t        pm_evsel;   /* address of EVSEL register */
  54         uint32_t        pm_perfctr; /* address of PERFCTR register */
  55 };
  56
  57 static  struct amd_descr amd_pmcdesc[AMD_NPMCS] =
  58 {
  59     {
  60         .pm_descr =
  61         {
  62                 .pd_name  = "TSC",
  63                 .pd_class = PMC_CLASS_TSC,
  64                 .pd_caps  = PMC_CAP_READ,
  65                 .pd_width = 64
  66         },
  67         .pm_evsel   = MSR_TSC,
  68         .pm_perfctr = 0 /* unused */
  69     },
  70
  71     {
  72         .pm_descr =
  73         {
  74                 .pd_name  = "",
  75                 .pd_class = -1,
  76                 .pd_caps  = AMD_PMC_CAPS,
  77                 .pd_width = 48
  78         },
  79         .pm_evsel   = AMD_PMC_EVSEL_0,
  80         .pm_perfctr = AMD_PMC_PERFCTR_0
  81     },
  82     {
  83         .pm_descr =
  84         {
  85                 .pd_name  = "",
  86                 .pd_class = -1,
  87                 .pd_caps  = AMD_PMC_CAPS,
  88                 .pd_width = 48
  89         },
  90         .pm_evsel   = AMD_PMC_EVSEL_1,
  91         .pm_perfctr = AMD_PMC_PERFCTR_1
  92     },
  93     {
  94         .pm_descr =
  95         {
  96                 .pd_name  = "",
  97                 .pd_class = -1,
  98                 .pd_caps  = AMD_PMC_CAPS,
  99                 .pd_width = 48
 100         },
 101         .pm_evsel   = AMD_PMC_EVSEL_2,
 102         .pm_perfctr = AMD_PMC_PERFCTR_2
 103     },
 104     {
 105         .pm_descr =
 106         {
 107                 .pd_name  = "",
 108                 .pd_class = -1,
 109                 .pd_caps  = AMD_PMC_CAPS,
 110                 .pd_width = 48
 111         },
 112         .pm_evsel   = AMD_PMC_EVSEL_3,
 113         .pm_perfctr = AMD_PMC_PERFCTR_3
 114     }
 115 };
 116
 117 struct amd_event_code_map {
 118         enum pmc_event  pe_ev;   /* enum value */
 119         uint8_t         pe_code; /* encoded event mask */
 120         uint8_t         pe_mask; /* bits allowed in unit mask */
 121 };
 122
 123 const struct amd_event_code_map amd_event_codes[] = {
 124 #if     defined(__i386__)       /* 32 bit Athlon (K7) only */
 125         { PMC_EV_K7_DC_ACCESSES,                0x40, 0 },
 126         { PMC_EV_K7_DC_MISSES,                  0x41, 0 },
 127         { PMC_EV_K7_DC_REFILLS_FROM_L2,         0x42, AMD_PMC_UNITMASK_MOESI },
 128         { PMC_EV_K7_DC_REFILLS_FROM_SYSTEM,     0x43, AMD_PMC_UNITMASK_MOESI },
 129         { PMC_EV_K7_DC_WRITEBACKS,              0x44, AMD_PMC_UNITMASK_MOESI },
 130         { PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS, 0x45, 0 },
 131         { PMC_EV_K7_L1_AND_L2_DTLB_MISSES,      0x46, 0 },
 132         { PMC_EV_K7_MISALIGNED_REFERENCES,      0x47, 0 },
 133
 134         { PMC_EV_K7_IC_FETCHES,                 0x80, 0 },
 135         { PMC_EV_K7_IC_MISSES,                  0x81, 0 },
 136
 137         { PMC_EV_K7_L1_ITLB_MISSES,             0x84, 0 },
 138         { PMC_EV_K7_L1_L2_ITLB_MISSES,          0x85, 0 },
 139
 140         { PMC_EV_K7_RETIRED_INSTRUCTIONS,       0xC0, 0 },
 141         { PMC_EV_K7_RETIRED_OPS,                0xC1, 0 },
 142         { PMC_EV_K7_RETIRED_BRANCHES,           0xC2, 0 },
 143         { PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0 },
 144         { PMC_EV_K7_RETIRED_TAKEN_BRANCHES,     0xC4, 0 },
 145         { PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0 },
 146         { PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0 },
 147         { PMC_EV_K7_RETIRED_RESYNC_BRANCHES,    0xC7, 0 },
 148         { PMC_EV_K7_INTERRUPTS_MASKED_CYCLES,   0xCD, 0 },
 149         { PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0 },
 150         { PMC_EV_K7_HARDWARE_INTERRUPTS,        0xCF, 0 },
 151 #endif
 152
 153         { PMC_EV_K8_FP_DISPATCHED_FPU_OPS,              0x00, 0x3F },
 154         { PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED,  0x01, 0x00 },
 155         { PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS,    0x02, 0x00 },
 156
 157         { PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD,           0x20, 0x7F },
 158         { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE,
 159                                                         0x21, 0x00 },
 160         { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x22, 0x00 },
 161         { PMC_EV_K8_LS_BUFFER2_FULL,                    0x23, 0x00 },
 162         { PMC_EV_K8_LS_LOCKED_OPERATION,                0x24, 0x07 },
 163         { PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL,  0x25, 0x00 },
 164         { PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS,     0x26, 0x00 },
 165         { PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS,      0x27, 0x00 },
 166
 167         { PMC_EV_K8_DC_ACCESS,                          0x40, 0x00 },
 168         { PMC_EV_K8_DC_MISS,                            0x41, 0x00 },
 169         { PMC_EV_K8_DC_REFILL_FROM_L2,                  0x42, 0x1F },
 170         { PMC_EV_K8_DC_REFILL_FROM_SYSTEM,              0x43, 0x1F },
 171         { PMC_EV_K8_DC_COPYBACK,                        0x44, 0x1F },
 172         { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT,    0x45, 0x00 },
 173         { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS,   0x46, 0x00 },
 174         { PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE,       0x47, 0x00 },
 175         { PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL,  0x48, 0x00 },
 176         { PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL, 0x49, 0x00 },
 177         { PMC_EV_K8_DC_ONE_BIT_ECC_ERROR,               0x4A, 0x03 },
 178         { PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS, 0x4B, 0x07 },
 179         { PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS,        0x4C, 0x03 },
 180
 181         { PMC_EV_K8_BU_CPU_CLK_UNHALTED,                0x76, 0x00 },
 182         { PMC_EV_K8_BU_INTERNAL_L2_REQUEST,             0x7D, 0x1F },
 183         { PMC_EV_K8_BU_FILL_REQUEST_L2_MISS,            0x7E, 0x07 },
 184         { PMC_EV_K8_BU_FILL_INTO_L2,                    0x7F, 0x03 },
 185
 186         { PMC_EV_K8_IC_FETCH,                           0x80, 0x00 },
 187         { PMC_EV_K8_IC_MISS,                            0x81, 0x00 },
 188         { PMC_EV_K8_IC_REFILL_FROM_L2,                  0x82, 0x00 },
 189         { PMC_EV_K8_IC_REFILL_FROM_SYSTEM,              0x83, 0x00 },
 190         { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT,    0x84, 0x00 },
 191         { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS,   0x85, 0x00 },
 192         { PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x86, 0x00 },
 193         { PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL,         0x87, 0x00 },
 194         { PMC_EV_K8_IC_RETURN_STACK_HIT,                0x88, 0x00 },
 195         { PMC_EV_K8_IC_RETURN_STACK_OVERFLOW,           0x89, 0x00 },
 196
 197         { PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS,        0xC0, 0x00 },
 198         { PMC_EV_K8_FR_RETIRED_UOPS,                    0xC1, 0x00 },
 199         { PMC_EV_K8_FR_RETIRED_BRANCHES,                0xC2, 0x00 },
 200         { PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED,   0xC3, 0x00 },
 201         { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES,          0xC4, 0x00 },
 202         { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0x00 },
 203         { PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS,   0xC6, 0x00 },
 204         { PMC_EV_K8_FR_RETIRED_RESYNCS,                 0xC7, 0x00 },
 205         { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS,            0xC8, 0x00 },
 206         { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED, 0xC9, 0x00 },
 207         { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE,
 208                                                         0xCA, 0x00 },
 209         { PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS,        0xCB, 0x0F },
 210         { PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS,
 211                                                         0xCC, 0x07 },
 212         { PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES,        0xCD, 0x00 },
 213         { PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0x00 },
 214         { PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS,       0xCF, 0x00 },
 215
 216         { PMC_EV_K8_FR_DECODER_EMPTY,                   0xD0, 0x00 },
 217         { PMC_EV_K8_FR_DISPATCH_STALLS,                 0xD1, 0x00 },
 218         { PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE,
 219                                                         0xD2, 0x00 },
 220         { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION, 0xD3, 0x00 },
 221         { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD, 0xD4, 0x00 },
 222         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL,
 223                                                         0xD5, 0x00 },
 224         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL,
 225                                                         0xD6, 0x00 },
 226         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL, 0xD7, 0x00 },
 227         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL,  0xD8, 0x00 },
 228         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET,
 229                                                         0xD9, 0x00 },
 230         { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING,
 231                                                         0xDA, 0x00 },
 232         { PMC_EV_K8_FR_FPU_EXCEPTIONS,                  0xDB, 0x0F },
 233         { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0,   0xDC, 0x00 },
 234         { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1,   0xDD, 0x00 },
 235         { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2,   0xDE, 0x00 },
 236         { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3,   0xDF, 0x00 },
 237
 238         { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT, 0xE0, 0x7 },
 239         { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW, 0xE1, 0x00 },
 240         { PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED,
 241                                                         0xE2, 0x00 },
 242         { PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND,    0xE3, 0x07 },
 243         { PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION, 0xE4, 0x0F },
 244         { PMC_EV_K8_NB_SIZED_COMMANDS,                  0xEB, 0x7F },
 245         { PMC_EV_K8_NB_PROBE_RESULT,                    0xEC, 0x0F },
 246         { PMC_EV_K8_NB_HT_BUS0_BANDWIDTH,               0xF6, 0x0F },
 247         { PMC_EV_K8_NB_HT_BUS1_BANDWIDTH,               0xF7, 0x0F },
 248         { PMC_EV_K8_NB_HT_BUS2_BANDWIDTH,               0xF8, 0x0F }
 249
 250 };
 251
 252 const int amd_event_codes_size =
 253         sizeof(amd_event_codes) / sizeof(amd_event_codes[0]);
 254
 255 /*
 256  * read a pmc register
 257  */
 258
 259 static int
 260 amd_read_pmc(int cpu, int ri, pmc_value_t *v)
 261 {
 262         enum pmc_mode mode;
 263         const struct amd_descr *pd;
 264         struct pmc *pm;
 265         const struct pmc_hw *phw;
 266         pmc_value_t tmp;
 267
 268         KASSERT(cpu >= 0 && cpu < mp_ncpus,
 269             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 270         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 271             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 272
 273         phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
 274         pd  = &amd_pmcdesc[ri];
 275         pm  = phw->phw_pmc;
 276
 277         KASSERT(pm != NULL,
 278             ("[amd,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__,
 279                 cpu, ri));
 280
 281         mode = PMC_TO_MODE(pm);
 282
 283         PMCDBG(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class);
 284
 285         /* Reading the TSC is a special case */
 286         if (pd->pm_descr.pd_class == PMC_CLASS_TSC) {
 287                 KASSERT(PMC_IS_COUNTING_MODE(mode),
 288                     ("[amd,%d] TSC counter in non-counting mode", __LINE__));
 289                 *v = rdtsc();
 290                 PMCDBG(MDP,REA,2,"amd-read id=%d -> %jd", ri, *v);
 291                 return 0;
 292         }
 293
 294 #ifdef  DEBUG
 295         KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
 296             ("[amd,%d] unknown PMC class (%d)", __LINE__,
 297                 pd->pm_descr.pd_class));
 298 #endif
 299
 300         tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */
 301         if (PMC_IS_SAMPLING_MODE(mode))
 302                 *v = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
 303         else
 304                 *v = tmp;
 305
 306         PMCDBG(MDP,REA,2,"amd-read id=%d -> %jd", ri, *v);
 307
 308         return 0;
 309 }
 310
 311 /*
 312  * Write a PMC MSR.
 313  */
 314
 315 static int
 316 amd_write_pmc(int cpu, int ri, pmc_value_t v)
 317 {
 318         const struct amd_descr *pd;
 319         struct pmc *pm;
 320         const struct pmc_hw *phw;
 321         enum pmc_mode mode;
 322
 323         KASSERT(cpu >= 0 && cpu < mp_ncpus,
 324             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 325         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 326             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 327
 328         phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
 329         pd  = &amd_pmcdesc[ri];
 330         pm  = phw->phw_pmc;
 331
 332         KASSERT(pm != NULL,
 333             ("[amd,%d] PMC not owned (cpu%d,pmc%d)", __LINE__,
 334                 cpu, ri));
 335
 336         mode = PMC_TO_MODE(pm);
 337
 338         if (pd->pm_descr.pd_class == PMC_CLASS_TSC)
 339                 return 0;
 340
 341 #ifdef  DEBUG
 342         KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
 343             ("[amd,%d] unknown PMC class (%d)", __LINE__,
 344                 pd->pm_descr.pd_class));
 345 #endif
 346
 347         /* use 2's complement of the count for sampling mode PMCs */
 348         if (PMC_IS_SAMPLING_MODE(mode))
 349                 v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
 350
 351         PMCDBG(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v);
 352
 353         /* write the PMC value */
 354         wrmsr(pd->pm_perfctr, v);
 355         return 0;
 356 }
 357
 358 /*
 359  * configure hardware pmc according to the configuration recorded in
 360  * pmc 'pm'.
 361  */
 362
 363 static int
 364 amd_config_pmc(int cpu, int ri, struct pmc *pm)
 365 {
 366         struct pmc_hw *phw;
 367
 368         PMCDBG(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
 369
 370         KASSERT(cpu >= 0 && cpu < mp_ncpus,
 371             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 372         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 373             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 374
 375         phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
 376
 377         KASSERT(pm == NULL || phw->phw_pmc == NULL,
 378             ("[amd,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
 379                 __LINE__, pm, phw->phw_pmc));
 380
 381         phw->phw_pmc = pm;
 382         return 0;
 383 }
 384
 385 /*
 386  * Retrieve a configured PMC pointer from hardware state.
 387  */
 388
 389 static int
 390 amd_get_config(int cpu, int ri, struct pmc **ppm)
 391 {
 392         *ppm = pmc_pcpu[cpu]->pc_hwpmcs[ri]->phw_pmc;
 393
 394         return 0;
 395 }
 396
 397 /*
 398  * Machine dependent actions taken during the context switch in of a
 399  * thread.
 400  */
 401
 402 static int
 403 amd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
 404 {
 405         (void) pc;
 406
 407         PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
 408             (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0);
 409
 410         /* enable the RDPMC instruction if needed */
 411         if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
 412                 load_cr4(rcr4() | CR4_PCE);
 413
 414         return 0;
 415 }
 416
 417 /*
 418  * Machine dependent actions taken during the context switch out of a
 419  * thread.
 420  */
 421
 422 static int
 423 amd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
 424 {
 425         (void) pc;
 426         (void) pp;              /* can be NULL */
 427
 428         PMCDBG(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ?
 429             (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0);
 430
 431         /* always turn off the RDPMC instruction */
 432         load_cr4(rcr4() & ~CR4_PCE);
 433
 434         return 0;
 435 }
 436
 437 /*
 438  * Check if a given allocation is feasible.
 439  */
 440
 441 static int
 442 amd_allocate_pmc(int cpu, int ri, struct pmc *pm,
 443     const struct pmc_op_pmcallocate *a)
 444 {
 445         int i;
 446         uint32_t allowed_unitmask, caps, config, unitmask;
 447         enum pmc_event pe;
 448         const struct pmc_descr *pd;
 449
 450         (void) cpu;
 451
 452         KASSERT(cpu >= 0 && cpu < mp_ncpus,
 453             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 454         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 455             ("[amd,%d] illegal row index %d", __LINE__, ri));
 456
 457         pd = &amd_pmcdesc[ri].pm_descr;
 458
 459         /* check class match */
 460         if (pd->pd_class != a->pm_class)
 461                 return EINVAL;
 462
 463         caps = pm->pm_caps;
 464
 465         PMCDBG(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps);
 466
 467         if ((pd->pd_caps & caps) != caps)
 468                 return EPERM;
 469         if (pd->pd_class == PMC_CLASS_TSC) {
 470                 /* TSC's are always allocated in system-wide counting mode */
 471                 if (a->pm_ev != PMC_EV_TSC_TSC ||
 472                     a->pm_mode != PMC_MODE_SC)
 473                         return EINVAL;
 474                 return 0;
 475         }
 476
 477 #ifdef  DEBUG
 478         KASSERT(pd->pd_class == amd_pmc_class,
 479             ("[amd,%d] Unknown PMC class (%d)", __LINE__, pd->pd_class));
 480 #endif
 481
 482         pe = a->pm_ev;
 483
 484         /* map ev to the correct event mask code */
 485         config = allowed_unitmask = 0;
 486         for (i = 0; i < amd_event_codes_size; i++)
 487                 if (amd_event_codes[i].pe_ev == pe) {
 488                         config =
 489                             AMD_PMC_TO_EVENTMASK(amd_event_codes[i].pe_code);
 490                         allowed_unitmask =
 491                             AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask);
 492                         break;
 493                 }
 494         if (i == amd_event_codes_size)
 495                 return EINVAL;
 496
 497         unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK;
 498         if (unitmask & ~allowed_unitmask) /* disallow reserved bits */
 499                 return EINVAL;
 500
 501         if (unitmask && (caps & PMC_CAP_QUALIFIER))
 502                 config |= unitmask;
 503
 504         if (caps & PMC_CAP_THRESHOLD)
 505                 config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK;
 506
 507         /* set at least one of the 'usr' or 'os' caps */
 508         if (caps & PMC_CAP_USER)
 509                 config |= AMD_PMC_USR;
 510         if (caps & PMC_CAP_SYSTEM)
 511                 config |= AMD_PMC_OS;
 512         if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0)
 513                 config |= (AMD_PMC_USR|AMD_PMC_OS);
 514
 515         if (caps & PMC_CAP_EDGE)
 516                 config |= AMD_PMC_EDGE;
 517         if (caps & PMC_CAP_INVERT)
 518                 config |= AMD_PMC_INVERT;
 519         if (caps & PMC_CAP_INTERRUPT)
 520                 config |= AMD_PMC_INT;
 521
 522         pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */
 523
 524         PMCDBG(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config);
 525
 526         return 0;
 527 }
 528
 529 /*
 530  * Release machine dependent state associated with a PMC.  This is a
 531  * no-op on this architecture.
 532  *
 533  */
 534
 535 /* ARGSUSED0 */
 536 static int
 537 amd_release_pmc(int cpu, int ri, struct pmc *pmc)
 538 {
 539 #ifdef  DEBUG
 540         const struct amd_descr *pd;
 541 #endif
 542         struct pmc_hw *phw;
 543
 544         (void) pmc;
 545
 546         KASSERT(cpu >= 0 && cpu < mp_ncpus,
 547             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 548         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 549             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 550
 551         phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
 552
 553         KASSERT(phw->phw_pmc == NULL,
 554             ("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
 555
 556 #ifdef  DEBUG
 557         pd = &amd_pmcdesc[ri];
 558         if (pd->pm_descr.pd_class == amd_pmc_class)
 559                 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
 560                     ("[amd,%d] PMC %d released while active", __LINE__, ri));
 561 #endif
 562
 563         return 0;
 564 }
 565
 566 /*
 567  * start a PMC.
 568  */
 569
 570 static int
 571 amd_start_pmc(int cpu, int ri)
 572 {
 573         uint32_t config;
 574         struct pmc *pm;
 575         struct pmc_hw *phw;
 576         const struct amd_descr *pd;
 577
 578         KASSERT(cpu >= 0 && cpu < mp_ncpus,
 579             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 580         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 581             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 582
 583         phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
 584         pm  = phw->phw_pmc;
 585         pd = &amd_pmcdesc[ri];
 586
 587         KASSERT(pm != NULL,
 588             ("[amd,%d] starting cpu%d,pmc%d with null pmc record", __LINE__,
 589                 cpu, ri));
 590
 591         PMCDBG(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri);
 592
 593         if (pd->pm_descr.pd_class == PMC_CLASS_TSC)
 594                 return 0;       /* TSCs are always running */
 595
 596 #ifdef  DEBUG
 597         KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
 598             ("[amd,%d] unknown PMC class (%d)", __LINE__,
 599                 pd->pm_descr.pd_class));
 600 #endif
 601
 602         KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
 603             ("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__,
 604             ri, cpu, pd->pm_descr.pd_name));
 605
 606         /* turn on the PMC ENABLE bit */
 607         config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE;
 608
 609         PMCDBG(MDP,STA,2,"amd-start config=0x%x", config);
 610
 611         wrmsr(pd->pm_evsel, config);
 612         return 0;
 613 }
 614
 615 /*
 616  * Stop a PMC.
 617  */
 618
 619 static int
 620 amd_stop_pmc(int cpu, int ri)
 621 {
 622         struct pmc *pm;
 623         struct pmc_hw *phw;
 624         const struct amd_descr *pd;
 625         uint64_t config;
 626
 627         KASSERT(cpu >= 0 && cpu < mp_ncpus,
 628             ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
 629         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 630             ("[amd,%d] illegal row-index %d", __LINE__, ri));
 631
 632         phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
 633         pm  = phw->phw_pmc;
 634         pd  = &amd_pmcdesc[ri];
 635
 636         KASSERT(pm != NULL,
 637             ("[amd,%d] cpu%d,pmc%d no PMC to stop", __LINE__,
 638                 cpu, ri));
 639
 640         /* can't stop a TSC */
 641         if (pd->pm_descr.pd_class == PMC_CLASS_TSC)
 642                 return 0;
 643
 644 #ifdef  DEBUG
 645         KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
 646             ("[amd,%d] unknown PMC class (%d)", __LINE__,
 647                 pd->pm_descr.pd_class));
 648 #endif
 649
 650         KASSERT(!AMD_PMC_IS_STOPPED(pd->pm_evsel),
 651             ("[amd,%d] PMC%d, CPU%d \"%s\" already stopped",
 652                 __LINE__, ri, cpu, pd->pm_descr.pd_name));
 653
 654         PMCDBG(MDP,STO,1,"amd-stop ri=%d", ri);
 655
 656         /* turn off the PMC ENABLE bit */
 657         config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE;
 658         wrmsr(pd->pm_evsel, config);
 659         return 0;
 660 }
 661
 662 /*
 663  * Interrupt handler.  This function needs to return '1' if the
 664  * interrupt was this CPU's PMCs or '0' otherwise.  It is not allowed
 665  * to sleep or do anything a 'fast' interrupt handler is not allowed
 666  * to do.
 667  */
 668
 669 static int
 670 amd_intr(int cpu, uintptr_t eip, int usermode)
 671 {
 672         int i, error, retval, ri;
 673         uint32_t config, evsel, perfctr;
 674         struct pmc *pm;
 675         struct pmc_cpu *pc;
 676         struct pmc_hw *phw;
 677         pmc_value_t v;
 678
 679         KASSERT(cpu >= 0 && cpu < mp_ncpus,
 680             ("[amd,%d] out of range CPU %d", __LINE__, cpu));
 681
 682         PMCDBG(MDP,INT,1, "cpu=%d eip=%p um=%d", cpu, (void *) eip,
 683             usermode);
 684
 685         retval = 0;
 686
 687         pc = pmc_pcpu[cpu];
 688
 689         /*
 690          * look for all PMCs that have interrupted:
 691          * - skip over the TSC [PMC#0]
 692          * - look for a running, sampling PMC which has overflowed
 693          *   and which has a valid 'struct pmc' association
 694          *
 695          * If found, we call a helper to process the interrupt.
 696          *
 697          * If multiple PMCs interrupt at the same time, the AMD64
 698          * processor appears to deliver as many NMIs as there are
 699          * outstanding PMC interrupts.  Thus we need to only process
 700          * one interrupt at a time.
 701          */
 702
 703         for (i = 0; retval == 0 && i < AMD_NPMCS-1; i++) {
 704
 705                 ri = i + 1;     /* row index; TSC is at ri == 0 */
 706
 707                 if (!AMD_PMC_HAS_OVERFLOWED(i))
 708                         continue;
 709
 710                 phw = pc->pc_hwpmcs[ri];
 711
 712                 KASSERT(phw != NULL, ("[amd,%d] null PHW pointer", __LINE__));
 713
 714                 if ((pm = phw->phw_pmc) == NULL ||
 715                     pm->pm_state != PMC_STATE_RUNNING ||
 716                     !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
 717                         continue;
 718                 }
 719
 720                 retval = 1;     /* found an interrupting PMC */
 721
 722                 /* stop the PMC, reload count */
 723                 evsel   = AMD_PMC_EVSEL_0 + i;
 724                 perfctr = AMD_PMC_PERFCTR_0 + i;
 725                 v       = pm->pm_sc.pm_reloadcount;
 726                 config  = rdmsr(evsel);
 727
 728                 KASSERT((config & ~AMD_PMC_ENABLE) ==
 729                     (pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE),
 730                     ("[amd,%d] config mismatch reg=0x%x pm=0x%x", __LINE__,
 731                         config, pm->pm_md.pm_amd.pm_amd_evsel));
 732
 733                 wrmsr(evsel, config & ~AMD_PMC_ENABLE);
 734                 wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v));
 735
 736                 /* restart the counter if there was no error during logging */
 737                 error = pmc_process_interrupt(cpu, pm, eip, usermode);
 738                 if (error == 0)
 739                         wrmsr(evsel, config | AMD_PMC_ENABLE);
 740         }
 741
 742         atomic_add_int(retval ? &pmc_stats.pm_intr_processed :
 743             &pmc_stats.pm_intr_ignored, 1);
 744
 745         return retval;
 746 }
 747
 748 /*
 749  * describe a PMC
 750  */
 751 static int
 752 amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
 753 {
 754         int error;
 755         size_t copied;
 756         const struct amd_descr *pd;
 757         struct pmc_hw *phw;
 758
 759         KASSERT(cpu >= 0 && cpu < mp_ncpus,
 760             ("[amd,%d] illegal CPU %d", __LINE__, cpu));
 761         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 762             ("[amd,%d] row-index %d out of range", __LINE__, ri));
 763
 764         phw = pmc_pcpu[cpu]->pc_hwpmcs[ri];
 765         pd  = &amd_pmcdesc[ri];
 766
 767         if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name,
 768                  PMC_NAME_MAX, &copied)) != 0)
 769                 return error;
 770
 771         pi->pm_class = pd->pm_descr.pd_class;
 772
 773         if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
 774                 pi->pm_enabled = TRUE;
 775                 *ppmc          = phw->phw_pmc;
 776         } else {
 777                 pi->pm_enabled = FALSE;
 778                 *ppmc          = NULL;
 779         }
 780
 781         return 0;
 782 }
 783
 784 /*
 785  * i386 specific entry points
 786  */
 787
 788 /*
 789  * return the MSR address of the given PMC.
 790  */
 791
 792 static int
 793 amd_get_msr(int ri, uint32_t *msr)
 794 {
 795         KASSERT(ri >= 0 && ri < AMD_NPMCS,
 796             ("[amd,%d] ri %d out of range", __LINE__, ri));
 797
 798         *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0;
 799         return 0;
 800 }
 801
 802 /*
 803  * processor dependent initialization.
 804  */
 805
 806 /*
 807  * Per-processor data structure
 808  *
 809  * [common stuff]
 810  * [5 struct pmc_hw pointers]
 811  * [5 struct pmc_hw structures]
 812  */
 813
 814 struct amd_cpu {
 815         struct pmc_cpu  pc_common;
 816         struct pmc_hw   *pc_hwpmcs[AMD_NPMCS];
 817         struct pmc_hw   pc_amdpmcs[AMD_NPMCS];
 818 };
 819
 820
 821 static int
 822 amd_init(int cpu)
 823 {
 824         int n;
 825         struct amd_cpu *pcs;
 826         struct pmc_hw  *phw;
 827
 828         KASSERT(cpu >= 0 && cpu < mp_ncpus,
 829             ("[amd,%d] insane cpu number %d", __LINE__, cpu));
 830
 831         PMCDBG(MDP,INI,1,"amd-init cpu=%d", cpu);
 832
 833         MALLOC(pcs, struct amd_cpu *, sizeof(struct amd_cpu), M_PMC,
 834             M_WAITOK|M_ZERO);
 835
 836         phw = &pcs->pc_amdpmcs[0];
 837
 838         /*
 839          * Initialize the per-cpu mutex and set the content of the
 840          * hardware descriptors to a known state.
 841          */
 842
 843         for (n = 0; n < AMD_NPMCS; n++, phw++) {
 844                 phw->phw_state    = PMC_PHW_FLAG_IS_ENABLED |
 845                     PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n);
 846                 phw->phw_pmc      = NULL;
 847                 pcs->pc_hwpmcs[n] = phw;
 848         }
 849
 850         /* Mark the TSC as shareable */
 851         pcs->pc_hwpmcs[0]->phw_state |= PMC_PHW_FLAG_IS_SHAREABLE;
 852
 853         pmc_pcpu[cpu] = (struct pmc_cpu *) pcs;
 854
 855         return 0;
 856 }
 857
 858
 859 /*
 860  * processor dependent cleanup prior to the KLD
 861  * being unloaded
 862  */
 863
 864 static int
 865 amd_cleanup(int cpu)
 866 {
 867         int i;
 868         uint32_t evsel;
 869         struct pmc_cpu *pcs;
 870
 871         KASSERT(cpu >= 0 && cpu < mp_ncpus,
 872             ("[amd,%d] insane cpu number (%d)", __LINE__, cpu));
 873
 874         PMCDBG(MDP,INI,1,"amd-cleanup cpu=%d", cpu);
 875
 876         /*
 877          * First, turn off all PMCs on this CPU.
 878          */
 879
 880         for (i = 0; i < 4; i++) { /* XXX this loop is now not needed */
 881                 evsel = rdmsr(AMD_PMC_EVSEL_0 + i);
 882                 evsel &= ~AMD_PMC_ENABLE;
 883                 wrmsr(AMD_PMC_EVSEL_0 + i, evsel);
 884         }
 885
 886         /*
 887          * Next, free up allocated space.
 888          */
 889
 890         if ((pcs = pmc_pcpu[cpu]) == NULL)
 891                 return 0;
 892
 893 #ifdef  DEBUG
 894         /* check the TSC */
 895         KASSERT(pcs->pc_hwpmcs[0]->phw_pmc == NULL,
 896             ("[amd,%d] CPU%d,PMC0 still in use", __LINE__, cpu));
 897         for (i = 1; i < AMD_NPMCS; i++) {
 898                 KASSERT(pcs->pc_hwpmcs[i]->phw_pmc == NULL,
 899                     ("[amd,%d] CPU%d/PMC%d in use", __LINE__, cpu, i));
 900                 KASSERT(AMD_PMC_IS_STOPPED(AMD_PMC_EVSEL_0 + (i-1)),
 901                     ("[amd,%d] CPU%d/PMC%d not stopped", __LINE__, cpu, i));
 902         }
 903 #endif
 904
 905         pmc_pcpu[cpu] = NULL;
 906         FREE(pcs, M_PMC);
 907         return 0;
 908 }
 909
 910 /*
 911  * Initialize ourselves.
 912  */
 913
 914 struct pmc_mdep *
 915 pmc_amd_initialize(void)
 916 {
 917         enum pmc_cputype cputype;
 918         enum pmc_class class;
 919         struct pmc_mdep *pmc_mdep;
 920         char *name;
 921         int i;
 922
 923         /*
 924          * The presence of hardware performance counters on the AMD
 925          * Athlon, Duron or later processors, is _not_ indicated by
 926          * any of the processor feature flags set by the 'CPUID'
 927          * instruction, so we only check the 'instruction family'
 928          * field returned by CPUID for instruction family >= 6.
 929          */
 930
 931         class = cputype = -1;
 932         name = NULL;
 933         switch (cpu_id & 0xF00) {
 934         case 0x600:             /* Athlon(tm) processor */
 935                 cputype = PMC_CPU_AMD_K7;
 936                 class = PMC_CLASS_K7;
 937                 name = "K7";
 938                 break;
 939         case 0xF00:             /* Athlon64/Opteron processor */
 940                 cputype = PMC_CPU_AMD_K8;
 941                 class = PMC_CLASS_K8;
 942                 name = "K8";
 943                 break;
 944         }
 945
 946         if ((int) cputype == -1) {
 947                 (void) printf("pmc: Unknown AMD CPU.\n");
 948                 return NULL;
 949         }
 950
 951 #ifdef  DEBUG
 952         amd_pmc_class = class;
 953 #endif
 954
 955         MALLOC(pmc_mdep, struct pmc_mdep *, sizeof(struct pmc_mdep),
 956             M_PMC, M_WAITOK|M_ZERO);
 957
 958         pmc_mdep->pmd_cputype      = cputype;
 959         pmc_mdep->pmd_npmc         = AMD_NPMCS;
 960
 961         /* this processor has two classes of usable PMCs */
 962         pmc_mdep->pmd_nclass       = 2;
 963
 964         /* TSC */
 965         pmc_mdep->pmd_classes[0].pm_class   = PMC_CLASS_TSC;
 966         pmc_mdep->pmd_classes[0].pm_caps    = PMC_CAP_READ;
 967         pmc_mdep->pmd_classes[0].pm_width   = 64;
 968
 969         /* AMD K7/K8 PMCs */
 970         pmc_mdep->pmd_classes[1].pm_class   = class;
 971         pmc_mdep->pmd_classes[1].pm_caps    = AMD_PMC_CAPS;
 972         pmc_mdep->pmd_classes[1].pm_width   = 48;
 973
 974         pmc_mdep->pmd_nclasspmcs[0] = 1;
 975         pmc_mdep->pmd_nclasspmcs[1] = (AMD_NPMCS-1);
 976
 977         /* fill in the correct pmc name and class */
 978         for (i = 1; i < AMD_NPMCS; i++) {
 979                 (void) snprintf(amd_pmcdesc[i].pm_descr.pd_name,
 980                     sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d",
 981                     name, i-1);
 982                 amd_pmcdesc[i].pm_descr.pd_class = class;
 983         }
 984
 985         pmc_mdep->pmd_init         = amd_init;
 986         pmc_mdep->pmd_cleanup      = amd_cleanup;
 987         pmc_mdep->pmd_switch_in    = amd_switch_in;
 988         pmc_mdep->pmd_switch_out   = amd_switch_out;
 989         pmc_mdep->pmd_read_pmc     = amd_read_pmc;
 990         pmc_mdep->pmd_write_pmc    = amd_write_pmc;
 991         pmc_mdep->pmd_config_pmc   = amd_config_pmc;
 992         pmc_mdep->pmd_get_config   = amd_get_config;
 993         pmc_mdep->pmd_allocate_pmc = amd_allocate_pmc;
 994         pmc_mdep->pmd_release_pmc  = amd_release_pmc;
 995         pmc_mdep->pmd_start_pmc    = amd_start_pmc;
 996         pmc_mdep->pmd_stop_pmc     = amd_stop_pmc;
 997         pmc_mdep->pmd_intr         = amd_intr;
 998         pmc_mdep->pmd_describe     = amd_describe;
 999         pmc_mdep->pmd_get_msr      = amd_get_msr; /* i386 */
1000
1001         PMCDBG(MDP,INI,0,"%s","amd-initialize");
1002
1003         return pmc_mdep;
1004 }