1 /******************************************************************************
3 Copyright (c) 2001-2009, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "ixgbe_type.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw);
41 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
42 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
43 ixgbe_link_speed *speed,
45 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
46 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
47 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw);
48 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
49 ixgbe_link_speed *speed, bool *link_up,
50 bool link_up_wait_to_complete);
51 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
52 ixgbe_link_speed speed,
54 bool autoneg_wait_to_complete);
55 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
56 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
57 ixgbe_link_speed speed,
59 bool autoneg_wait_to_complete);
60 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
61 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
62 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
63 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan,
64 u32 vind, bool vlan_on);
65 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
66 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
67 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
68 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
70 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
71 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);
74 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
75 * @hw: pointer to hardware structure
77 * Read PCIe configuration space, and get the MSI-X vector count from
78 * the capabilities table.
80 u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
84 if (hw->mac.msix_vectors_from_pcie) {
85 msix_count = IXGBE_READ_PCIE_WORD(hw,
86 IXGBE_PCIE_MSIX_82598_CAPS);
87 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
89 /* MSI-X count is zero-based in HW, so increment to give
97 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
98 * @hw: pointer to hardware structure
100 * Initialize the function pointers and assign the MAC type for 82598.
101 * Does not touch the hardware.
103 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
105 struct ixgbe_mac_info *mac = &hw->mac;
106 struct ixgbe_phy_info *phy = &hw->phy;
109 ret_val = ixgbe_init_phy_ops_generic(hw);
110 ret_val = ixgbe_init_ops_generic(hw);
113 phy->ops.init = &ixgbe_init_phy_ops_82598;
116 mac->ops.reset_hw = &ixgbe_reset_hw_82598;
117 mac->ops.get_media_type = &ixgbe_get_media_type_82598;
118 mac->ops.get_supported_physical_layer =
119 &ixgbe_get_supported_physical_layer_82598;
120 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
121 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
123 /* RAR, Multicast, VLAN */
124 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
125 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
126 mac->ops.set_vfta = &ixgbe_set_vfta_82598;
127 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
130 mac->ops.fc_enable = &ixgbe_fc_enable_82598;
132 mac->mcft_size = 128;
134 mac->num_rar_entries = 16;
135 mac->max_tx_queues = 32;
136 mac->max_rx_queues = 64;
137 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
140 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
143 mac->ops.check_link = &ixgbe_check_mac_link_82598;
144 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
145 mac->ops.setup_link_speed = &ixgbe_setup_mac_link_speed_82598;
146 mac->ops.get_link_capabilities =
147 &ixgbe_get_link_capabilities_82598;
153 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
154 * @hw: pointer to hardware structure
156 * Initialize any function pointers that were not able to be
157 * set during init_shared_code because the PHY/SFP type was
158 * not known. Perform the SFP init if necessary.
161 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
163 struct ixgbe_mac_info *mac = &hw->mac;
164 struct ixgbe_phy_info *phy = &hw->phy;
165 s32 ret_val = IXGBE_SUCCESS;
166 u16 list_offset, data_offset;
169 /* Identify the PHY */
170 phy->ops.identify(hw);
172 /* Overwrite the link function pointers if copper PHY */
173 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
174 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
175 mac->ops.setup_link_speed =
176 &ixgbe_setup_copper_link_speed_82598;
177 mac->ops.get_link_capabilities =
178 &ixgbe_get_copper_link_capabilities_generic;
181 switch (hw->phy.type) {
183 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
184 phy->ops.get_firmware_version =
185 &ixgbe_get_phy_firmware_version_tnx;
188 phy->ops.get_firmware_version =
189 &ixgbe_get_phy_firmware_version_aq;
192 phy->ops.reset = &ixgbe_reset_phy_nl;
194 /* Call SFP+ identify routine to get the SFP+ module type */
195 ret_val = phy->ops.identify_sfp(hw);
196 if (ret_val != IXGBE_SUCCESS)
198 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
199 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
203 /* Check to see if SFP+ module is supported */
204 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
207 if (ret_val != IXGBE_SUCCESS) {
208 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
221 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
222 * @hw: pointer to hardware structure
223 * @speed: pointer to link speed
224 * @autoneg: boolean auto-negotiation value
226 * Determines the link capabilities by reading the AUTOC register.
228 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
229 ixgbe_link_speed *speed,
232 s32 status = IXGBE_SUCCESS;
236 * Determine link capabilities based on the stored value of AUTOC,
237 * which represents EEPROM defaults. If AUTOC value has not been
238 * stored, use the current register value.
240 if (hw->mac.orig_link_settings_stored)
241 autoc = hw->mac.orig_autoc;
243 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
245 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
246 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
247 *speed = IXGBE_LINK_SPEED_1GB_FULL;
251 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
252 *speed = IXGBE_LINK_SPEED_10GB_FULL;
256 case IXGBE_AUTOC_LMS_1G_AN:
257 *speed = IXGBE_LINK_SPEED_1GB_FULL;
261 case IXGBE_AUTOC_LMS_KX4_AN:
262 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
263 *speed = IXGBE_LINK_SPEED_UNKNOWN;
264 if (autoc & IXGBE_AUTOC_KX4_SUPP)
265 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
266 if (autoc & IXGBE_AUTOC_KX_SUPP)
267 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
272 status = IXGBE_ERR_LINK_SETUP;
280 * ixgbe_get_media_type_82598 - Determines media type
281 * @hw: pointer to hardware structure
283 * Returns the media type (fiber, copper, backplane)
285 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
287 enum ixgbe_media_type media_type;
289 /* Detect if there is a copper PHY attached. */
290 if (hw->phy.type == ixgbe_phy_cu_unknown ||
291 hw->phy.type == ixgbe_phy_tn ||
292 hw->phy.type == ixgbe_phy_aq) {
293 media_type = ixgbe_media_type_copper;
297 /* Media type for I82598 is based on device ID */
298 switch (hw->device_id) {
299 case IXGBE_DEV_ID_82598:
300 case IXGBE_DEV_ID_82598_BX:
301 /* Default device ID is mezzanine card KX/KX4 */
302 media_type = ixgbe_media_type_backplane;
304 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
305 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
306 case IXGBE_DEV_ID_82598EB_CX4:
307 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
308 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
309 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
310 case IXGBE_DEV_ID_82598EB_XF_LR:
311 case IXGBE_DEV_ID_82598EB_SFP_LOM:
312 media_type = ixgbe_media_type_fiber;
314 case IXGBE_DEV_ID_82598AT:
315 media_type = ixgbe_media_type_copper;
318 media_type = ixgbe_media_type_unknown;
326 * ixgbe_fc_enable_82598 - Enable flow control
327 * @hw: pointer to hardware structure
328 * @packetbuf_num: packet buffer number (0-7)
330 * Enable flow control according to the current settings.
332 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
334 s32 ret_val = IXGBE_SUCCESS;
339 DEBUGFUNC("ixgbe_fc_enable_82598");
341 /* Negotiate the fc mode to use */
342 ret_val = ixgbe_fc_autoneg(hw);
346 /* Disable any previous flow control settings */
347 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
348 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
350 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
351 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
354 * The possible values of fc.current_mode are:
355 * 0: Flow control is completely disabled
356 * 1: Rx flow control is enabled (we can receive pause frames,
357 * but not send pause frames).
358 * 2: Tx flow control is enabled (we can send pause frames but
359 * we do not support receiving pause frames).
360 * 3: Both Rx and Tx flow control (symmetric) are enabled.
363 switch (hw->fc.current_mode) {
365 /* Flow control is disabled by software override or autoneg.
366 * The code below will actually disable it in the HW.
369 case ixgbe_fc_rx_pause:
371 * Rx Flow control is enabled and Tx Flow control is
372 * disabled by software override. Since there really
373 * isn't a way to advertise that we are capable of RX
374 * Pause ONLY, we will advertise that we support both
375 * symmetric and asymmetric Rx PAUSE. Later, we will
376 * disable the adapter's ability to send PAUSE frames.
378 fctrl_reg |= IXGBE_FCTRL_RFCE;
380 case ixgbe_fc_tx_pause:
382 * Tx Flow control is enabled, and Rx Flow control is
383 * disabled by software override.
385 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
388 /* Flow control (both Rx and Tx) is enabled by SW override. */
389 fctrl_reg |= IXGBE_FCTRL_RFCE;
390 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
393 DEBUGOUT("Flow control param set incorrectly\n");
394 ret_val = -IXGBE_ERR_CONFIG;
399 /* Set 802.3x based flow control settings. */
400 fctrl_reg |= IXGBE_FCTRL_DPF;
401 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
402 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
404 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
405 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
406 if (hw->fc.send_xon) {
407 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
408 (hw->fc.low_water | IXGBE_FCRTL_XONE));
410 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
414 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
415 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
418 /* Configure pause time (2 TCs per register) */
419 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
420 if ((packetbuf_num & 1) == 0)
421 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
423 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
424 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
426 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
433 * ixgbe_setup_mac_link_82598 - Configures MAC link settings
434 * @hw: pointer to hardware structure
436 * Configures link settings based on values in the ixgbe_hw struct.
437 * Restarts the link. Performs autonegotiation if needed.
439 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
444 s32 status = IXGBE_SUCCESS;
447 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
448 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
449 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
451 /* Only poll for autoneg to complete if specified to do so */
452 if (hw->phy.autoneg_wait_to_complete) {
453 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
454 IXGBE_AUTOC_LMS_KX4_AN ||
455 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
456 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
457 links_reg = 0; /* Just in case Autoneg time = 0 */
458 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
459 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
460 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
464 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
465 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
466 DEBUGOUT("Autonegotiation did not complete.\n");
471 /* Add delay to filter out noises during initial link setup */
478 * ixgbe_check_mac_link_82598 - Get link/speed status
479 * @hw: pointer to hardware structure
480 * @speed: pointer to link speed
481 * @link_up: TRUE is link is up, FALSE otherwise
482 * @link_up_wait_to_complete: bool used to wait for link up or not
484 * Reads the links register to determine if link is up and the current speed
486 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
487 ixgbe_link_speed *speed, bool *link_up,
488 bool link_up_wait_to_complete)
492 u16 link_reg, adapt_comp_reg;
495 * SERDES PHY requires us to read link status from undocumented
496 * register 0xC79F. Bit 0 set indicates link is up/ready; clear
497 * indicates link down. OxC00C is read to check that the XAUI lanes
498 * are active. Bit 0 clear indicates active; set indicates inactive.
500 if (hw->phy.type == ixgbe_phy_nl) {
501 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
502 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
503 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
505 if (link_up_wait_to_complete) {
506 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
507 if ((link_reg & 1) &&
508 ((adapt_comp_reg & 1) == 0)) {
515 hw->phy.ops.read_reg(hw, 0xC79F,
518 hw->phy.ops.read_reg(hw, 0xC00C,
523 if ((link_reg & 1) &&
524 ((adapt_comp_reg & 1) == 0))
530 if (*link_up == FALSE)
534 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
535 if (link_up_wait_to_complete) {
536 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
537 if (links_reg & IXGBE_LINKS_UP) {
544 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
547 if (links_reg & IXGBE_LINKS_UP)
553 if (links_reg & IXGBE_LINKS_SPEED)
554 *speed = IXGBE_LINK_SPEED_10GB_FULL;
556 *speed = IXGBE_LINK_SPEED_1GB_FULL;
558 /* if link is down, zero out the current_mode */
559 if (*link_up == FALSE) {
560 hw->fc.current_mode = ixgbe_fc_none;
561 hw->fc.fc_was_autonegged = FALSE;
564 return IXGBE_SUCCESS;
568 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
569 * @hw: pointer to hardware structure
570 * @speed: new link speed
571 * @autoneg: TRUE if autonegotiation enabled
572 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
574 * Set the link speed in the AUTOC register and restarts link.
576 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
577 ixgbe_link_speed speed, bool autoneg,
578 bool autoneg_wait_to_complete)
580 s32 status = IXGBE_SUCCESS;
581 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
582 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
583 u32 autoc = curr_autoc;
584 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
586 /* Check to see if speed passed in is supported. */
587 ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
588 speed &= link_capabilities;
590 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
591 status = IXGBE_ERR_LINK_SETUP;
593 /* Set KX4/KX support according to speed requested */
594 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
595 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
596 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
597 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
598 autoc |= IXGBE_AUTOC_KX4_SUPP;
599 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
600 autoc |= IXGBE_AUTOC_KX_SUPP;
601 if (autoc != curr_autoc)
602 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
605 if (status == IXGBE_SUCCESS) {
606 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
609 * Setup and restart the link based on the new values in
610 * ixgbe_hw This will write the AUTOC register based on the new
613 status = ixgbe_setup_mac_link_82598(hw);
621 * ixgbe_setup_copper_link_82598 - Setup copper link settings
622 * @hw: pointer to hardware structure
624 * Configures link settings based on values in the ixgbe_hw struct.
625 * Restarts the link. Performs autonegotiation if needed. Restart
626 * phy and wait for autonegotiate to finish. Then synchronize the
629 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
633 /* Restart autonegotiation on PHY */
634 status = hw->phy.ops.setup_link(hw);
637 ixgbe_setup_mac_link_82598(hw);
643 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
644 * @hw: pointer to hardware structure
645 * @speed: new link speed
646 * @autoneg: TRUE if autonegotiation enabled
647 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
649 * Sets the link speed in the AUTOC register in the MAC and restarts link.
651 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
652 ixgbe_link_speed speed,
654 bool autoneg_wait_to_complete)
658 /* Setup the PHY according to input speed */
659 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
660 autoneg_wait_to_complete);
662 ixgbe_setup_mac_link_82598(hw);
668 * ixgbe_reset_hw_82598 - Performs hardware reset
669 * @hw: pointer to hardware structure
671 * Resets the hardware by resetting the transmit and receive units, masks and
672 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
675 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
677 s32 status = IXGBE_SUCCESS;
684 /* Call adapter stop to disable tx/rx and clear interrupts */
685 hw->mac.ops.stop_adapter(hw);
688 * Power up the Atlas Tx lanes if they are currently powered down.
689 * Atlas Tx lanes are powered down for MAC loopback tests, but
690 * they are not automatically restored on reset.
692 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
693 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
694 /* Enable Tx Atlas so packets can be transmitted again */
695 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
697 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
698 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
701 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
703 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
704 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
707 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
709 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
710 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
713 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
715 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
716 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
721 if (hw->phy.reset_disable == FALSE) {
722 /* PHY ops must be identified and initialized prior to reset */
724 /* Init PHY and function pointers, perform SFP setup */
725 status = hw->phy.ops.init(hw);
726 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
729 hw->phy.ops.reset(hw);
733 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
734 * access and verify no pending requests before reset
736 status = ixgbe_disable_pcie_master(hw);
737 if (status != IXGBE_SUCCESS) {
738 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
739 DEBUGOUT("PCI-E Master disable polling has failed.\n");
743 * Issue global reset to the MAC. This needs to be a SW reset.
744 * If link reset is used, it might reset the MAC when mng is using it
746 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
747 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
748 IXGBE_WRITE_FLUSH(hw);
750 /* Poll for reset bit to self-clear indicating reset is complete */
751 for (i = 0; i < 10; i++) {
753 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
754 if (!(ctrl & IXGBE_CTRL_RST))
757 if (ctrl & IXGBE_CTRL_RST) {
758 status = IXGBE_ERR_RESET_FAILED;
759 DEBUGOUT("Reset polling failed to complete.\n");
764 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
765 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
766 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
769 * Store the original AUTOC value if it has not been
770 * stored off yet. Otherwise restore the stored original
771 * AUTOC value since the reset operation sets back to deaults.
773 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
774 if (hw->mac.orig_link_settings_stored == FALSE) {
775 hw->mac.orig_autoc = autoc;
776 hw->mac.orig_link_settings_stored = TRUE;
777 } else if (autoc != hw->mac.orig_autoc)
778 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
781 * Store MAC address from RAR0, clear receive address registers, and
782 * clear the multicast table
784 hw->mac.ops.init_rx_addrs(hw);
786 /* Store the permanent mac address */
787 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
794 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
795 * @hw: pointer to hardware struct
796 * @rar: receive address register index to associate with a VMDq index
797 * @vmdq: VMDq set index
799 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
803 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
804 rar_high &= ~IXGBE_RAH_VIND_MASK;
805 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
806 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
807 return IXGBE_SUCCESS;
811 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
812 * @hw: pointer to hardware struct
813 * @rar: receive address register index to associate with a VMDq index
814 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
816 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
819 u32 rar_entries = hw->mac.num_rar_entries;
821 UNREFERENCED_PARAMETER(vmdq);
823 if (rar < rar_entries) {
824 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
825 if (rar_high & IXGBE_RAH_VIND_MASK) {
826 rar_high &= ~IXGBE_RAH_VIND_MASK;
827 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
830 DEBUGOUT1("RAR index %d is out of range.\n", rar);
833 return IXGBE_SUCCESS;
837 * ixgbe_set_vfta_82598 - Set VLAN filter table
838 * @hw: pointer to hardware structure
839 * @vlan: VLAN id to write to VLAN filter
840 * @vind: VMDq output index that maps queue to VLAN id in VFTA
841 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
843 * Turn on/off specified VLAN in the VLAN filter table.
845 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
854 return IXGBE_ERR_PARAM;
856 /* Determine 32-bit word position in array */
857 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
859 /* Determine the location of the (VMD) queue index */
860 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
861 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
863 /* Set the nibble for VMD queue index */
864 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
865 bits &= (~(0x0F << bitindex));
866 bits |= (vind << bitindex);
867 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
869 /* Determine the location of the bit for this VLAN id */
870 bitindex = vlan & 0x1F; /* lower five bits */
872 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
874 /* Turn on this VLAN id */
875 bits |= (1 << bitindex);
877 /* Turn off this VLAN id */
878 bits &= ~(1 << bitindex);
879 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
881 return IXGBE_SUCCESS;
885 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
886 * @hw: pointer to hardware structure
888 * Clears the VLAN filer table, and the VMDq index associated with the filter
890 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
895 for (offset = 0; offset < hw->mac.vft_size; offset++)
896 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
898 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
899 for (offset = 0; offset < hw->mac.vft_size; offset++)
900 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
903 return IXGBE_SUCCESS;
907 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
908 * @hw: pointer to hardware structure
909 * @reg: analog register to read
912 * Performs read operation to Atlas analog register specified.
914 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
918 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
919 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
920 IXGBE_WRITE_FLUSH(hw);
922 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
923 *val = (u8)atlas_ctl;
925 return IXGBE_SUCCESS;
929 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
930 * @hw: pointer to hardware structure
931 * @reg: atlas register to write
932 * @val: value to write
934 * Performs write operation to Atlas analog register specified.
936 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
940 atlas_ctl = (reg << 8) | val;
941 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
942 IXGBE_WRITE_FLUSH(hw);
945 return IXGBE_SUCCESS;
949 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
950 * @hw: pointer to hardware structure
951 * @byte_offset: EEPROM byte offset to read
952 * @eeprom_data: value read
954 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
956 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
959 s32 status = IXGBE_SUCCESS;
965 if (hw->phy.type == ixgbe_phy_nl) {
967 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
968 * 0xC30D. These registers are used to talk to the SFP+
969 * module's EEPROM through the SDA/SCL (I2C) interface.
971 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
972 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
973 hw->phy.ops.write_reg(hw,
974 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
975 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
979 for (i = 0; i < 100; i++) {
980 hw->phy.ops.read_reg(hw,
981 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
982 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
984 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
985 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
990 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
991 DEBUGOUT("EEPROM read did not pass.\n");
992 status = IXGBE_ERR_SFP_NOT_PRESENT;
997 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
998 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1000 *eeprom_data = (u8)(sfp_data >> 8);
1002 status = IXGBE_ERR_PHY;
1011 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1012 * @hw: pointer to hardware structure
1014 * Determines physical layer capabilities of the current configuration.
1016 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1018 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1019 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1020 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1021 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1022 u16 ext_ability = 0;
1024 hw->phy.ops.identify(hw);
1026 /* Copper PHY must be checked before AUTOC LMS to determine correct
1027 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1028 if (hw->phy.type == ixgbe_phy_tn ||
1029 hw->phy.type == ixgbe_phy_cu_unknown) {
1030 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1031 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1032 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1033 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1034 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1035 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1036 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1037 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1041 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1042 case IXGBE_AUTOC_LMS_1G_AN:
1043 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1044 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1045 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1047 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1049 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1050 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1051 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1052 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1053 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1055 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1057 case IXGBE_AUTOC_LMS_KX4_AN:
1058 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1059 if (autoc & IXGBE_AUTOC_KX_SUPP)
1060 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1061 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1062 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1068 if (hw->phy.type == ixgbe_phy_nl) {
1069 hw->phy.ops.identify_sfp(hw);
1071 switch (hw->phy.sfp_type) {
1072 case ixgbe_sfp_type_da_cu:
1073 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1075 case ixgbe_sfp_type_sr:
1076 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1078 case ixgbe_sfp_type_lr:
1079 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1082 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1087 switch (hw->device_id) {
1088 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1089 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1091 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1092 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1093 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1094 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1096 case IXGBE_DEV_ID_82598EB_XF_LR:
1097 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1104 return physical_layer;