2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
39 #include <sys/module.h>
41 #include <sys/queue.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/if_types.h>
54 #include <net/if_vlan_var.h>
56 #include <netinet/in.h>
57 #include <netinet/in_systm.h>
58 #include <netinet/ip.h>
59 #include <netinet/tcp.h>
61 #include <dev/mii/mii.h>
62 #include <dev/mii/miivar.h>
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
67 #include <machine/atomic.h>
68 #include <machine/bus.h>
69 #include <machine/in_cksum.h>
71 #include <dev/jme/if_jmereg.h>
72 #include <dev/jme/if_jmevar.h>
74 /* "device miibus" required. See GENERIC if you get errors here. */
75 #include "miibus_if.h"
77 /* Define the following to disable printing Rx errors. */
78 #undef JME_SHOW_ERRORS
80 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
82 MODULE_DEPEND(jme, pci, 1, 1, 1);
83 MODULE_DEPEND(jme, ether, 1, 1, 1);
84 MODULE_DEPEND(jme, miibus, 1, 1, 1);
87 static int msi_disable = 0;
88 static int msix_disable = 0;
89 TUNABLE_INT("hw.jme.msi_disable", &msi_disable);
90 TUNABLE_INT("hw.jme.msix_disable", &msix_disable);
93 * Devices supported by this driver.
95 static struct jme_dev {
96 uint16_t jme_vendorid;
97 uint16_t jme_deviceid;
100 { VENDORID_JMICRON, DEVICEID_JMC250,
101 "JMicron Inc, JMC250 Gigabit Ethernet" },
102 { VENDORID_JMICRON, DEVICEID_JMC260,
103 "JMicron Inc, JMC260 Fast Ethernet" },
106 static int jme_miibus_readreg(device_t, int, int);
107 static int jme_miibus_writereg(device_t, int, int, int);
108 static void jme_miibus_statchg(device_t);
109 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
110 static int jme_mediachange(struct ifnet *);
111 static int jme_probe(device_t);
112 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
113 static int jme_eeprom_macaddr(struct jme_softc *);
114 static void jme_reg_macaddr(struct jme_softc *);
115 static void jme_map_intr_vector(struct jme_softc *);
116 static int jme_attach(device_t);
117 static int jme_detach(device_t);
118 static void jme_sysctl_node(struct jme_softc *);
119 static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int);
120 static int jme_dma_alloc(struct jme_softc *);
121 static void jme_dma_free(struct jme_softc *);
122 static int jme_shutdown(device_t);
123 static void jme_setlinkspeed(struct jme_softc *);
124 static void jme_setwol(struct jme_softc *);
125 static int jme_suspend(device_t);
126 static int jme_resume(device_t);
127 static int jme_encap(struct jme_softc *, struct mbuf **);
128 static void jme_tx_task(void *, int);
129 static void jme_start(struct ifnet *);
130 static void jme_watchdog(struct jme_softc *);
131 static int jme_ioctl(struct ifnet *, u_long, caddr_t);
132 static void jme_mac_config(struct jme_softc *);
133 static void jme_link_task(void *, int);
134 static int jme_intr(void *);
135 static void jme_int_task(void *, int);
136 static void jme_txeof(struct jme_softc *);
137 static __inline void jme_discard_rxbuf(struct jme_softc *, int);
138 static void jme_rxeof(struct jme_softc *);
139 static int jme_rxintr(struct jme_softc *, int);
140 static void jme_tick(void *);
141 static void jme_reset(struct jme_softc *);
142 static void jme_init(void *);
143 static void jme_init_locked(struct jme_softc *);
144 static void jme_stop(struct jme_softc *);
145 static void jme_stop_tx(struct jme_softc *);
146 static void jme_stop_rx(struct jme_softc *);
147 static int jme_init_rx_ring(struct jme_softc *);
148 static void jme_init_tx_ring(struct jme_softc *);
149 static void jme_init_ssb(struct jme_softc *);
150 static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *);
151 static void jme_set_vlan(struct jme_softc *);
152 static void jme_set_filter(struct jme_softc *);
153 static void jme_stats_clear(struct jme_softc *);
154 static void jme_stats_save(struct jme_softc *);
155 static void jme_stats_update(struct jme_softc *);
156 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
157 static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS);
158 static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
159 static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS);
160 static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
161 static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS);
164 static device_method_t jme_methods[] = {
165 /* Device interface. */
166 DEVMETHOD(device_probe, jme_probe),
167 DEVMETHOD(device_attach, jme_attach),
168 DEVMETHOD(device_detach, jme_detach),
169 DEVMETHOD(device_shutdown, jme_shutdown),
170 DEVMETHOD(device_suspend, jme_suspend),
171 DEVMETHOD(device_resume, jme_resume),
174 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
175 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
176 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
181 static driver_t jme_driver = {
184 sizeof(struct jme_softc)
187 static devclass_t jme_devclass;
189 DRIVER_MODULE(jme, pci, jme_driver, jme_devclass, 0, 0);
190 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0);
192 static struct resource_spec jme_res_spec_mem[] = {
193 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
197 static struct resource_spec jme_irq_spec_legacy[] = {
198 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
202 static struct resource_spec jme_irq_spec_msi[] = {
203 { SYS_RES_IRQ, 1, RF_ACTIVE },
204 { SYS_RES_IRQ, 2, RF_ACTIVE },
205 { SYS_RES_IRQ, 3, RF_ACTIVE },
206 { SYS_RES_IRQ, 4, RF_ACTIVE },
207 { SYS_RES_IRQ, 5, RF_ACTIVE },
208 { SYS_RES_IRQ, 6, RF_ACTIVE },
209 { SYS_RES_IRQ, 7, RF_ACTIVE },
210 { SYS_RES_IRQ, 8, RF_ACTIVE },
215 * Read a PHY register on the MII of the JMC250.
218 jme_miibus_readreg(device_t dev, int phy, int reg)
220 struct jme_softc *sc;
224 sc = device_get_softc(dev);
226 /* For FPGA version, PHY address 0 should be ignored. */
227 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
231 if (sc->jme_phyaddr != phy)
235 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
236 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
237 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
239 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
244 device_printf(sc->jme_dev, "phy read timeout : %d\n", reg);
248 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
252 * Write a PHY register on the MII of the JMC250.
255 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
257 struct jme_softc *sc;
260 sc = device_get_softc(dev);
262 /* For FPGA version, PHY address 0 should be ignored. */
263 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
267 if (sc->jme_phyaddr != phy)
271 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
272 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
273 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
274 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
276 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
281 device_printf(sc->jme_dev, "phy write timeout : %d\n", reg);
287 * Callback from MII layer when media changes.
290 jme_miibus_statchg(device_t dev)
292 struct jme_softc *sc;
294 sc = device_get_softc(dev);
295 taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task);
299 * Get the current interface media status.
302 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
304 struct jme_softc *sc;
305 struct mii_data *mii;
309 mii = device_get_softc(sc->jme_miibus);
312 ifmr->ifm_status = mii->mii_media_status;
313 ifmr->ifm_active = mii->mii_media_active;
318 * Set hardware to newly-selected media.
321 jme_mediachange(struct ifnet *ifp)
323 struct jme_softc *sc;
324 struct mii_data *mii;
325 struct mii_softc *miisc;
330 mii = device_get_softc(sc->jme_miibus);
331 if (mii->mii_instance != 0) {
332 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
333 mii_phy_reset(miisc);
335 error = mii_mediachg(mii);
342 jme_probe(device_t dev)
346 uint16_t vendor, devid;
348 vendor = pci_get_vendor(dev);
349 devid = pci_get_device(dev);
351 for (i = 0; i < sizeof(jme_devs) / sizeof(jme_devs[0]);
353 if (vendor == sp->jme_vendorid &&
354 devid == sp->jme_deviceid) {
355 device_set_desc(dev, sp->jme_name);
356 return (BUS_PROBE_DEFAULT);
364 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
370 for (i = JME_TIMEOUT; i > 0; i--) {
371 reg = CSR_READ_4(sc, JME_SMBCSR);
372 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
378 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
382 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
383 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
384 for (i = JME_TIMEOUT; i > 0; i--) {
386 reg = CSR_READ_4(sc, JME_SMBINTF);
387 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
392 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
396 reg = CSR_READ_4(sc, JME_SMBINTF);
397 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
403 jme_eeprom_macaddr(struct jme_softc *sc)
405 uint8_t eaddr[ETHER_ADDR_LEN];
406 uint8_t fup, reg, val;
411 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
412 fup != JME_EEPROM_SIG0)
414 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
415 fup != JME_EEPROM_SIG1)
419 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
421 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
422 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
423 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
425 if (reg >= JME_PAR0 &&
426 reg < JME_PAR0 + ETHER_ADDR_LEN) {
427 if (jme_eeprom_read_byte(sc, offset + 2,
430 eaddr[reg - JME_PAR0] = val;
434 /* Check for the end of EEPROM descriptor. */
435 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
437 /* Try next eeprom descriptor. */
438 offset += JME_EEPROM_DESC_BYTES;
439 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
441 if (match == ETHER_ADDR_LEN) {
442 bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN);
450 jme_reg_macaddr(struct jme_softc *sc)
454 /* Read station address. */
455 par0 = CSR_READ_4(sc, JME_PAR0);
456 par1 = CSR_READ_4(sc, JME_PAR1);
458 if ((par0 == 0 && par1 == 0) ||
459 (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) {
460 device_printf(sc->jme_dev,
461 "generating fake ethernet address.\n");
463 /* Set OUI to JMicron. */
464 sc->jme_eaddr[0] = 0x00;
465 sc->jme_eaddr[1] = 0x1B;
466 sc->jme_eaddr[2] = 0x8C;
467 sc->jme_eaddr[3] = (par0 >> 16) & 0xff;
468 sc->jme_eaddr[4] = (par0 >> 8) & 0xff;
469 sc->jme_eaddr[5] = par0 & 0xff;
471 sc->jme_eaddr[0] = (par0 >> 0) & 0xFF;
472 sc->jme_eaddr[1] = (par0 >> 8) & 0xFF;
473 sc->jme_eaddr[2] = (par0 >> 16) & 0xFF;
474 sc->jme_eaddr[3] = (par0 >> 24) & 0xFF;
475 sc->jme_eaddr[4] = (par1 >> 0) & 0xFF;
476 sc->jme_eaddr[5] = (par1 >> 8) & 0xFF;
481 jme_map_intr_vector(struct jme_softc *sc)
483 uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES];
485 bzero(map, sizeof(map));
487 /* Map Tx interrupts source to MSI/MSIX vector 2. */
488 map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] =
489 MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP);
490 map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |=
491 MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP);
492 map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |=
493 MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP);
494 map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |=
495 MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP);
496 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |=
497 MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP);
498 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |=
499 MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP);
500 map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |=
501 MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP);
502 map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |=
503 MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP);
504 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |=
505 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL);
506 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |=
507 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO);
509 /* Map Rx interrupts source to MSI/MSIX vector 1. */
510 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] =
511 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP);
512 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] =
513 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP);
514 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] =
515 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP);
516 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] =
517 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP);
518 map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] =
519 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY);
520 map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] =
521 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY);
522 map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] =
523 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY);
524 map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] =
525 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY);
526 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] =
527 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL);
528 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] =
529 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL);
530 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] =
531 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL);
532 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] =
533 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL);
534 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] =
535 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO);
536 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] =
537 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO);
538 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] =
539 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO);
540 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] =
541 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO);
543 /* Map all other interrupts source to MSI/MSIX vector 0. */
544 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]);
545 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]);
546 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]);
547 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]);
551 jme_attach(device_t dev)
553 struct jme_softc *sc;
555 struct mii_softc *miisc;
556 struct mii_data *mii;
559 int error, i, msic, msixc, pmc;
562 sc = device_get_softc(dev);
565 mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
567 callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0);
568 TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc);
569 TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc);
572 * Map the device. JMC250 supports both memory mapped and I/O
573 * register space access. Because I/O register access should
574 * use different BARs to access registers it's waste of time
575 * to use I/O register spce access. JMC250 uses 16K to map
576 * entire memory space.
578 pci_enable_busmaster(dev);
579 sc->jme_res_spec = jme_res_spec_mem;
580 sc->jme_irq_spec = jme_irq_spec_legacy;
581 error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res);
583 device_printf(dev, "cannot allocate memory resources.\n");
587 /* Allocate IRQ resources. */
588 msixc = pci_msix_count(dev);
589 msic = pci_msi_count(dev);
591 device_printf(dev, "MSIX count : %d\n", msixc);
592 device_printf(dev, "MSI count : %d\n", msic);
595 /* Prefer MSIX over MSI. */
596 if (msix_disable == 0 || msi_disable == 0) {
597 if (msix_disable == 0 && msixc == JME_MSIX_MESSAGES &&
598 pci_alloc_msix(dev, &msixc) == 0) {
599 if (msic == JME_MSIX_MESSAGES) {
600 device_printf(dev, "Using %d MSIX messages.\n",
602 sc->jme_flags |= JME_FLAG_MSIX;
603 sc->jme_irq_spec = jme_irq_spec_msi;
605 pci_release_msi(dev);
607 if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 &&
608 msic == JME_MSI_MESSAGES &&
609 pci_alloc_msi(dev, &msic) == 0) {
610 if (msic == JME_MSI_MESSAGES) {
611 device_printf(dev, "Using %d MSI messages.\n",
613 sc->jme_flags |= JME_FLAG_MSI;
614 sc->jme_irq_spec = jme_irq_spec_msi;
616 pci_release_msi(dev);
618 /* Map interrupt vector 0, 1 and 2. */
619 if ((sc->jme_flags & JME_FLAG_MSI) != 0 ||
620 (sc->jme_flags & JME_FLAG_MSIX) != 0)
621 jme_map_intr_vector(sc);
624 error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq);
626 device_printf(dev, "cannot allocate IRQ resources.\n");
630 sc->jme_rev = pci_get_device(dev);
631 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) {
632 sc->jme_flags |= JME_FLAG_FASTETH;
633 sc->jme_flags |= JME_FLAG_NOJUMBO;
635 reg = CSR_READ_4(sc, JME_CHIPMODE);
636 sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT;
637 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
639 sc->jme_flags |= JME_FLAG_FPGA;
641 device_printf(dev, "PCI device revision : 0x%04x\n",
643 device_printf(dev, "Chip revision : 0x%02x\n",
645 if ((sc->jme_flags & JME_FLAG_FPGA) != 0)
646 device_printf(dev, "FPGA revision : 0x%04x\n",
647 (reg & CHIPMODE_FPGA_REV_MASK) >>
648 CHIPMODE_FPGA_REV_SHIFT);
650 if (sc->jme_chip_rev == 0xFF) {
651 device_printf(dev, "Unknown chip revision : 0x%02x\n",
657 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) {
658 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 &&
659 CHIPMODE_REVFM(sc->jme_chip_rev) == 2)
660 sc->jme_flags |= JME_FLAG_DMA32BIT;
661 sc->jme_flags |= JME_FLAG_TXCLK;
662 sc->jme_flags |= JME_FLAG_HWMIB;
665 /* Reset the ethernet controller. */
668 /* Get station address. */
669 reg = CSR_READ_4(sc, JME_SMBCSR);
670 if ((reg & SMBCSR_EEPROM_PRESENT) != 0)
671 error = jme_eeprom_macaddr(sc);
672 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
673 if (error != 0 && (bootverbose))
674 device_printf(sc->jme_dev,
675 "ethernet hardware address not found in EEPROM.\n");
681 * Integrated JR0211 has fixed PHY address whereas FPGA version
682 * requires PHY probing to get correct PHY address.
684 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) {
685 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
686 GPREG0_PHY_ADDR_MASK;
688 device_printf(dev, "PHY is at address %d.\n",
693 /* Set max allowable DMA size. */
694 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
695 sc->jme_flags |= JME_FLAG_PCIE;
696 burst = pci_read_config(dev, i + 0x08, 2);
698 device_printf(dev, "Read request size : %d bytes.\n",
699 128 << ((burst >> 12) & 0x07));
700 device_printf(dev, "TLP payload size : %d bytes.\n",
701 128 << ((burst >> 5) & 0x07));
703 switch ((burst >> 12) & 0x07) {
705 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
708 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
711 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
714 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
716 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
717 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
719 /* Create coalescing sysctl node. */
721 if ((error = jme_dma_alloc(sc) != 0))
724 ifp = sc->jme_ifp = if_alloc(IFT_ETHER);
726 device_printf(dev, "cannot allocate ifnet structure.\n");
732 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
733 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
734 ifp->if_ioctl = jme_ioctl;
735 ifp->if_start = jme_start;
736 ifp->if_init = jme_init;
737 ifp->if_snd.ifq_drv_maxlen = JME_TX_RING_CNT - 1;
738 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
739 IFQ_SET_READY(&ifp->if_snd);
740 /* JMC250 supports Tx/Rx checksum offload as well as TSO. */
741 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
742 ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO;
743 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
744 sc->jme_flags |= JME_FLAG_PMCAP;
745 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
747 ifp->if_capenable = ifp->if_capabilities;
749 /* Set up MII bus. */
750 if ((error = mii_phy_probe(dev, &sc->jme_miibus, jme_mediachange,
751 jme_mediastatus)) != 0) {
752 device_printf(dev, "no PHY found!\n");
757 * Force PHY to FPGA mode.
759 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
760 mii = device_get_softc(sc->jme_miibus);
761 if (mii->mii_instance != 0) {
762 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
763 if (miisc->mii_phy != 0) {
764 sc->jme_phyaddr = miisc->mii_phy;
768 if (sc->jme_phyaddr != 0) {
769 device_printf(sc->jme_dev,
770 "FPGA PHY is at %d\n", sc->jme_phyaddr);
772 jme_miibus_writereg(dev, sc->jme_phyaddr, 27,
778 ether_ifattach(ifp, sc->jme_eaddr);
780 /* VLAN capability setup */
781 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
783 ifp->if_capenable = ifp->if_capabilities;
785 /* Tell the upper layer(s) we support long frames. */
786 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
788 /* Create local taskq. */
789 TASK_INIT(&sc->jme_tx_task, 1, jme_tx_task, ifp);
790 sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK,
791 taskqueue_thread_enqueue, &sc->jme_tq);
792 if (sc->jme_tq == NULL) {
793 device_printf(dev, "could not create taskqueue.\n");
798 taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq",
799 device_get_nameunit(sc->jme_dev));
801 if ((sc->jme_flags & JME_FLAG_MSIX) != 0)
802 msic = JME_MSIX_MESSAGES;
803 else if ((sc->jme_flags & JME_FLAG_MSI) != 0)
804 msic = JME_MSI_MESSAGES;
807 for (i = 0; i < msic; i++) {
808 error = bus_setup_intr(dev, sc->jme_irq[i],
809 INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc,
810 &sc->jme_intrhand[i]);
816 device_printf(dev, "could not set up interrupt handler.\n");
817 taskqueue_free(sc->jme_tq);
831 jme_detach(device_t dev)
833 struct jme_softc *sc;
837 sc = device_get_softc(dev);
840 if (device_is_attached(dev)) {
842 sc->jme_flags |= JME_FLAG_DETACH;
845 callout_drain(&sc->jme_tick_ch);
846 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
847 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task);
848 taskqueue_drain(taskqueue_swi, &sc->jme_link_task);
852 if (sc->jme_tq != NULL) {
853 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
854 taskqueue_free(sc->jme_tq);
858 if (sc->jme_miibus != NULL) {
859 device_delete_child(dev, sc->jme_miibus);
860 sc->jme_miibus = NULL;
862 bus_generic_detach(dev);
871 if ((sc->jme_flags & JME_FLAG_MSIX) != 0)
872 msic = JME_MSIX_MESSAGES;
873 else if ((sc->jme_flags & JME_FLAG_MSI) != 0)
874 msic = JME_MSI_MESSAGES;
877 for (i = 0; i < msic; i++) {
878 if (sc->jme_intrhand[i] != NULL) {
879 bus_teardown_intr(dev, sc->jme_irq[i],
880 sc->jme_intrhand[i]);
881 sc->jme_intrhand[i] = NULL;
885 bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq);
886 if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0)
887 pci_release_msi(dev);
888 bus_release_resources(dev, sc->jme_res_spec, sc->jme_res);
889 mtx_destroy(&sc->jme_mtx);
894 #define JME_SYSCTL_STAT_ADD32(c, h, n, p, d) \
895 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
898 jme_sysctl_node(struct jme_softc *sc)
900 struct sysctl_ctx_list *ctx;
901 struct sysctl_oid_list *child, *parent;
902 struct sysctl_oid *tree;
903 struct jme_hw_stats *stats;
906 stats = &sc->jme_stats;
907 ctx = device_get_sysctl_ctx(sc->jme_dev);
908 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev));
910 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to",
911 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to, 0,
912 sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout");
914 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt",
915 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt, 0,
916 sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet");
918 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to",
919 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to, 0,
920 sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout");
922 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt",
923 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt, 0,
924 sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet");
926 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
927 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_process_limit, 0,
928 sysctl_hw_jme_proc_limit, "I",
929 "max number of Rx events to process");
931 /* Pull in device tunables. */
932 sc->jme_process_limit = JME_PROC_DEFAULT;
933 error = resource_int_value(device_get_name(sc->jme_dev),
934 device_get_unit(sc->jme_dev), "process_limit",
935 &sc->jme_process_limit);
937 if (sc->jme_process_limit < JME_PROC_MIN ||
938 sc->jme_process_limit > JME_PROC_MAX) {
939 device_printf(sc->jme_dev,
940 "process_limit value out of range; "
941 "using default: %d\n", JME_PROC_DEFAULT);
942 sc->jme_process_limit = JME_PROC_DEFAULT;
946 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
947 error = resource_int_value(device_get_name(sc->jme_dev),
948 device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to);
950 if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN ||
951 sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) {
952 device_printf(sc->jme_dev,
953 "tx_coal_to value out of range; "
954 "using default: %d\n", PCCTX_COAL_TO_DEFAULT);
955 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
959 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
960 error = resource_int_value(device_get_name(sc->jme_dev),
961 device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to);
963 if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN ||
964 sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) {
965 device_printf(sc->jme_dev,
966 "tx_coal_pkt value out of range; "
967 "using default: %d\n", PCCTX_COAL_PKT_DEFAULT);
968 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
972 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
973 error = resource_int_value(device_get_name(sc->jme_dev),
974 device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to);
976 if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN ||
977 sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) {
978 device_printf(sc->jme_dev,
979 "rx_coal_to value out of range; "
980 "using default: %d\n", PCCRX_COAL_TO_DEFAULT);
981 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
985 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
986 error = resource_int_value(device_get_name(sc->jme_dev),
987 device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to);
989 if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN ||
990 sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) {
991 device_printf(sc->jme_dev,
992 "tx_coal_pkt value out of range; "
993 "using default: %d\n", PCCRX_COAL_PKT_DEFAULT);
994 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
998 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
1001 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
1002 NULL, "JME statistics");
1003 parent = SYSCTL_CHILDREN(tree);
1005 /* Rx statistics. */
1006 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
1007 NULL, "Rx MAC statistics");
1008 child = SYSCTL_CHILDREN(tree);
1009 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1010 &stats->rx_good_frames, "Good frames");
1011 JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
1012 &stats->rx_crc_errs, "CRC errors");
1013 JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs",
1014 &stats->rx_mii_errs, "MII errors");
1015 JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
1016 &stats->rx_fifo_oflows, "FIFO overflows");
1017 JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty",
1018 &stats->rx_desc_empty, "Descriptor empty");
1019 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
1020 &stats->rx_bad_frames, "Bad frames");
1022 /* Tx statistics. */
1023 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
1024 NULL, "Tx MAC statistics");
1025 child = SYSCTL_CHILDREN(tree);
1026 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1027 &stats->tx_good_frames, "Good frames");
1028 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
1029 &stats->tx_bad_frames, "Bad frames");
1032 #undef JME_SYSCTL_STAT_ADD32
1034 struct jme_dmamap_arg {
1035 bus_addr_t jme_busaddr;
1039 jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1041 struct jme_dmamap_arg *ctx;
1046 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1048 ctx = (struct jme_dmamap_arg *)arg;
1049 ctx->jme_busaddr = segs[0].ds_addr;
1053 jme_dma_alloc(struct jme_softc *sc)
1055 struct jme_dmamap_arg ctx;
1056 struct jme_txdesc *txd;
1057 struct jme_rxdesc *rxd;
1058 bus_addr_t lowaddr, rx_ring_end, tx_ring_end;
1061 lowaddr = BUS_SPACE_MAXADDR;
1062 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
1063 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1066 /* Create parent ring tag. */
1067 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
1068 1, 0, /* algnmnt, boundary */
1069 lowaddr, /* lowaddr */
1070 BUS_SPACE_MAXADDR, /* highaddr */
1071 NULL, NULL, /* filter, filterarg */
1072 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1074 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1076 NULL, NULL, /* lockfunc, lockarg */
1077 &sc->jme_cdata.jme_ring_tag);
1079 device_printf(sc->jme_dev,
1080 "could not create parent ring DMA tag.\n");
1083 /* Create tag for Tx ring. */
1084 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1085 JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */
1086 BUS_SPACE_MAXADDR, /* lowaddr */
1087 BUS_SPACE_MAXADDR, /* highaddr */
1088 NULL, NULL, /* filter, filterarg */
1089 JME_TX_RING_SIZE, /* maxsize */
1091 JME_TX_RING_SIZE, /* maxsegsize */
1093 NULL, NULL, /* lockfunc, lockarg */
1094 &sc->jme_cdata.jme_tx_ring_tag);
1096 device_printf(sc->jme_dev,
1097 "could not allocate Tx ring DMA tag.\n");
1101 /* Create tag for Rx ring. */
1102 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1103 JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */
1104 lowaddr, /* lowaddr */
1105 BUS_SPACE_MAXADDR, /* highaddr */
1106 NULL, NULL, /* filter, filterarg */
1107 JME_RX_RING_SIZE, /* maxsize */
1109 JME_RX_RING_SIZE, /* maxsegsize */
1111 NULL, NULL, /* lockfunc, lockarg */
1112 &sc->jme_cdata.jme_rx_ring_tag);
1114 device_printf(sc->jme_dev,
1115 "could not allocate Rx ring DMA tag.\n");
1119 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1120 error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag,
1121 (void **)&sc->jme_rdata.jme_tx_ring,
1122 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1123 &sc->jme_cdata.jme_tx_ring_map);
1125 device_printf(sc->jme_dev,
1126 "could not allocate DMA'able memory for Tx ring.\n");
1130 ctx.jme_busaddr = 0;
1131 error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag,
1132 sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring,
1133 JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1134 if (error != 0 || ctx.jme_busaddr == 0) {
1135 device_printf(sc->jme_dev,
1136 "could not load DMA'able memory for Tx ring.\n");
1139 sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr;
1141 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1142 error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag,
1143 (void **)&sc->jme_rdata.jme_rx_ring,
1144 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1145 &sc->jme_cdata.jme_rx_ring_map);
1147 device_printf(sc->jme_dev,
1148 "could not allocate DMA'able memory for Rx ring.\n");
1152 ctx.jme_busaddr = 0;
1153 error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag,
1154 sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring,
1155 JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1156 if (error != 0 || ctx.jme_busaddr == 0) {
1157 device_printf(sc->jme_dev,
1158 "could not load DMA'able memory for Rx ring.\n");
1161 sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr;
1163 if (lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1164 /* Tx/Rx descriptor queue should reside within 4GB boundary. */
1165 tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr +
1167 rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr +
1169 if ((JME_ADDR_HI(tx_ring_end) !=
1170 JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) ||
1171 (JME_ADDR_HI(rx_ring_end) !=
1172 JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) {
1173 device_printf(sc->jme_dev, "4GB boundary crossed, "
1174 "switching to 32bit DMA address mode.\n");
1176 /* Limit DMA address space to 32bit and try again. */
1177 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1182 lowaddr = BUS_SPACE_MAXADDR;
1183 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
1184 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1185 /* Create parent buffer tag. */
1186 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
1187 1, 0, /* algnmnt, boundary */
1188 lowaddr, /* lowaddr */
1189 BUS_SPACE_MAXADDR, /* highaddr */
1190 NULL, NULL, /* filter, filterarg */
1191 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1193 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1195 NULL, NULL, /* lockfunc, lockarg */
1196 &sc->jme_cdata.jme_buffer_tag);
1198 device_printf(sc->jme_dev,
1199 "could not create parent buffer DMA tag.\n");
1203 /* Create shadow status block tag. */
1204 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1205 JME_SSB_ALIGN, 0, /* algnmnt, boundary */
1206 BUS_SPACE_MAXADDR, /* lowaddr */
1207 BUS_SPACE_MAXADDR, /* highaddr */
1208 NULL, NULL, /* filter, filterarg */
1209 JME_SSB_SIZE, /* maxsize */
1211 JME_SSB_SIZE, /* maxsegsize */
1213 NULL, NULL, /* lockfunc, lockarg */
1214 &sc->jme_cdata.jme_ssb_tag);
1216 device_printf(sc->jme_dev,
1217 "could not create shared status block DMA tag.\n");
1221 /* Create tag for Tx buffers. */
1222 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1223 1, 0, /* algnmnt, boundary */
1224 BUS_SPACE_MAXADDR, /* lowaddr */
1225 BUS_SPACE_MAXADDR, /* highaddr */
1226 NULL, NULL, /* filter, filterarg */
1227 JME_TSO_MAXSIZE, /* maxsize */
1228 JME_MAXTXSEGS, /* nsegments */
1229 JME_TSO_MAXSEGSIZE, /* maxsegsize */
1231 NULL, NULL, /* lockfunc, lockarg */
1232 &sc->jme_cdata.jme_tx_tag);
1234 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1238 /* Create tag for Rx buffers. */
1239 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1240 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
1241 BUS_SPACE_MAXADDR, /* lowaddr */
1242 BUS_SPACE_MAXADDR, /* highaddr */
1243 NULL, NULL, /* filter, filterarg */
1244 MCLBYTES, /* maxsize */
1246 MCLBYTES, /* maxsegsize */
1248 NULL, NULL, /* lockfunc, lockarg */
1249 &sc->jme_cdata.jme_rx_tag);
1251 device_printf(sc->jme_dev, "could not create Rx DMA tag.\n");
1256 * Allocate DMA'able memory and load the DMA map for shared
1259 error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag,
1260 (void **)&sc->jme_rdata.jme_ssb_block,
1261 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1262 &sc->jme_cdata.jme_ssb_map);
1264 device_printf(sc->jme_dev, "could not allocate DMA'able "
1265 "memory for shared status block.\n");
1269 ctx.jme_busaddr = 0;
1270 error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag,
1271 sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block,
1272 JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1273 if (error != 0 || ctx.jme_busaddr == 0) {
1274 device_printf(sc->jme_dev, "could not load DMA'able memory "
1275 "for shared status block.\n");
1278 sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr;
1280 /* Create DMA maps for Tx buffers. */
1281 for (i = 0; i < JME_TX_RING_CNT; i++) {
1282 txd = &sc->jme_cdata.jme_txdesc[i];
1284 txd->tx_dmamap = NULL;
1285 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0,
1288 device_printf(sc->jme_dev,
1289 "could not create Tx dmamap.\n");
1293 /* Create DMA maps for Rx buffers. */
1294 if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1295 &sc->jme_cdata.jme_rx_sparemap)) != 0) {
1296 device_printf(sc->jme_dev,
1297 "could not create spare Rx dmamap.\n");
1300 for (i = 0; i < JME_RX_RING_CNT; i++) {
1301 rxd = &sc->jme_cdata.jme_rxdesc[i];
1303 rxd->rx_dmamap = NULL;
1304 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1307 device_printf(sc->jme_dev,
1308 "could not create Rx dmamap.\n");
1318 jme_dma_free(struct jme_softc *sc)
1320 struct jme_txdesc *txd;
1321 struct jme_rxdesc *rxd;
1325 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1326 if (sc->jme_cdata.jme_tx_ring_map)
1327 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1328 sc->jme_cdata.jme_tx_ring_map);
1329 if (sc->jme_cdata.jme_tx_ring_map &&
1330 sc->jme_rdata.jme_tx_ring)
1331 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1332 sc->jme_rdata.jme_tx_ring,
1333 sc->jme_cdata.jme_tx_ring_map);
1334 sc->jme_rdata.jme_tx_ring = NULL;
1335 sc->jme_cdata.jme_tx_ring_map = NULL;
1336 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1337 sc->jme_cdata.jme_tx_ring_tag = NULL;
1340 if (sc->jme_cdata.jme_rx_ring_tag != NULL) {
1341 if (sc->jme_cdata.jme_rx_ring_map)
1342 bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag,
1343 sc->jme_cdata.jme_rx_ring_map);
1344 if (sc->jme_cdata.jme_rx_ring_map &&
1345 sc->jme_rdata.jme_rx_ring)
1346 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag,
1347 sc->jme_rdata.jme_rx_ring,
1348 sc->jme_cdata.jme_rx_ring_map);
1349 sc->jme_rdata.jme_rx_ring = NULL;
1350 sc->jme_cdata.jme_rx_ring_map = NULL;
1351 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1352 sc->jme_cdata.jme_rx_ring_tag = NULL;
1355 if (sc->jme_cdata.jme_tx_tag != NULL) {
1356 for (i = 0; i < JME_TX_RING_CNT; i++) {
1357 txd = &sc->jme_cdata.jme_txdesc[i];
1358 if (txd->tx_dmamap != NULL) {
1359 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1361 txd->tx_dmamap = NULL;
1364 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1365 sc->jme_cdata.jme_tx_tag = NULL;
1368 if (sc->jme_cdata.jme_rx_tag != NULL) {
1369 for (i = 0; i < JME_RX_RING_CNT; i++) {
1370 rxd = &sc->jme_cdata.jme_rxdesc[i];
1371 if (rxd->rx_dmamap != NULL) {
1372 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1374 rxd->rx_dmamap = NULL;
1377 if (sc->jme_cdata.jme_rx_sparemap != NULL) {
1378 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1379 sc->jme_cdata.jme_rx_sparemap);
1380 sc->jme_cdata.jme_rx_sparemap = NULL;
1382 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1383 sc->jme_cdata.jme_rx_tag = NULL;
1386 /* Shared status block. */
1387 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1388 if (sc->jme_cdata.jme_ssb_map)
1389 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1390 sc->jme_cdata.jme_ssb_map);
1391 if (sc->jme_cdata.jme_ssb_map && sc->jme_rdata.jme_ssb_block)
1392 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1393 sc->jme_rdata.jme_ssb_block,
1394 sc->jme_cdata.jme_ssb_map);
1395 sc->jme_rdata.jme_ssb_block = NULL;
1396 sc->jme_cdata.jme_ssb_map = NULL;
1397 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1398 sc->jme_cdata.jme_ssb_tag = NULL;
1401 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1402 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1403 sc->jme_cdata.jme_buffer_tag = NULL;
1405 if (sc->jme_cdata.jme_ring_tag != NULL) {
1406 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1407 sc->jme_cdata.jme_ring_tag = NULL;
1412 * Make sure the interface is stopped at reboot time.
1415 jme_shutdown(device_t dev)
1418 return (jme_suspend(dev));
1422 * Unlike other ethernet controllers, JMC250 requires
1423 * explicit resetting link speed to 10/100Mbps as gigabit
1424 * link will cunsume more power than 375mA.
1425 * Note, we reset the link speed to 10/100Mbps with
1426 * auto-negotiation but we don't know whether that operation
1427 * would succeed or not as we have no control after powering
1428 * off. If the renegotiation fail WOL may not work. Running
1429 * at 1Gbps draws more power than 375mA at 3.3V which is
1430 * specified in PCI specification and that would result in
1431 * complete shutdowning power to ethernet controller.
1434 * Save current negotiated media speed/duplex/flow-control
1435 * to softc and restore the same link again after resuming.
1436 * PHY handling such as power down/resetting to 100Mbps
1437 * may be better handled in suspend method in phy driver.
1440 jme_setlinkspeed(struct jme_softc *sc)
1442 struct mii_data *mii;
1445 JME_LOCK_ASSERT(sc);
1447 mii = device_get_softc(sc->jme_miibus);
1450 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1451 switch IFM_SUBTYPE(mii->mii_media_active) {
1461 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1462 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1463 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1464 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1465 BMCR_AUTOEN | BMCR_STARTNEG);
1468 /* Poll link state until jme(4) get a 10/100 link. */
1469 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1471 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1472 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1482 pause("jmelnk", hz);
1485 if (i == MII_ANEGTICKS_GIGE)
1486 device_printf(sc->jme_dev, "establishing link failed, "
1487 "WOL may not work!");
1490 * No link, force MAC to have 100Mbps, full-duplex link.
1491 * This is the last resort and may/may not work.
1493 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1494 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1499 jme_setwol(struct jme_softc *sc)
1506 JME_LOCK_ASSERT(sc);
1508 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1509 /* Remove Tx MAC/offload clock to save more power. */
1510 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1511 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1512 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1513 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
1514 /* No PME capability, PHY power down. */
1515 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1516 MII_BMCR, BMCR_PDOWN);
1521 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1522 pmcs = CSR_READ_4(sc, JME_PMCS);
1523 pmcs &= ~PMCS_WOL_ENB_MASK;
1524 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1525 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1526 /* Enable PME message. */
1527 gpr |= GPREG0_PME_ENB;
1528 /* For gigabit controllers, reset link speed to 10/100. */
1529 if ((sc->jme_flags & JME_FLAG_FASTETH) == 0)
1530 jme_setlinkspeed(sc);
1533 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1534 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1535 /* Remove Tx MAC/offload clock to save more power. */
1536 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1537 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1538 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1539 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
1541 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1542 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1543 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1544 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1545 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1546 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1547 /* No WOL, PHY power down. */
1548 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1549 MII_BMCR, BMCR_PDOWN);
1554 jme_suspend(device_t dev)
1556 struct jme_softc *sc;
1558 sc = device_get_softc(dev);
1569 jme_resume(device_t dev)
1571 struct jme_softc *sc;
1576 sc = device_get_softc(dev);
1579 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1580 pmstat = pci_read_config(sc->jme_dev,
1581 pmc + PCIR_POWER_STATUS, 2);
1582 /* Disable PME clear PME status. */
1583 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1584 pci_write_config(sc->jme_dev,
1585 pmc + PCIR_POWER_STATUS, pmstat, 2);
1588 if ((ifp->if_flags & IFF_UP) != 0)
1589 jme_init_locked(sc);
1597 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1599 struct jme_txdesc *txd;
1600 struct jme_desc *desc;
1602 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1603 int error, i, nsegs, prod;
1604 uint32_t cflags, tso_segsz;
1606 JME_LOCK_ASSERT(sc);
1608 M_ASSERTPKTHDR((*m_head));
1610 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1612 * Due to the adherence to NDIS specification JMC250
1613 * assumes upper stack computed TCP pseudo checksum
1614 * without including payload length. This breaks
1615 * checksum offload for TSO case so recompute TCP
1616 * pseudo checksum for JMC250. Hopefully this wouldn't
1617 * be much burden on modern CPUs.
1619 struct ether_header *eh;
1622 uint32_t ip_off, poff;
1624 if (M_WRITABLE(*m_head) == 0) {
1625 /* Get a writable copy. */
1626 m = m_dup(*m_head, M_DONTWAIT);
1634 ip_off = sizeof(struct ether_header);
1635 m = m_pullup(*m_head, ip_off);
1640 eh = mtod(m, struct ether_header *);
1641 /* Check the existence of VLAN tag. */
1642 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1643 ip_off = sizeof(struct ether_vlan_header);
1644 m = m_pullup(m, ip_off);
1650 m = m_pullup(m, ip_off + sizeof(struct ip));
1655 ip = (struct ip *)(mtod(m, char *) + ip_off);
1656 poff = ip_off + (ip->ip_hl << 2);
1657 m = m_pullup(m, poff + sizeof(struct tcphdr));
1662 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1664 * Reset IP checksum and recompute TCP pseudo
1665 * checksum that NDIS specification requires.
1668 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) {
1669 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1671 htons((tcp->th_off << 2) + IPPROTO_TCP));
1672 /* No need to TSO, force IP checksum offload. */
1673 (*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO;
1674 (*m_head)->m_pkthdr.csum_flags |= CSUM_IP;
1676 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1677 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1681 prod = sc->jme_cdata.jme_tx_prod;
1682 txd = &sc->jme_cdata.jme_txdesc[prod];
1684 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag,
1685 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1686 if (error == EFBIG) {
1687 m = m_collapse(*m_head, M_DONTWAIT, JME_MAXTXSEGS);
1694 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag,
1695 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1701 } else if (error != 0)
1710 * Check descriptor overrun. Leave one free descriptor.
1711 * Since we always use 64bit address mode for transmitting,
1712 * each Tx request requires one more dummy descriptor.
1714 if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) {
1715 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
1722 /* Configure checksum offload and TSO. */
1723 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1724 tso_segsz = (uint32_t)m->m_pkthdr.tso_segsz <<
1726 cflags |= JME_TD_TSO;
1728 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
1729 cflags |= JME_TD_IPCSUM;
1730 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1731 cflags |= JME_TD_TCPCSUM;
1732 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1733 cflags |= JME_TD_UDPCSUM;
1735 /* Configure VLAN. */
1736 if ((m->m_flags & M_VLANTAG) != 0) {
1737 cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK);
1738 cflags |= JME_TD_VLAN_TAG;
1741 desc = &sc->jme_rdata.jme_tx_ring[prod];
1742 desc->flags = htole32(cflags);
1743 desc->buflen = htole32(tso_segsz);
1744 desc->addr_hi = htole32(m->m_pkthdr.len);
1746 sc->jme_cdata.jme_tx_cnt++;
1747 JME_DESC_INC(prod, JME_TX_RING_CNT);
1748 for (i = 0; i < nsegs; i++) {
1749 desc = &sc->jme_rdata.jme_tx_ring[prod];
1750 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT);
1751 desc->buflen = htole32(txsegs[i].ds_len);
1752 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1753 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1754 sc->jme_cdata.jme_tx_cnt++;
1755 JME_DESC_INC(prod, JME_TX_RING_CNT);
1758 /* Update producer index. */
1759 sc->jme_cdata.jme_tx_prod = prod;
1761 * Finally request interrupt and give the first descriptor
1762 * owenership to hardware.
1764 desc = txd->tx_desc;
1765 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1768 txd->tx_ndesc = nsegs + 1;
1770 /* Sync descriptors. */
1771 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1772 BUS_DMASYNC_PREWRITE);
1773 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
1774 sc->jme_cdata.jme_tx_ring_map,
1775 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1781 jme_tx_task(void *arg, int pending)
1785 ifp = (struct ifnet *)arg;
1790 jme_start(struct ifnet *ifp)
1792 struct jme_softc *sc;
1793 struct mbuf *m_head;
1800 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT)
1803 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1804 IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0) {
1809 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1810 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1814 * Pack the data into the transmit ring. If we
1815 * don't have room, set the OACTIVE flag and wait
1816 * for the NIC to drain the ring.
1818 if (jme_encap(sc, &m_head)) {
1821 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1822 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1828 * If there's a BPF listener, bounce a copy of this frame
1831 ETHER_BPF_MTAP(ifp, m_head);
1836 * Reading TXCSR takes very long time under heavy load
1837 * so cache TXCSR value and writes the ORed value with
1838 * the kick command to the TXCSR. This saves one register
1841 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1842 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1843 /* Set a timeout in case the chip goes out to lunch. */
1844 sc->jme_watchdog_timer = JME_TX_TIMEOUT;
1851 jme_watchdog(struct jme_softc *sc)
1855 JME_LOCK_ASSERT(sc);
1857 if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer)
1861 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1862 if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n");
1864 jme_init_locked(sc);
1868 if (sc->jme_cdata.jme_tx_cnt == 0) {
1869 if_printf(sc->jme_ifp,
1870 "watchdog timeout (missed Tx interrupts) -- recovering\n");
1871 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1872 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
1876 if_printf(sc->jme_ifp, "watchdog timeout\n");
1878 jme_init_locked(sc);
1879 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1880 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
1884 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1886 struct jme_softc *sc;
1888 struct mii_data *mii;
1893 ifr = (struct ifreq *)data;
1897 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1898 ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 &&
1899 ifr->ifr_mtu > JME_MAX_MTU)) {
1904 if (ifp->if_mtu != ifr->ifr_mtu) {
1906 * No special configuration is required when interface
1907 * MTU is changed but availability of TSO/Tx checksum
1908 * offload should be chcked against new MTU size as
1909 * FIFO size is just 2K.
1912 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1913 ifp->if_capenable &=
1914 ~(IFCAP_TXCSUM | IFCAP_TSO4);
1916 ~(JME_CSUM_FEATURES | CSUM_TSO);
1917 VLAN_CAPABILITIES(ifp);
1919 ifp->if_mtu = ifr->ifr_mtu;
1920 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1921 jme_init_locked(sc);
1927 if ((ifp->if_flags & IFF_UP) != 0) {
1928 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1929 if (((ifp->if_flags ^ sc->jme_if_flags)
1930 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1933 if ((sc->jme_flags & JME_FLAG_DETACH) == 0)
1934 jme_init_locked(sc);
1937 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1940 sc->jme_if_flags = ifp->if_flags;
1946 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1952 mii = device_get_softc(sc->jme_miibus);
1953 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1957 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1958 if ((mask & IFCAP_TXCSUM) != 0 &&
1959 ifp->if_mtu < JME_TX_FIFO_SIZE) {
1960 if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1961 ifp->if_capenable ^= IFCAP_TXCSUM;
1962 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
1963 ifp->if_hwassist |= JME_CSUM_FEATURES;
1965 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1968 if ((mask & IFCAP_RXCSUM) != 0 &&
1969 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) {
1970 ifp->if_capenable ^= IFCAP_RXCSUM;
1971 reg = CSR_READ_4(sc, JME_RXMAC);
1972 reg &= ~RXMAC_CSUM_ENB;
1973 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1974 reg |= RXMAC_CSUM_ENB;
1975 CSR_WRITE_4(sc, JME_RXMAC, reg);
1977 if ((mask & IFCAP_TSO4) != 0 &&
1978 ifp->if_mtu < JME_TX_FIFO_SIZE) {
1979 if ((IFCAP_TSO4 & ifp->if_capabilities) != 0) {
1980 ifp->if_capenable ^= IFCAP_TSO4;
1981 if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
1982 ifp->if_hwassist |= CSUM_TSO;
1984 ifp->if_hwassist &= ~CSUM_TSO;
1987 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1988 (IFCAP_WOL_MAGIC & ifp->if_capabilities) != 0)
1989 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1990 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1991 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
1992 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1993 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1994 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) {
1995 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1999 VLAN_CAPABILITIES(ifp);
2002 error = ether_ioctl(ifp, cmd, data);
2010 jme_mac_config(struct jme_softc *sc)
2012 struct mii_data *mii;
2013 uint32_t ghc, gpreg, rxmac, txmac, txpause;
2016 JME_LOCK_ASSERT(sc);
2018 mii = device_get_softc(sc->jme_miibus);
2020 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2022 CSR_WRITE_4(sc, JME_GHC, 0);
2025 rxmac = CSR_READ_4(sc, JME_RXMAC);
2026 rxmac &= ~RXMAC_FC_ENB;
2027 txmac = CSR_READ_4(sc, JME_TXMAC);
2028 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
2029 txpause = CSR_READ_4(sc, JME_TXPFC);
2030 txpause &= ~TXPFC_PAUSE_ENB;
2031 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2032 ghc |= GHC_FULL_DUPLEX;
2033 rxmac &= ~RXMAC_COLL_DET_ENB;
2034 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
2035 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
2038 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2039 txpause |= TXPFC_PAUSE_ENB;
2040 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2041 rxmac |= RXMAC_FC_ENB;
2043 /* Disable retry transmit timer/retry limit. */
2044 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
2045 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
2047 rxmac |= RXMAC_COLL_DET_ENB;
2048 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
2049 /* Enable retry transmit timer/retry limit. */
2050 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
2051 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
2053 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */
2054 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2056 ghc |= GHC_SPEED_10;
2057 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
2060 ghc |= GHC_SPEED_100;
2061 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
2064 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0)
2066 ghc |= GHC_SPEED_1000;
2067 txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000;
2068 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
2069 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
2074 if (sc->jme_rev == DEVICEID_JMC250 &&
2075 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) {
2077 * Workaround occasional packet loss issue of JMC250 A2
2078 * when it runs on half-duplex media.
2080 gpreg = CSR_READ_4(sc, JME_GPREG1);
2081 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
2082 gpreg &= ~GPREG1_HDPX_FIX;
2084 gpreg |= GPREG1_HDPX_FIX;
2085 CSR_WRITE_4(sc, JME_GPREG1, gpreg);
2086 /* Workaround CRC errors at 100Mbps on JMC250 A2. */
2087 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
2088 /* Extend interface FIFO depth. */
2089 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2092 /* Select default interface FIFO depth. */
2093 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2097 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
2099 CSR_WRITE_4(sc, JME_GHC, ghc);
2100 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
2101 CSR_WRITE_4(sc, JME_TXMAC, txmac);
2102 CSR_WRITE_4(sc, JME_TXPFC, txpause);
2106 jme_link_task(void *arg, int pending)
2108 struct jme_softc *sc;
2109 struct mii_data *mii;
2111 struct jme_txdesc *txd;
2115 sc = (struct jme_softc *)arg;
2118 mii = device_get_softc(sc->jme_miibus);
2120 if (mii == NULL || ifp == NULL ||
2121 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2126 sc->jme_flags &= ~JME_FLAG_LINK;
2127 if ((mii->mii_media_status & IFM_AVALID) != 0) {
2128 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2131 sc->jme_flags |= JME_FLAG_LINK;
2134 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0)
2136 sc->jme_flags |= JME_FLAG_LINK;
2144 * Disabling Rx/Tx MACs have a side-effect of resetting
2145 * JME_TXNDA/JME_RXNDA register to the first address of
2146 * Tx/Rx descriptor address. So driver should reset its
2147 * internal procucer/consumer pointer and reclaim any
2148 * allocated resources. Note, just saving the value of
2149 * JME_TXNDA and JME_RXNDA registers before stopping MAC
2150 * and restoring JME_TXNDA/JME_RXNDA register is not
2151 * sufficient to make sure correct MAC state because
2152 * stopping MAC operation can take a while and hardware
2153 * might have updated JME_TXNDA/JME_RXNDA registers
2154 * during the stop operation.
2156 /* Block execution of task. */
2157 taskqueue_block(sc->jme_tq);
2158 /* Disable interrupts and stop driver. */
2159 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2160 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2161 callout_stop(&sc->jme_tick_ch);
2162 sc->jme_watchdog_timer = 0;
2164 /* Stop receiver/transmitter. */
2168 /* XXX Drain all queued tasks. */
2170 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
2171 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task);
2174 jme_rxintr(sc, JME_RX_RING_CNT);
2175 if (sc->jme_cdata.jme_rxhead != NULL)
2176 m_freem(sc->jme_cdata.jme_rxhead);
2177 JME_RXCHAIN_RESET(sc);
2179 if (sc->jme_cdata.jme_tx_cnt != 0) {
2180 /* Remove queued packets for transmit. */
2181 for (i = 0; i < JME_TX_RING_CNT; i++) {
2182 txd = &sc->jme_cdata.jme_txdesc[i];
2183 if (txd->tx_m != NULL) {
2185 sc->jme_cdata.jme_tx_tag,
2187 BUS_DMASYNC_POSTWRITE);
2189 sc->jme_cdata.jme_tx_tag,
2200 * Reuse configured Rx descriptors and reset
2201 * procuder/consumer index.
2203 sc->jme_cdata.jme_rx_cons = 0;
2204 atomic_set_int(&sc->jme_morework, 0);
2205 jme_init_tx_ring(sc);
2206 /* Initialize shadow status block. */
2209 /* Program MAC with resolved speed/duplex/flow-control. */
2210 if ((sc->jme_flags & JME_FLAG_LINK) != 0) {
2212 jme_stats_clear(sc);
2214 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2215 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2217 /* Set Tx ring address to the hardware. */
2218 paddr = JME_TX_RING_ADDR(sc, 0);
2219 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2220 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2222 /* Set Rx ring address to the hardware. */
2223 paddr = JME_RX_RING_ADDR(sc, 0);
2224 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2225 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2227 /* Restart receiver/transmitter. */
2228 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
2230 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
2233 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2234 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2235 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2236 /* Unblock execution of task. */
2237 taskqueue_unblock(sc->jme_tq);
2238 /* Reenable interrupts. */
2239 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2247 struct jme_softc *sc;
2250 sc = (struct jme_softc *)arg;
2252 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
2253 if (status == 0 || status == 0xFFFFFFFF)
2254 return (FILTER_STRAY);
2255 /* Disable interrupts. */
2256 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2257 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task);
2259 return (FILTER_HANDLED);
2263 jme_int_task(void *arg, int pending)
2265 struct jme_softc *sc;
2270 sc = (struct jme_softc *)arg;
2273 status = CSR_READ_4(sc, JME_INTR_STATUS);
2274 more = atomic_readandclear_int(&sc->jme_morework);
2276 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO;
2279 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
2281 /* Reset PCC counter/timer and Ack interrupts. */
2282 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
2283 if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0)
2284 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
2285 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0)
2286 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP;
2287 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2289 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2290 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) {
2291 more = jme_rxintr(sc, sc->jme_process_limit);
2293 atomic_set_int(&sc->jme_morework, 1);
2295 if ((status & INTR_RXQ_DESC_EMPTY) != 0) {
2297 * Notify hardware availability of new Rx
2299 * Reading RXCSR takes very long time under
2300 * heavy load so cache RXCSR value and writes
2301 * the ORed value with the kick command to
2302 * the RXCSR. This saves one register access
2305 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2306 RXCSR_RX_ENB | RXCSR_RXQ_START);
2309 * Reclaiming Tx buffers are deferred to make jme(4) run
2310 * without locks held.
2312 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2313 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
2316 if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) {
2317 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task);
2321 /* Reenable interrupts. */
2322 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2326 jme_txeof(struct jme_softc *sc)
2329 struct jme_txdesc *txd;
2333 JME_LOCK_ASSERT(sc);
2337 cons = sc->jme_cdata.jme_tx_cons;
2338 if (cons == sc->jme_cdata.jme_tx_prod)
2341 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2342 sc->jme_cdata.jme_tx_ring_map,
2343 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2346 * Go through our Tx list and free mbufs for those
2347 * frames which have been transmitted.
2349 for (; cons != sc->jme_cdata.jme_tx_prod;) {
2350 txd = &sc->jme_cdata.jme_txdesc[cons];
2351 status = le32toh(txd->tx_desc->flags);
2352 if ((status & JME_TD_OWN) == JME_TD_OWN)
2355 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0)
2359 if ((status & JME_TD_COLLISION) != 0)
2360 ifp->if_collisions +=
2361 le32toh(txd->tx_desc->buflen) &
2362 JME_TD_BUF_LEN_MASK;
2365 * Only the first descriptor of multi-descriptor
2366 * transmission is updated so driver have to skip entire
2367 * chained buffers for the transmiited frame. In other
2368 * words, JME_TD_OWN bit is valid only at the first
2369 * descriptor of a multi-descriptor transmission.
2371 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2372 sc->jme_rdata.jme_tx_ring[cons].flags = 0;
2373 JME_DESC_INC(cons, JME_TX_RING_CNT);
2376 /* Reclaim transferred mbufs. */
2377 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
2378 BUS_DMASYNC_POSTWRITE);
2379 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2381 KASSERT(txd->tx_m != NULL,
2382 ("%s: freeing NULL mbuf!\n", __func__));
2385 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2386 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2387 ("%s: Active Tx desc counter was garbled\n", __func__));
2389 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2391 sc->jme_cdata.jme_tx_cons = cons;
2392 /* Unarm watchog timer when there is no pending descriptors in queue. */
2393 if (sc->jme_cdata.jme_tx_cnt == 0)
2394 sc->jme_watchdog_timer = 0;
2396 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2397 sc->jme_cdata.jme_tx_ring_map,
2398 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2401 static __inline void
2402 jme_discard_rxbuf(struct jme_softc *sc, int cons)
2404 struct jme_desc *desc;
2406 desc = &sc->jme_rdata.jme_rx_ring[cons];
2407 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2408 desc->buflen = htole32(MCLBYTES);
2411 /* Receive a frame. */
2413 jme_rxeof(struct jme_softc *sc)
2416 struct jme_desc *desc;
2417 struct jme_rxdesc *rxd;
2418 struct mbuf *mp, *m;
2419 uint32_t flags, status;
2420 int cons, count, nsegs;
2424 cons = sc->jme_cdata.jme_rx_cons;
2425 desc = &sc->jme_rdata.jme_rx_ring[cons];
2426 flags = le32toh(desc->flags);
2427 status = le32toh(desc->buflen);
2428 nsegs = JME_RX_NSEGS(status);
2429 sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2430 if ((status & JME_RX_ERR_STAT) != 0) {
2432 jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons);
2433 #ifdef JME_SHOW_ERRORS
2434 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2435 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2437 sc->jme_cdata.jme_rx_cons += nsegs;
2438 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2442 for (count = 0; count < nsegs; count++,
2443 JME_DESC_INC(cons, JME_RX_RING_CNT)) {
2444 rxd = &sc->jme_cdata.jme_rxdesc[cons];
2446 /* Add a new receive buffer to the ring. */
2447 if (jme_newbuf(sc, rxd) != 0) {
2450 for (; count < nsegs; count++) {
2451 jme_discard_rxbuf(sc, cons);
2452 JME_DESC_INC(cons, JME_RX_RING_CNT);
2454 if (sc->jme_cdata.jme_rxhead != NULL) {
2455 m_freem(sc->jme_cdata.jme_rxhead);
2456 JME_RXCHAIN_RESET(sc);
2462 * Assume we've received a full sized frame.
2463 * Actual size is fixed when we encounter the end of
2464 * multi-segmented frame.
2466 mp->m_len = MCLBYTES;
2468 /* Chain received mbufs. */
2469 if (sc->jme_cdata.jme_rxhead == NULL) {
2470 sc->jme_cdata.jme_rxhead = mp;
2471 sc->jme_cdata.jme_rxtail = mp;
2474 * Receive processor can receive a maximum frame
2475 * size of 65535 bytes.
2477 mp->m_flags &= ~M_PKTHDR;
2478 sc->jme_cdata.jme_rxtail->m_next = mp;
2479 sc->jme_cdata.jme_rxtail = mp;
2482 if (count == nsegs - 1) {
2483 /* Last desc. for this frame. */
2484 m = sc->jme_cdata.jme_rxhead;
2485 m->m_flags |= M_PKTHDR;
2486 m->m_pkthdr.len = sc->jme_cdata.jme_rxlen;
2488 /* Set first mbuf size. */
2489 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2490 /* Set last mbuf size. */
2491 mp->m_len = sc->jme_cdata.jme_rxlen -
2492 ((MCLBYTES - JME_RX_PAD_BYTES) +
2493 (MCLBYTES * (nsegs - 2)));
2495 m->m_len = sc->jme_cdata.jme_rxlen;
2496 m->m_pkthdr.rcvif = ifp;
2499 * Account for 10bytes auto padding which is used
2500 * to align IP header on 32bit boundary. Also note,
2501 * CRC bytes is automatically removed by the
2504 m->m_data += JME_RX_PAD_BYTES;
2506 /* Set checksum information. */
2507 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2508 (flags & JME_RD_IPV4) != 0) {
2509 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2510 if ((flags & JME_RD_IPCSUM) != 0)
2511 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2512 if (((flags & JME_RD_MORE_FRAG) == 0) &&
2513 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2514 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2515 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2516 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2517 m->m_pkthdr.csum_flags |=
2518 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2519 m->m_pkthdr.csum_data = 0xffff;
2523 /* Check for VLAN tagged packets. */
2524 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2525 (flags & JME_RD_VLAN_TAG) != 0) {
2526 m->m_pkthdr.ether_vtag =
2527 flags & JME_RD_VLAN_MASK;
2528 m->m_flags |= M_VLANTAG;
2533 (*ifp->if_input)(ifp, m);
2535 /* Reset mbuf chains. */
2536 JME_RXCHAIN_RESET(sc);
2540 sc->jme_cdata.jme_rx_cons += nsegs;
2541 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2545 jme_rxintr(struct jme_softc *sc, int count)
2547 struct jme_desc *desc;
2548 int nsegs, prog, pktlen;
2550 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2551 sc->jme_cdata.jme_rx_ring_map,
2552 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2554 for (prog = 0; count > 0; prog++) {
2555 desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons];
2556 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2558 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2560 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2562 * Check number of segments against received bytes.
2563 * Non-matching value would indicate that hardware
2564 * is still trying to update Rx descriptors. I'm not
2565 * sure whether this check is needed.
2567 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2568 if (nsegs != ((pktlen + (MCLBYTES - 1)) / MCLBYTES))
2571 /* Received a frame. */
2577 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2578 sc->jme_cdata.jme_rx_ring_map,
2579 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2581 return (count > 0 ? 0 : EAGAIN);
2587 struct jme_softc *sc;
2588 struct mii_data *mii;
2590 sc = (struct jme_softc *)arg;
2592 JME_LOCK_ASSERT(sc);
2594 mii = device_get_softc(sc->jme_miibus);
2597 * Reclaim Tx buffers that have been completed. It's not
2598 * needed here but it would release allocated mbuf chains
2599 * faster and limit the maximum delay to a hz.
2602 jme_stats_update(sc);
2604 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2608 jme_reset(struct jme_softc *sc)
2611 /* Stop receiver, transmitter. */
2614 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2616 CSR_WRITE_4(sc, JME_GHC, 0);
2622 struct jme_softc *sc;
2624 sc = (struct jme_softc *)xsc;
2626 jme_init_locked(sc);
2631 jme_init_locked(struct jme_softc *sc)
2634 struct mii_data *mii;
2635 uint8_t eaddr[ETHER_ADDR_LEN];
2640 JME_LOCK_ASSERT(sc);
2643 mii = device_get_softc(sc->jme_miibus);
2646 * Cancel any pending I/O.
2651 * Reset the chip to a known state.
2655 /* Init descriptors. */
2656 error = jme_init_rx_ring(sc);
2658 device_printf(sc->jme_dev,
2659 "%s: initialization failed: no memory for Rx buffers.\n",
2664 jme_init_tx_ring(sc);
2665 /* Initialize shadow status block. */
2668 /* Reprogram the station address. */
2669 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2670 CSR_WRITE_4(sc, JME_PAR0,
2671 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2672 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2675 * Configure Tx queue.
2676 * Tx priority queue weight value : 0
2677 * Tx FIFO threshold for processing next packet : 16QW
2678 * Maximum Tx DMA length : 512
2679 * Allow Tx DMA burst.
2681 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2682 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2683 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2684 sc->jme_txcsr |= sc->jme_tx_dma_size;
2685 sc->jme_txcsr |= TXCSR_DMA_BURST;
2686 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2688 /* Set Tx descriptor counter. */
2689 CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT);
2691 /* Set Tx ring address to the hardware. */
2692 paddr = JME_TX_RING_ADDR(sc, 0);
2693 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2694 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2696 /* Configure TxMAC parameters. */
2697 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2698 reg |= TXMAC_THRESH_1_PKT;
2699 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2700 CSR_WRITE_4(sc, JME_TXMAC, reg);
2703 * Configure Rx queue.
2704 * FIFO full threshold for transmitting Tx pause packet : 128T
2705 * FIFO threshold for processing next packet : 128QW
2707 * Max Rx DMA length : 128
2708 * Rx descriptor retry : 32
2709 * Rx descriptor retry time gap : 256ns
2710 * Don't receive runt/bad frame.
2712 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2714 * Since Rx FIFO size is 4K bytes, receiving frames larger
2715 * than 4K bytes will suffer from Rx FIFO overruns. So
2716 * decrease FIFO threshold to reduce the FIFO overruns for
2717 * frames larger than 4000 bytes.
2718 * For best performance of standard MTU sized frames use
2719 * maximum allowable FIFO threshold, 128QW. Note these do
2720 * not hold on chip full mask verion >=2. For these
2721 * controllers 64QW and 128QW are not valid value.
2723 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2)
2724 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2726 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2727 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE)
2728 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2730 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2732 sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0);
2733 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2734 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2735 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2737 /* Set Rx descriptor counter. */
2738 CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT);
2740 /* Set Rx ring address to the hardware. */
2741 paddr = JME_RX_RING_ADDR(sc, 0);
2742 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2743 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2745 /* Clear receive filter. */
2746 CSR_WRITE_4(sc, JME_RXMAC, 0);
2747 /* Set up the receive filter. */
2752 * Disable all WOL bits as WOL can interfere normal Rx
2753 * operation. Also clear WOL detection status bits.
2755 reg = CSR_READ_4(sc, JME_PMCS);
2756 reg &= ~PMCS_WOL_ENB_MASK;
2757 CSR_WRITE_4(sc, JME_PMCS, reg);
2759 reg = CSR_READ_4(sc, JME_RXMAC);
2761 * Pad 10bytes right before received frame. This will greatly
2762 * help Rx performance on strict-alignment architectures as
2763 * it does not need to copy the frame to align the payload.
2765 reg |= RXMAC_PAD_10BYTES;
2766 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2767 reg |= RXMAC_CSUM_ENB;
2768 CSR_WRITE_4(sc, JME_RXMAC, reg);
2770 /* Configure general purpose reg0 */
2771 reg = CSR_READ_4(sc, JME_GPREG0);
2772 reg &= ~GPREG0_PCC_UNIT_MASK;
2773 /* Set PCC timer resolution to micro-seconds unit. */
2774 reg |= GPREG0_PCC_UNIT_US;
2776 * Disable all shadow register posting as we have to read
2777 * JME_INTR_STATUS register in jme_int_task. Also it seems
2778 * that it's hard to synchronize interrupt status between
2779 * hardware and software with shadow posting due to
2780 * requirements of bus_dmamap_sync(9).
2782 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2783 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2784 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2785 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2786 /* Disable posting of DW0. */
2787 reg &= ~GPREG0_POST_DW0_ENB;
2788 /* Clear PME message. */
2789 reg &= ~GPREG0_PME_ENB;
2790 /* Set PHY address. */
2791 reg &= ~GPREG0_PHY_ADDR_MASK;
2792 reg |= sc->jme_phyaddr;
2793 CSR_WRITE_4(sc, JME_GPREG0, reg);
2795 /* Configure Tx queue 0 packet completion coalescing. */
2796 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
2798 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
2799 PCCTX_COAL_PKT_MASK;
2800 reg |= PCCTX_COAL_TXQ0;
2801 CSR_WRITE_4(sc, JME_PCCTX, reg);
2803 /* Configure Rx queue 0 packet completion coalescing. */
2804 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
2806 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
2807 PCCRX_COAL_PKT_MASK;
2808 CSR_WRITE_4(sc, JME_PCCRX0, reg);
2810 /* Configure shadow status block but don't enable posting. */
2811 paddr = sc->jme_rdata.jme_ssb_block_paddr;
2812 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2813 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2815 /* Disable Timer 1 and Timer 2. */
2816 CSR_WRITE_4(sc, JME_TIMER1, 0);
2817 CSR_WRITE_4(sc, JME_TIMER2, 0);
2819 /* Configure retry transmit period, retry limit value. */
2820 CSR_WRITE_4(sc, JME_TXTRHD,
2821 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2822 TXTRHD_RT_PERIOD_MASK) |
2823 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2824 TXTRHD_RT_LIMIT_SHIFT));
2827 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
2829 /* Initialize the interrupt mask. */
2830 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2831 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2834 * Enabling Tx/Rx DMA engines and Rx queue processing is
2835 * done after detection of valid link in jme_link_task.
2838 sc->jme_flags &= ~JME_FLAG_LINK;
2839 /* Set the current media. */
2842 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2844 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2845 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2849 jme_stop(struct jme_softc *sc)
2852 struct jme_txdesc *txd;
2853 struct jme_rxdesc *rxd;
2856 JME_LOCK_ASSERT(sc);
2858 * Mark the interface down and cancel the watchdog timer.
2861 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2862 sc->jme_flags &= ~JME_FLAG_LINK;
2863 callout_stop(&sc->jme_tick_ch);
2864 sc->jme_watchdog_timer = 0;
2867 * Disable interrupts.
2869 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2870 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2872 /* Disable updating shadow status block. */
2873 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2874 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2876 /* Stop receiver, transmitter. */
2880 /* Reclaim Rx/Tx buffers that have been completed. */
2881 jme_rxintr(sc, JME_RX_RING_CNT);
2882 if (sc->jme_cdata.jme_rxhead != NULL)
2883 m_freem(sc->jme_cdata.jme_rxhead);
2884 JME_RXCHAIN_RESET(sc);
2887 * Free RX and TX mbufs still in the queues.
2889 for (i = 0; i < JME_RX_RING_CNT; i++) {
2890 rxd = &sc->jme_cdata.jme_rxdesc[i];
2891 if (rxd->rx_m != NULL) {
2892 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag,
2893 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2894 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag,
2900 for (i = 0; i < JME_TX_RING_CNT; i++) {
2901 txd = &sc->jme_cdata.jme_txdesc[i];
2902 if (txd->tx_m != NULL) {
2903 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag,
2904 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2905 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2912 jme_stats_update(sc);
2917 jme_stop_tx(struct jme_softc *sc)
2922 reg = CSR_READ_4(sc, JME_TXCSR);
2923 if ((reg & TXCSR_TX_ENB) == 0)
2925 reg &= ~TXCSR_TX_ENB;
2926 CSR_WRITE_4(sc, JME_TXCSR, reg);
2927 for (i = JME_TIMEOUT; i > 0; i--) {
2929 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2933 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2937 jme_stop_rx(struct jme_softc *sc)
2942 reg = CSR_READ_4(sc, JME_RXCSR);
2943 if ((reg & RXCSR_RX_ENB) == 0)
2945 reg &= ~RXCSR_RX_ENB;
2946 CSR_WRITE_4(sc, JME_RXCSR, reg);
2947 for (i = JME_TIMEOUT; i > 0; i--) {
2949 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2953 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2957 jme_init_tx_ring(struct jme_softc *sc)
2959 struct jme_ring_data *rd;
2960 struct jme_txdesc *txd;
2963 sc->jme_cdata.jme_tx_prod = 0;
2964 sc->jme_cdata.jme_tx_cons = 0;
2965 sc->jme_cdata.jme_tx_cnt = 0;
2967 rd = &sc->jme_rdata;
2968 bzero(rd->jme_tx_ring, JME_TX_RING_SIZE);
2969 for (i = 0; i < JME_TX_RING_CNT; i++) {
2970 txd = &sc->jme_cdata.jme_txdesc[i];
2972 txd->tx_desc = &rd->jme_tx_ring[i];
2976 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2977 sc->jme_cdata.jme_tx_ring_map,
2978 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2982 jme_init_ssb(struct jme_softc *sc)
2984 struct jme_ring_data *rd;
2986 rd = &sc->jme_rdata;
2987 bzero(rd->jme_ssb_block, JME_SSB_SIZE);
2988 bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map,
2989 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2993 jme_init_rx_ring(struct jme_softc *sc)
2995 struct jme_ring_data *rd;
2996 struct jme_rxdesc *rxd;
2999 sc->jme_cdata.jme_rx_cons = 0;
3000 JME_RXCHAIN_RESET(sc);
3001 atomic_set_int(&sc->jme_morework, 0);
3003 rd = &sc->jme_rdata;
3004 bzero(rd->jme_rx_ring, JME_RX_RING_SIZE);
3005 for (i = 0; i < JME_RX_RING_CNT; i++) {
3006 rxd = &sc->jme_cdata.jme_rxdesc[i];
3008 rxd->rx_desc = &rd->jme_rx_ring[i];
3009 if (jme_newbuf(sc, rxd) != 0)
3013 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
3014 sc->jme_cdata.jme_rx_ring_map,
3015 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3021 jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd)
3023 struct jme_desc *desc;
3025 bus_dma_segment_t segs[1];
3029 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3033 * JMC250 has 64bit boundary alignment limitation so jme(4)
3034 * takes advantage of 10 bytes padding feature of hardware
3035 * in order not to copy entire frame to align IP header on
3038 m->m_len = m->m_pkthdr.len = MCLBYTES;
3040 if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag,
3041 sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3045 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3047 if (rxd->rx_m != NULL) {
3048 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
3049 BUS_DMASYNC_POSTREAD);
3050 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap);
3052 map = rxd->rx_dmamap;
3053 rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap;
3054 sc->jme_cdata.jme_rx_sparemap = map;
3055 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
3056 BUS_DMASYNC_PREREAD);
3059 desc = rxd->rx_desc;
3060 desc->buflen = htole32(segs[0].ds_len);
3061 desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr));
3062 desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr));
3063 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
3069 jme_set_vlan(struct jme_softc *sc)
3074 JME_LOCK_ASSERT(sc);
3077 reg = CSR_READ_4(sc, JME_RXMAC);
3078 reg &= ~RXMAC_VLAN_ENB;
3079 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3080 reg |= RXMAC_VLAN_ENB;
3081 CSR_WRITE_4(sc, JME_RXMAC, reg);
3085 jme_set_filter(struct jme_softc *sc)
3088 struct ifmultiaddr *ifma;
3093 JME_LOCK_ASSERT(sc);
3097 rxcfg = CSR_READ_4(sc, JME_RXMAC);
3098 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
3100 /* Always accept frames destined to our station address. */
3101 rxcfg |= RXMAC_UNICAST;
3102 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3103 rxcfg |= RXMAC_BROADCAST;
3104 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3105 if ((ifp->if_flags & IFF_PROMISC) != 0)
3106 rxcfg |= RXMAC_PROMISC;
3107 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3108 rxcfg |= RXMAC_ALLMULTI;
3109 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
3110 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
3111 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3116 * Set up the multicast address filter by passing all multicast
3117 * addresses through a CRC generator, and then using the low-order
3118 * 6 bits as an index into the 64 bit multicast hash table. The
3119 * high order bits select the register, while the rest of the bits
3120 * select the bit within the register.
3122 rxcfg |= RXMAC_MULTICAST;
3123 bzero(mchash, sizeof(mchash));
3126 TAILQ_FOREACH(ifma, &sc->jme_ifp->if_multiaddrs, ifma_link) {
3127 if (ifma->ifma_addr->sa_family != AF_LINK)
3129 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3130 ifma->ifma_addr), ETHER_ADDR_LEN);
3132 /* Just want the 6 least significant bits. */
3135 /* Set the corresponding bit in the hash table. */
3136 mchash[crc >> 5] |= 1 << (crc & 0x1f);
3138 IF_ADDR_UNLOCK(ifp);
3140 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3141 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3142 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3146 jme_stats_clear(struct jme_softc *sc)
3149 JME_LOCK_ASSERT(sc);
3151 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3154 /* Disable and clear counters. */
3155 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
3156 /* Activate hw counters. */
3157 CSR_WRITE_4(sc, JME_STATCSR, 0);
3158 CSR_READ_4(sc, JME_STATCSR);
3159 bzero(&sc->jme_stats, sizeof(struct jme_hw_stats));
3163 jme_stats_save(struct jme_softc *sc)
3166 JME_LOCK_ASSERT(sc);
3168 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3170 /* Save current counters. */
3171 bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats));
3172 /* Disable and clear counters. */
3173 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
3177 jme_stats_update(struct jme_softc *sc)
3179 struct jme_hw_stats *stat, *ostat;
3182 JME_LOCK_ASSERT(sc);
3184 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3186 stat = &sc->jme_stats;
3187 ostat = &sc->jme_ostats;
3188 stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD);
3189 stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD);
3190 reg = CSR_READ_4(sc, JME_STAT_CRCMII);
3191 stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >>
3192 STAT_RX_CRC_ERR_SHIFT;
3193 stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >>
3194 STAT_RX_MII_ERR_SHIFT;
3195 reg = CSR_READ_4(sc, JME_STAT_RXERR);
3196 stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >>
3197 STAT_RXERR_OFLOW_SHIFT;
3198 stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >>
3199 STAT_RXERR_MPTY_SHIFT;
3200 reg = CSR_READ_4(sc, JME_STAT_FAIL);
3201 stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT;
3202 stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT;
3204 /* Account for previous counters. */
3205 stat->rx_good_frames += ostat->rx_good_frames;
3206 stat->rx_crc_errs += ostat->rx_crc_errs;
3207 stat->rx_mii_errs += ostat->rx_mii_errs;
3208 stat->rx_fifo_oflows += ostat->rx_fifo_oflows;
3209 stat->rx_desc_empty += ostat->rx_desc_empty;
3210 stat->rx_bad_frames += ostat->rx_bad_frames;
3211 stat->tx_good_frames += ostat->tx_good_frames;
3212 stat->tx_bad_frames += ostat->tx_bad_frames;
3216 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3222 value = *(int *)arg1;
3223 error = sysctl_handle_int(oidp, &value, 0, req);
3224 if (error || req->newptr == NULL)
3226 if (value < low || value > high)
3228 *(int *)arg1 = value;
3234 sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS)
3236 return (sysctl_int_range(oidp, arg1, arg2, req,
3237 PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX));
3241 sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
3243 return (sysctl_int_range(oidp, arg1, arg2, req,
3244 PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX));
3248 sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS)
3250 return (sysctl_int_range(oidp, arg1, arg2, req,
3251 PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX));
3255 sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3257 return (sysctl_int_range(oidp, arg1, arg2, req,
3258 PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX));
3262 sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS)
3264 return (sysctl_int_range(oidp, arg1, arg2, req,
3265 JME_PROC_MIN, JME_PROC_MAX));