sys/dev/mii/brgphy.c

   1 /*-
   2  * Copyright (c) 2000
   3  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 /*
  37  * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
  38  */
  39
  40 #include <sys/param.h>
  41 #include <sys/systm.h>
  42 #include <sys/kernel.h>
  43 #include <sys/module.h>
  44 #include <sys/socket.h>
  45 #include <sys/bus.h>
  46
  47 #include <net/if.h>
  48 #include <net/ethernet.h>
  49 #include <net/if_media.h>
  50
  51 #include <dev/mii/mii.h>
  52 #include <dev/mii/miivar.h>
  53 #include "miidevs.h"
  54
  55 #include <dev/mii/brgphyreg.h>
  56 #include <net/if_arp.h>
  57 #include <machine/bus.h>
  58 #include <dev/bge/if_bgereg.h>
  59 #include <dev/bce/if_bcereg.h>
  60
  61 #include <dev/pci/pcireg.h>
  62 #include <dev/pci/pcivar.h>
  63
  64 #include "miibus_if.h"
  65
  66 static int brgphy_probe(device_t);
  67 static int brgphy_attach(device_t);
  68
  69 struct brgphy_softc {
  70         struct mii_softc mii_sc;
  71         int mii_oui;
  72         int mii_model;
  73         int mii_rev;
  74         int serdes_flags;       /* Keeps track of the serdes type used */
  75 #define BRGPHY_5706S    0x0001
  76 #define BRGPHY_5708S    0x0002
  77         int bce_phy_flags;              /* PHY flags transferred from the MAC driver */
  78 };
  79
  80 static device_method_t brgphy_methods[] = {
  81         /* device interface */
  82         DEVMETHOD(device_probe,         brgphy_probe),
  83         DEVMETHOD(device_attach,        brgphy_attach),
  84         DEVMETHOD(device_detach,        mii_phy_detach),
  85         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  86         { 0, 0 }
  87 };
  88
  89 static devclass_t brgphy_devclass;
  90
  91 static driver_t brgphy_driver = {
  92         "brgphy",
  93         brgphy_methods,
  94         sizeof(struct brgphy_softc)
  95 };
  96
  97 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
  98
  99 static int      brgphy_service(struct mii_softc *, struct mii_data *, int);
 100 static void     brgphy_setmedia(struct mii_softc *, int, int);
 101 static void     brgphy_status(struct mii_softc *);
 102 static void     brgphy_mii_phy_auto(struct mii_softc *);
 103 static void     brgphy_reset(struct mii_softc *);
 104 static void     brgphy_enable_loopback(struct mii_softc *);
 105 static void     bcm5401_load_dspcode(struct mii_softc *);
 106 static void     bcm5411_load_dspcode(struct mii_softc *);
 107 static void     brgphy_fixup_5704_a0_bug(struct mii_softc *);
 108 static void     brgphy_fixup_adc_bug(struct mii_softc *);
 109 static void     brgphy_fixup_adjust_trim(struct mii_softc *);
 110 static void     brgphy_fixup_ber_bug(struct mii_softc *);
 111 static void     brgphy_fixup_crc_bug(struct mii_softc *);
 112 static void     brgphy_fixup_jitter_bug(struct mii_softc *);
 113 static void     brgphy_ethernet_wirespeed(struct mii_softc *);
 114 static void     brgphy_jumbo_settings(struct mii_softc *, u_long);
 115
 116 static const struct mii_phydesc brgphys[] = {
 117         MII_PHY_DESC(xxBROADCOM, BCM5400),
 118         MII_PHY_DESC(xxBROADCOM, BCM5401),
 119         MII_PHY_DESC(xxBROADCOM, BCM5411),
 120         MII_PHY_DESC(xxBROADCOM, BCM5701),
 121         MII_PHY_DESC(xxBROADCOM, BCM5703),
 122         MII_PHY_DESC(xxBROADCOM, BCM5704),
 123         MII_PHY_DESC(xxBROADCOM, BCM5705),
 124         MII_PHY_DESC(xxBROADCOM, BCM5706),
 125         MII_PHY_DESC(xxBROADCOM, BCM5714),
 126         MII_PHY_DESC(xxBROADCOM, BCM5750),
 127         MII_PHY_DESC(xxBROADCOM, BCM5752),
 128         MII_PHY_DESC(xxBROADCOM, BCM5754),
 129         MII_PHY_DESC(xxBROADCOM, BCM5780),
 130         MII_PHY_DESC(xxBROADCOM, BCM5708C),
 131         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755),
 132         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787),
 133         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S),
 134         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722),
 135         MII_PHY_DESC(BROADCOM2, BCM5906),
 136         MII_PHY_END
 137 };
 138
 139
 140 /* Search for our PHY in the list of known PHYs */
 141 static int
 142 brgphy_probe(device_t dev)
 143 {
 144         return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
 145 }
 146
 147 /* Attach the PHY to the MII bus */
 148 static int
 149 brgphy_attach(device_t dev)
 150 {
 151         struct brgphy_softc *bsc;
 152         struct bge_softc *bge_sc = NULL;
 153         struct bce_softc *bce_sc = NULL;
 154         struct mii_softc *sc;
 155         struct mii_attach_args *ma;
 156         struct mii_data *mii;
 157         struct ifnet *ifp;
 158         int fast_ether;
 159
 160         bsc = device_get_softc(dev);
 161         sc = &bsc->mii_sc;
 162         ma = device_get_ivars(dev);
 163         sc->mii_dev = device_get_parent(dev);
 164         mii = device_get_softc(sc->mii_dev);
 165         LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
 166
 167         /* Initialize mii_softc structure */
 168         sc->mii_inst = mii->mii_instance;
 169         sc->mii_phy = ma->mii_phyno;
 170         sc->mii_service = brgphy_service;
 171         sc->mii_pdata = mii;
 172         sc->mii_anegticks = MII_ANEGTICKS_GIGE;
 173         sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
 174         mii->mii_instance++;
 175
 176         /* Initialize brgphy_softc structure */
 177         bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
 178         bsc->mii_model = MII_MODEL(ma->mii_id2);
 179         bsc->mii_rev = MII_REV(ma->mii_id2);
 180         bsc->serdes_flags = 0;
 181
 182         fast_ether = 0;
 183
 184         if (bootverbose)
 185                 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
 186                     bsc->mii_oui, bsc->mii_model, bsc->mii_rev);
 187
 188         /* Handle any special cases based on the PHY ID */
 189         switch (bsc->mii_oui) {
 190         case MII_OUI_BROADCOM:
 191         case MII_OUI_BROADCOM2:
 192                 break;
 193         case MII_OUI_xxBROADCOM:
 194                 switch (bsc->mii_model) {
 195                         case MII_MODEL_xxBROADCOM_BCM5706:
 196                                 /*
 197                                  * The 5464 PHY used in the 5706 supports both copper
 198                                  * and fiber interfaces over GMII.  Need to check the
 199                                  * shadow registers to see which mode is actually
 200                                  * in effect, and therefore whether we have 5706C or
 201                                  * 5706S.
 202                                  */
 203                                 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
 204                                         BRGPHY_SHADOW_1C_MODE_CTRL);
 205                                 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
 206                                         BRGPHY_SHADOW_1C_ENA_1000X) {
 207                                         bsc->serdes_flags |= BRGPHY_5706S;
 208                                         sc->mii_flags |= MIIF_HAVEFIBER;
 209                                 }
 210                                 break;
 211                 } break;
 212         case MII_OUI_xxBROADCOM_ALT1:
 213                 switch (bsc->mii_model) {
 214                         case MII_MODEL_xxBROADCOM_ALT1_BCM5708S:
 215                                 bsc->serdes_flags |= BRGPHY_5708S;
 216                                 sc->mii_flags |= MIIF_HAVEFIBER;
 217                                 break;
 218                 } break;
 219         default:
 220                 device_printf(dev, "Unrecognized OUI for PHY!\n");
 221         }
 222
 223         ifp = sc->mii_pdata->mii_ifp;
 224
 225         /* Find the MAC driver associated with this PHY. */
 226         if (strcmp(ifp->if_dname, "bge") == 0)  {
 227                 bge_sc = ifp->if_softc;
 228         } else if (strcmp(ifp->if_dname, "bce") == 0) {
 229                 bce_sc = ifp->if_softc;
 230         }
 231
 232         /* Todo: Need to add additional controllers such as 5787F */
 233         /* The 590x chips are 10/100 only. */
 234         if (bge_sc &&
 235             pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
 236             (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
 237             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2 ||
 238             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906 ||
 239             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906M)) {
 240                 fast_ether = 1;
 241                 sc->mii_anegticks = MII_ANEGTICKS;
 242         }
 243
 244         brgphy_reset(sc);
 245
 246         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
 247         if (sc->mii_capabilities & BMSR_EXTSTAT)
 248                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 249         device_printf(dev, " ");
 250
 251 #define ADD(m, c)       ifmedia_add(&mii->mii_media, (m), (c), NULL)
 252
 253         /* Create an instance of Ethernet media. */
 254         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), BMCR_ISO);
 255
 256         /* Add the supported media types */
 257         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 258                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst),
 259                         BRGPHY_S10);
 260                 printf("10baseT, ");
 261                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
 262                         BRGPHY_S10 | BRGPHY_BMCR_FDX);
 263                 printf("10baseT-FDX, ");
 264                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst),
 265                         BRGPHY_S100);
 266                 printf("100baseTX, ");
 267                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
 268                         BRGPHY_S100 | BRGPHY_BMCR_FDX);
 269                 printf("100baseTX-FDX, ");
 270                 if (fast_ether == 0) {
 271                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
 272                                 BRGPHY_S1000);
 273                         printf("1000baseT, ");
 274                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst),
 275                                 BRGPHY_S1000 | BRGPHY_BMCR_FDX);
 276                         printf("1000baseT-FDX, ");
 277                 }
 278         } else {
 279                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
 280                         BRGPHY_S1000 | BRGPHY_BMCR_FDX);
 281                 printf("1000baseSX-FDX, ");
 282                 /* 2.5G support is a software enabled feature on the 5708S */
 283                 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 284                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0);
 285                         printf("2500baseSX-FDX, ");
 286                 }
 287         }
 288
 289         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
 290         printf("auto\n");
 291
 292 #undef ADD
 293         MIIBUS_MEDIAINIT(sc->mii_dev);
 294         return (0);
 295 }
 296
 297 static int
 298 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 299 {
 300         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 301         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 302         int error = 0;
 303         int val;
 304
 305         switch (cmd) {
 306         case MII_POLLSTAT:
 307                 /* If we're not polling our PHY instance, just return. */
 308                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 309                         goto brgphy_service_exit;
 310                 break;
 311         case MII_MEDIACHG:
 312                 /*
 313                  * If the media indicates a different PHY instance,
 314                  * isolate ourselves.
 315                  */
 316                 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
 317                         PHY_WRITE(sc, MII_BMCR,
 318                             PHY_READ(sc, MII_BMCR) | BMCR_ISO);
 319                         goto brgphy_service_exit;
 320                 }
 321
 322                 /* If the interface is not up, don't do anything. */
 323                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 324                         break;
 325
 326                 /* Todo: Why is this here?  Is it really needed? */
 327                 brgphy_reset(sc);       /* XXX hardware bug work-around */
 328
 329                 switch (IFM_SUBTYPE(ife->ifm_media)) {
 330                 case IFM_AUTO:
 331                         brgphy_mii_phy_auto(sc);
 332                         break;
 333                 case IFM_2500_SX:
 334                 case IFM_1000_SX:
 335                 case IFM_1000_T:
 336                 case IFM_100_TX:
 337                 case IFM_10_T:
 338                         brgphy_setmedia(sc, ife->ifm_media,
 339                             mii->mii_ifp->if_flags & IFF_LINK0);
 340                         break;
 341                 default:
 342                         error = EINVAL;
 343                         goto brgphy_service_exit;
 344                 }
 345                 break;
 346         case MII_TICK:
 347                 /* Bail if we're not currently selected. */
 348                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 349                         goto brgphy_service_exit;
 350
 351                 /* Bail if the interface isn't up. */
 352                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 353                         goto brgphy_service_exit;
 354
 355
 356                 /* Bail if autoneg isn't in process. */
 357                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
 358                         sc->mii_ticks = 0;
 359                         break;
 360                 }
 361
 362                 /*
 363                  * Check to see if we have link.  If we do, we don't
 364                  * need to restart the autonegotiation process.
 365                  */
 366                 val     = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
 367                 if (val & BMSR_LINK) {
 368                         sc->mii_ticks = 0;      /* Reset autoneg timer. */
 369                         break;
 370                 }
 371
 372                 /* Announce link loss right after it happens. */
 373                 if (sc->mii_ticks++ == 0)
 374                         break;
 375
 376                 /* Only retry autonegotiation every mii_anegticks seconds. */
 377                 if (sc->mii_ticks <= sc->mii_anegticks)
 378                         break;
 379
 380
 381                 /* Retry autonegotiation */
 382                 sc->mii_ticks = 0;
 383                 brgphy_mii_phy_auto(sc);
 384                 break;
 385         }
 386
 387         /* Update the media status. */
 388         brgphy_status(sc);
 389
 390         /*
 391          * Callback if something changed. Note that we need to poke
 392          * the DSP on the Broadcom PHYs if the media changes.
 393          */
 394         if (sc->mii_media_active != mii->mii_media_active ||
 395             sc->mii_media_status != mii->mii_media_status ||
 396             cmd == MII_MEDIACHG) {
 397                 switch (bsc->mii_oui) {
 398                 case MII_OUI_BROADCOM:
 399                         break;
 400                 case MII_OUI_xxBROADCOM:
 401                         switch (bsc->mii_model) {
 402                         case MII_MODEL_xxBROADCOM_BCM5400:
 403                                 bcm5401_load_dspcode(sc);
 404                                 break;
 405                         case MII_MODEL_xxBROADCOM_BCM5401:
 406                                 if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
 407                                         bcm5401_load_dspcode(sc);
 408                                 break;
 409                         case MII_MODEL_xxBROADCOM_BCM5411:
 410                                 bcm5411_load_dspcode(sc);
 411                                 break;
 412                         }
 413                         break;
 414                 case MII_OUI_xxBROADCOM_ALT1:
 415                         break;
 416                 }
 417         }
 418         mii_phy_update(sc, cmd);
 419 brgphy_service_exit:
 420         return (error);
 421 }
 422
 423 static void
 424 brgphy_setmedia(struct mii_softc *sc, int media, int master)
 425 {
 426         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 427         int bmcr = 0, gig;
 428
 429         switch (IFM_SUBTYPE(media)) {
 430         case IFM_2500_SX:
 431                 break;
 432         case IFM_1000_SX:
 433         case IFM_1000_T:
 434                 bmcr = BRGPHY_S1000;
 435                 break;
 436         case IFM_100_TX:
 437                 bmcr = BRGPHY_S100;
 438                 break;
 439         case IFM_10_T:
 440         default:
 441                 bmcr = BRGPHY_S10;
 442                 break;
 443         }
 444         if ((media & IFM_GMASK) == IFM_FDX) {
 445                 bmcr |= BRGPHY_BMCR_FDX;
 446                 gig = BRGPHY_1000CTL_AFD;
 447         } else {
 448                 gig = BRGPHY_1000CTL_AHD;
 449         }
 450
 451         brgphy_enable_loopback(sc);
 452         PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
 453         PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
 454         PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
 455
 456         if ((IFM_SUBTYPE(media) != IFM_1000_T) && (IFM_SUBTYPE(media) != IFM_1000_SX))
 457                 goto brgphy_setmedia_exit;
 458
 459         PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
 460         PHY_WRITE(sc, BRGPHY_MII_BMCR,
 461             bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 462
 463         if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
 464                 goto brgphy_setmedia_exit;
 465
 466         /*
 467          * When setting the link manually, one side must be the master and
 468          * the other the slave. However ifmedia doesn't give us a good way
 469          * to specify this, so we fake it by using one of the LINK flags.
 470          * If LINK0 is set, we program the PHY to be a master, otherwise
 471          * it's a slave.
 472          */
 473         if (master) {
 474                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 475                     gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC);
 476         } else {
 477                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 478                     gig | BRGPHY_1000CTL_MSE);
 479         }
 480 brgphy_setmedia_exit:
 481         return;
 482 }
 483
 484 /* Set the media status based on the PHY settings. */
 485 /* IFM_FLAG0 = 0 (RX flow control disabled | 1 (enabled) */
 486 /* IFM_FLAG1 = 0 (TX flow control disabled | 1 (enabled) */
 487 static void
 488 brgphy_status(struct mii_softc *sc)
 489 {
 490         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 491         struct mii_data *mii = sc->mii_pdata;
 492         int aux, bmcr, bmsr, anar, anlpar, xstat, val;
 493
 494
 495         mii->mii_media_status = IFM_AVALID;
 496         mii->mii_media_active = IFM_ETHER;
 497
 498         bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
 499         bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
 500         anar = PHY_READ(sc, BRGPHY_MII_ANAR);
 501         anlpar = PHY_READ(sc, BRGPHY_MII_ANLPAR);
 502
 503         /* Loopback is enabled. */
 504         if (bmcr & BRGPHY_BMCR_LOOP) {
 505
 506                 mii->mii_media_active |= IFM_LOOP;
 507         }
 508
 509         /* Autoneg is still in progress. */
 510         if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
 511             (bmsr & BRGPHY_BMSR_ACOMP) == 0) {
 512                 /* Erg, still trying, I guess... */
 513                 mii->mii_media_active |= IFM_NONE;
 514                 goto brgphy_status_exit;
 515         }
 516
 517         /* Autoneg is enabled and complete, link should be up. */
 518         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 519                 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
 520
 521                 /* If copper link is up, get the negotiated speed/duplex. */
 522                 if (aux & BRGPHY_AUXSTS_LINK) {
 523                         mii->mii_media_status |= IFM_ACTIVE;
 524                         switch (aux & BRGPHY_AUXSTS_AN_RES) {
 525                         case BRGPHY_RES_1000FD:
 526                                 mii->mii_media_active |= IFM_1000_T | IFM_FDX;  break;
 527                         case BRGPHY_RES_1000HD:
 528                                 mii->mii_media_active |= IFM_1000_T | IFM_HDX;  break;
 529                         case BRGPHY_RES_100FD:
 530                                 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
 531                         case BRGPHY_RES_100T4:
 532                                 mii->mii_media_active |= IFM_100_T4; break;
 533                         case BRGPHY_RES_100HD:
 534                                 mii->mii_media_active |= IFM_100_TX | IFM_HDX;  break;
 535                         case BRGPHY_RES_10FD:
 536                                 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
 537                         case BRGPHY_RES_10HD:
 538                                 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
 539                         default:
 540                                 mii->mii_media_active |= IFM_NONE; break;
 541                         }
 542                 }
 543         } else {
 544                 /* If serdes link is up, get the negotiated speed/duplex. */
 545                 if (bmsr & BRGPHY_BMSR_LINK) {
 546                         mii->mii_media_status |= IFM_ACTIVE;
 547                 }
 548
 549                 /* Check the link speed/duplex based on the PHY type. */
 550                 if (bsc->serdes_flags & BRGPHY_5706S) {
 551                         mii->mii_media_active |= IFM_1000_SX;
 552
 553                         /* If autoneg enabled, read negotiated duplex settings */
 554                         if (bmcr & BRGPHY_BMCR_AUTOEN) {
 555                                 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
 556                                 if (val & BRGPHY_SERDES_ANAR_FDX)
 557                                         mii->mii_media_active |= IFM_FDX;
 558                                 else
 559                                         mii->mii_media_active |= IFM_HDX;
 560                         }
 561
 562                 } else if (bsc->serdes_flags & BRGPHY_5708S) {
 563                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 564                         xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
 565
 566                         /* Todo: Create #defines for hard coded values */
 567                         switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
 568                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
 569                                 mii->mii_media_active |= IFM_10_FL; break;
 570                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
 571                                 mii->mii_media_active |= IFM_100_FX; break;
 572                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
 573                                 mii->mii_media_active |= IFM_1000_SX; break;
 574                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
 575                                 mii->mii_media_active |= IFM_2500_SX; break;
 576                         }
 577
 578                         if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
 579                                 mii->mii_media_active |= IFM_FDX;
 580                         else
 581                                 mii->mii_media_active |= IFM_HDX;
 582                 }
 583         }
 584
 585 #if 0
 586         /* Todo: Change bge/bce to use these settings. */
 587
 588         /* Fetch flow control settings from the PHY */
 589         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 590                 /* Set FLAG0 is RX is enabled and FLAG1 if TX is enabled */
 591                 if ((anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANLPAR_PC)) {
 592                         mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
 593                 } else if (!(anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANAR_ASP) &&
 594                     (anlpar & BRPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
 595                         mii->mii_media_active |= IFM_FLAG1;
 596                 } else if ((anar & BRGPHY_ANAR_PC) && (anar & BRGPHY_ANAR_ASP) &&
 597                     !(anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
 598                         mii->mii_media_active |= IFM_FLAG0;
 599                 }
 600         }
 601         /* Todo: Add support for fiber settings too. */
 602 #endif
 603
 604
 605 brgphy_status_exit:
 606         return;
 607 }
 608
 609 static void
 610 brgphy_mii_phy_auto(struct mii_softc *sc)
 611 {
 612         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 613         int ktcr = 0;
 614
 615         brgphy_reset(sc);
 616
 617         /* Enable flow control in the advertisement register. */
 618         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 619                 /* Pause capability advertisement (pause capable & asymmetric) */
 620                 PHY_WRITE(sc, BRGPHY_MII_ANAR,
 621                 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA |
 622                 BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC);
 623         } else {
 624                 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX |
 625                         BRGPHY_SERDES_ANAR_HDX | BRGPHY_SERDES_ANAR_BOTH_PAUSE);
 626         }
 627
 628         /* Enable speed in the 1000baseT control register */
 629         ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
 630         if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
 631                 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
 632         PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
 633         ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
 634
 635         /* Start autonegotiation */
 636         PHY_WRITE(sc, BRGPHY_MII_BMCR,BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 637         PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
 638
 639 }
 640
 641 /* Enable loopback to force the link down. */
 642 static void
 643 brgphy_enable_loopback(struct mii_softc *sc)
 644 {
 645         int i;
 646
 647         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
 648         for (i = 0; i < 15000; i++) {
 649                 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
 650                         break;
 651                 DELAY(10);
 652         }
 653 }
 654
 655 /* Turn off tap power management on 5401. */
 656 static void
 657 bcm5401_load_dspcode(struct mii_softc *sc)
 658 {
 659         static const struct {
 660                 int             reg;
 661                 uint16_t        val;
 662         } dspcode[] = {
 663                 { BRGPHY_MII_AUXCTL,            0x0c20 },
 664                 { BRGPHY_MII_DSP_ADDR_REG,      0x0012 },
 665                 { BRGPHY_MII_DSP_RW_PORT,       0x1804 },
 666                 { BRGPHY_MII_DSP_ADDR_REG,      0x0013 },
 667                 { BRGPHY_MII_DSP_RW_PORT,       0x1204 },
 668                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 669                 { BRGPHY_MII_DSP_RW_PORT,       0x0132 },
 670                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 671                 { BRGPHY_MII_DSP_RW_PORT,       0x0232 },
 672                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 673                 { BRGPHY_MII_DSP_RW_PORT,       0x0a20 },
 674                 { 0,                            0 },
 675         };
 676         int i;
 677
 678         for (i = 0; dspcode[i].reg != 0; i++)
 679                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 680         DELAY(40);
 681 }
 682
 683 static void
 684 bcm5411_load_dspcode(struct mii_softc *sc)
 685 {
 686         static const struct {
 687                 int             reg;
 688                 uint16_t        val;
 689         } dspcode[] = {
 690                 { 0x1c,                         0x8c23 },
 691                 { 0x1c,                         0x8ca3 },
 692                 { 0x1c,                         0x8c23 },
 693                 { 0,                            0 },
 694         };
 695         int i;
 696
 697         for (i = 0; dspcode[i].reg != 0; i++)
 698                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 699 }
 700
 701 static void
 702 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
 703 {
 704         static const struct {
 705                 int             reg;
 706                 uint16_t        val;
 707         } dspcode[] = {
 708                 { 0x1c,                         0x8d68 },
 709                 { 0x1c,                         0x8d68 },
 710                 { 0,                            0 },
 711         };
 712         int i;
 713
 714         for (i = 0; dspcode[i].reg != 0; i++)
 715                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 716 }
 717
 718 static void
 719 brgphy_fixup_adc_bug(struct mii_softc *sc)
 720 {
 721         static const struct {
 722                 int             reg;
 723                 uint16_t        val;
 724         } dspcode[] = {
 725                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 726                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 727                 { BRGPHY_MII_DSP_RW_PORT,       0x2aaa },
 728                 { 0,                            0 },
 729         };
 730         int i;
 731
 732         for (i = 0; dspcode[i].reg != 0; i++)
 733                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 734 }
 735
 736 static void
 737 brgphy_fixup_adjust_trim(struct mii_softc *sc)
 738 {
 739         static const struct {
 740                 int             reg;
 741                 uint16_t        val;
 742         } dspcode[] = {
 743                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 744                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 745                 { BRGPHY_MII_DSP_RW_PORT,       0x110b },
 746                 { BRGPHY_MII_TEST1,                     0x0014 },
 747                 { BRGPHY_MII_AUXCTL,            0x0400 },
 748                 { 0,                            0 },
 749         };
 750         int i;
 751
 752         for (i = 0; dspcode[i].reg != 0; i++)
 753                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 754 }
 755
 756 static void
 757 brgphy_fixup_ber_bug(struct mii_softc *sc)
 758 {
 759         static const struct {
 760                 int             reg;
 761                 uint16_t        val;
 762         } dspcode[] = {
 763                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 764                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 765                 { BRGPHY_MII_DSP_RW_PORT,       0x310b },
 766                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 767                 { BRGPHY_MII_DSP_RW_PORT,       0x9506 },
 768                 { BRGPHY_MII_DSP_ADDR_REG,      0x401f },
 769                 { BRGPHY_MII_DSP_RW_PORT,       0x14e2 },
 770                 { BRGPHY_MII_AUXCTL,            0x0400 },
 771                 { 0,                            0 },
 772         };
 773         int i;
 774
 775         for (i = 0; dspcode[i].reg != 0; i++)
 776                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 777 }
 778
 779 static void
 780 brgphy_fixup_crc_bug(struct mii_softc *sc)
 781 {
 782         static const struct {
 783                 int             reg;
 784                 uint16_t        val;
 785         } dspcode[] = {
 786                 { BRGPHY_MII_DSP_RW_PORT,       0x0a75 },
 787                 { 0x1c,                         0x8c68 },
 788                 { 0x1c,                         0x8d68 },
 789                 { 0x1c,                         0x8c68 },
 790                 { 0,                            0 },
 791         };
 792         int i;
 793
 794         for (i = 0; dspcode[i].reg != 0; i++)
 795                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 796 }
 797
 798 static void
 799 brgphy_fixup_jitter_bug(struct mii_softc *sc)
 800 {
 801         static const struct {
 802                 int             reg;
 803                 uint16_t        val;
 804         } dspcode[] = {
 805                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 806                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 807                 { BRGPHY_MII_DSP_RW_PORT,       0x010b },
 808                 { BRGPHY_MII_AUXCTL,            0x0400 },
 809                 { 0,                            0 },
 810         };
 811         int i;
 812
 813         for (i = 0; dspcode[i].reg != 0; i++)
 814                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 815 }
 816
 817 static void
 818 brgphy_ethernet_wirespeed(struct mii_softc *sc)
 819 {
 820         uint32_t        val;
 821
 822         /* Enable Ethernet@WireSpeed. */
 823         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
 824         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 825         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
 826 }
 827
 828 static void
 829 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
 830 {
 831         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 832         uint32_t        val;
 833
 834         /* Set or clear jumbo frame settings in the PHY. */
 835         if (mtu > ETHER_MAX_LEN) {
 836                 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
 837                         /* BCM5401 PHY cannot read-modify-write. */
 838                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
 839                 } else {
 840                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 841                         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 842                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 843                             val | BRGPHY_AUXCTL_LONG_PKT);
 844                 }
 845
 846                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 847                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 848                     val | BRGPHY_PHY_EXTCTL_HIGH_LA);
 849         } else {
 850                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 851                 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 852                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 853                     val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
 854
 855                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 856                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 857                         val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
 858         }
 859 }
 860
 861 static void
 862 brgphy_reset(struct mii_softc *sc)
 863 {
 864         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 865         struct bge_softc *bge_sc = NULL;
 866         struct bce_softc *bce_sc = NULL;
 867         struct ifnet *ifp;
 868
 869         mii_phy_reset(sc);
 870
 871         /* Handle any PHY specific procedures to finish the reset. */
 872         switch (bsc->mii_oui) {
 873         case MII_OUI_BROADCOM:
 874                 break;
 875         case MII_OUI_xxBROADCOM:
 876                 switch (bsc->mii_model) {
 877                 case MII_MODEL_xxBROADCOM_BCM5400:
 878                         bcm5401_load_dspcode(sc);
 879                         break;
 880                 case MII_MODEL_xxBROADCOM_BCM5401:
 881                         if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
 882                                 bcm5401_load_dspcode(sc);
 883                         break;
 884                 case MII_MODEL_xxBROADCOM_BCM5411:
 885                         bcm5411_load_dspcode(sc);
 886                         break;
 887                 }
 888                 break;
 889         case MII_OUI_xxBROADCOM_ALT1:
 890                 break;
 891         }
 892
 893         ifp = sc->mii_pdata->mii_ifp;
 894
 895         /* Find the driver associated with this PHY. */
 896         if (strcmp(ifp->if_dname, "bge") == 0)  {
 897                 bge_sc = ifp->if_softc;
 898         } else if (strcmp(ifp->if_dname, "bce") == 0) {
 899                 bce_sc = ifp->if_softc;
 900         }
 901
 902         /* Handle any bge (NetXtreme/NetLink) workarounds. */
 903         if (bge_sc) {
 904                 /* Fix up various bugs */
 905                 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
 906                         brgphy_fixup_5704_a0_bug(sc);
 907                 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG)
 908                         brgphy_fixup_adc_bug(sc);
 909                 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM)
 910                         brgphy_fixup_adjust_trim(sc);
 911                 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG)
 912                         brgphy_fixup_ber_bug(sc);
 913                 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG)
 914                         brgphy_fixup_crc_bug(sc);
 915                 if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG)
 916                         brgphy_fixup_jitter_bug(sc);
 917
 918                 brgphy_jumbo_settings(sc, ifp->if_mtu);
 919
 920                 if (bge_sc->bge_flags & BGE_FLAG_WIRESPEED)
 921                         brgphy_ethernet_wirespeed(sc);
 922
 923                 /* Enable Link LED on Dell boxes */
 924                 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) {
 925                         PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 926                             PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
 927                             ~BRGPHY_PHY_EXTCTL_3_LED);
 928                 }
 929
 930                 /* Adjust output voltage (From Linux driver) */
 931                 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
 932                         PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
 933
 934         /* Handle any bce (NetXtreme II) workarounds. */
 935         } else if (bce_sc) {
 936
 937                 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
 938                         BCE_CHIP_BOND_ID(bce_sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
 939
 940                         /* Store autoneg capabilities/results in digital block (Page 0) */
 941                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
 942                         PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
 943                                 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
 944                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 945
 946                         /* Enable fiber mode and autodetection */
 947                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
 948                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
 949                                 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
 950                                 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
 951
 952                         /* Enable parallel detection */
 953                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
 954                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
 955                                 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
 956
 957                         /* Advertise 2.5G support through next page during autoneg */
 958                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 959                                 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
 960                                         PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
 961                                         BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
 962
 963                         /* Increase TX signal amplitude */
 964                         if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
 965                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
 966                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
 967                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
 968                                         BRGPHY_5708S_TX_MISC_PG5);
 969                                 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
 970                                         PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
 971                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
 972                                         BRGPHY_5708S_DIG_PG0);
 973                         }
 974
 975                         /* Backplanes use special driver/pre-driver/pre-emphasis values. */
 976                         if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
 977                                 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
 978                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
 979                                                 BRGPHY_5708S_TX_MISC_PG5);
 980                                         PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
 981                                                 bce_sc->bce_port_hw_cfg &
 982                                                 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
 983                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
 984                                                 BRGPHY_5708S_DIG_PG0);
 985                         }
 986                 } else {
 987                         brgphy_fixup_ber_bug(sc);
 988                         brgphy_jumbo_settings(sc, ifp->if_mtu);
 989                         brgphy_ethernet_wirespeed(sc);
 990                 }
 991
 992         }
 993 }
 994