2 * Copyright (c) 1997-2000 Nicolas Souchu
3 * Copyright (c) 2001 Alcove - Nicolas Souchu
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
38 #include <sys/malloc.h>
40 #include <machine/bus.h>
41 #include <machine/resource.h>
47 #include <machine/vmparam.h>
50 #include <dev/ppbus/ppbconf.h>
51 #include <dev/ppbus/ppb_msq.h>
53 #include <dev/ppc/ppcvar.h>
54 #include <dev/ppc/ppcreg.h>
58 static void ppcintr(void *arg);
60 #define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */
61 #define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */
63 #define LOG_PPC(function, ppc, string) \
64 if (bootverbose) printf("%s: %s\n", function, string)
66 #if defined(__i386__) && defined(PC98)
67 #define PC98_IEEE_1284_DISABLE 0x100
68 #define PC98_IEEE_1284_PORT 0x140
71 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
73 devclass_t ppc_devclass;
74 const char ppc_driver_name[] = "ppc";
76 static char *ppc_models[] = {
77 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
78 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
79 "SMC FDC37C935", "PC87303", 0
82 /* list of available modes */
83 static char *ppc_avms[] = {
84 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
85 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
86 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
87 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
90 /* list of current executing modes
91 * Note that few modes do not actually exist.
93 static char *ppc_modes[] = {
94 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
95 "EPP", "EPP", "EPP", "ECP",
96 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
97 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
100 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
104 * BIOS printer list - used by BIOS probe.
106 #define BIOS_PPC_PORTS 0x408
107 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
108 #define BIOS_MAX_PPC 4
115 ppc_ecp_sync(device_t dev) {
118 struct ppc_data *ppc = DEVTOSOFTC(dev);
120 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
124 if ((r & 0xe0) != PPC_ECR_EPP)
127 for (i = 0; i < 100; i++) {
134 printf("ppc%d: ECP sync failed as data still " \
135 "present in FIFO.\n", ppc->ppc_unit);
143 * Detect parallel port FIFO
146 ppc_detect_fifo(struct ppc_data *ppc)
149 char ctr_sav, ctr, cc;
153 ecr_sav = r_ecr(ppc);
154 ctr_sav = r_ctr(ppc);
156 /* enter ECP configuration mode, no interrupt, no DMA */
159 /* read PWord size - transfers in FIFO mode must be PWord aligned */
160 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
162 /* XXX 16 and 32 bits implementations not supported */
163 if (ppc->ppc_pword != PPC_PWORD_8) {
164 LOG_PPC(__func__, ppc, "PWord not supported");
168 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
170 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
172 /* enter ECP test mode, no interrupt, no DMA */
176 for (i=0; i<1024; i++) {
177 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
183 LOG_PPC(__func__, ppc, "can't flush FIFO");
187 /* enable interrupts, no DMA */
190 /* determine readIntrThreshold
191 * fill the FIFO until serviceIntr is set
193 for (i=0; i<1024; i++) {
194 w_fifo(ppc, (char)i);
195 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
196 /* readThreshold reached */
199 if (r_ecr(ppc) & PPC_FIFO_FULL) {
206 LOG_PPC(__func__, ppc, "can't fill FIFO");
210 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
211 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
212 w_ecr(ppc, 0xd0); /* enable interrupts */
214 /* determine writeIntrThreshold
215 * empty the FIFO until serviceIntr is set
217 for (i=ppc->ppc_fifo; i>0; i--) {
218 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
219 LOG_PPC(__func__, ppc, "invalid data in FIFO");
222 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
223 /* writeIntrThreshold reached */
224 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
226 /* if FIFO empty before the last byte, error */
227 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
228 LOG_PPC(__func__, ppc, "data lost in FIFO");
233 /* FIFO must be empty after the last byte */
234 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
235 LOG_PPC(__func__, ppc, "can't empty the FIFO");
252 ppc_detect_port(struct ppc_data *ppc)
255 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
257 if (r_dtr(ppc) != 0xaa)
264 * EPP timeout, according to the PC87332 manual
265 * Semantics of clearing EPP timeout bit.
266 * PC87332 - reading SPP_STR does it...
267 * SMC - write 1 to EPP timeout bit XXX
268 * Others - (?) write 0 to EPP timeout bit
271 ppc_reset_epp_timeout(struct ppc_data *ppc)
277 w_str(ppc, r & 0xfe);
283 ppc_check_epp_timeout(struct ppc_data *ppc)
285 ppc_reset_epp_timeout(ppc);
287 return (!(r_str(ppc) & TIMEOUT));
291 * Configure current operating mode
294 ppc_generic_setmode(struct ppc_data *ppc, int mode)
298 /* check if mode is available */
299 if (mode && !(ppc->ppc_avm & mode))
302 /* if ECP mode, configure ecr register */
303 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
304 /* return to byte mode (keeping direction bit),
305 * no interrupt, no DMA to be able to change to
308 w_ecr(ppc, PPC_ECR_RESET);
309 ecr = PPC_DISABLE_INTR;
313 else if (mode & PPB_ECP)
314 /* select ECP mode */
316 else if (mode & PPB_PS2)
317 /* select PS2 mode with ECP */
320 /* select COMPATIBLE/NIBBLE mode */
326 ppc->ppc_mode = mode;
332 * The ppc driver is free to choose options like FIFO or DMA
333 * if ECP mode is available.
335 * The 'RAW' option allows the upper drivers to force the ppc mode
336 * even with FIFO, DMA available.
339 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
343 /* check if mode is available */
344 if (mode && !(ppc->ppc_avm & mode))
347 /* if ECP mode, configure ecr register */
348 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
349 /* return to byte mode (keeping direction bit),
350 * no interrupt, no DMA to be able to change to
353 w_ecr(ppc, PPC_ECR_RESET);
354 ecr = PPC_DISABLE_INTR;
357 /* select EPP mode */
359 else if (mode & PPB_ECP)
360 /* select ECP mode */
362 else if (mode & PPB_PS2)
363 /* select PS2 mode with ECP */
366 /* select COMPATIBLE/NIBBLE mode */
372 ppc->ppc_mode = mode;
377 #ifdef PPC_PROBE_CHIPSET
381 * Probe for a Natsemi PC873xx-family part.
383 * References in this function are to the National Semiconductor
384 * PC87332 datasheet TL/C/11930, May 1995 revision.
386 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
387 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
388 static int pc873xx_irqtab[] = {5, 7, 5, 0};
390 static int pc873xx_regstab[] = {
391 PC873_FER, PC873_FAR, PC873_PTR,
392 PC873_FCR, PC873_PCR, PC873_PMC,
393 PC873_TUP, PC873_SID, PC873_PNP0,
394 PC873_PNP1, PC873_LPTBA, -1
397 static char *pc873xx_rnametab[] = {
398 "FER", "FAR", "PTR", "FCR", "PCR",
399 "PMC", "TUP", "SID", "PNP0", "PNP1",
404 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
406 static int index = 0;
408 int ptr, pcr, val, i;
410 while ((idport = pc873xx_basetab[index++])) {
412 /* XXX should check first to see if this location is already claimed */
415 * Pull the 873xx through the power-on ID cycle (2.2,1.).
416 * We can't use this to locate the chip as it may already have
417 * been used by the BIOS.
419 (void)inb(idport); (void)inb(idport);
420 (void)inb(idport); (void)inb(idport);
423 * Read the SID byte. Possible values are :
430 outb(idport, PC873_SID);
431 val = inb(idport + 1);
432 if ((val & 0xf0) == 0x10) {
433 ppc->ppc_model = NS_PC87332;
434 } else if ((val & 0xf8) == 0x70) {
435 ppc->ppc_model = NS_PC87306;
436 } else if ((val & 0xf8) == 0x50) {
437 ppc->ppc_model = NS_PC87334;
438 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
439 documentation, but probing
441 ppc->ppc_model = NS_PC87303;
443 if (bootverbose && (val != 0xff))
444 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
445 continue ; /* not recognised */
448 /* print registers */
451 for (i=0; pc873xx_regstab[i] != -1; i++) {
452 outb(idport, pc873xx_regstab[i]);
453 printf(" %s=0x%x", pc873xx_rnametab[i],
454 inb(idport + 1) & 0xff);
460 * We think we have one. Is it enabled and where we want it to be?
462 outb(idport, PC873_FER);
463 val = inb(idport + 1);
464 if (!(val & PC873_PPENABLE)) {
466 printf("PC873xx parallel port disabled\n");
469 outb(idport, PC873_FAR);
470 val = inb(idport + 1);
471 /* XXX we should create a driver instance for every port found */
472 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
474 /* First try to change the port address to that requested... */
476 switch(ppc->ppc_base) {
494 outb(idport, PC873_FAR);
495 outb(idport + 1, val);
496 outb(idport + 1, val);
498 /* Check for success by reading back the value we supposedly
499 wrote and comparing...*/
501 outb(idport, PC873_FAR);
502 val = inb(idport + 1) & 0x3;
504 /* If we fail, report the failure... */
506 if (pc873xx_porttab[val] != ppc->ppc_base) {
508 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
509 pc873xx_porttab[val], ppc->ppc_base);
514 outb(idport, PC873_PTR);
515 ptr = inb(idport + 1);
517 /* get irq settings */
518 if (ppc->ppc_base == 0x378)
519 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
521 irq = pc873xx_irqtab[val];
524 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
527 * Check if irq settings are correct
529 if (irq != ppc->ppc_irq) {
531 * If the chipset is not locked and base address is 0x378,
532 * we have another chance
534 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
535 if (ppc->ppc_irq == 7) {
536 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
537 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
539 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
540 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
543 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
546 printf("PC873xx sorry, can't change irq setting\n");
550 printf("PC873xx irq settings are correct\n");
553 outb(idport, PC873_PCR);
554 pcr = inb(idport + 1);
556 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
558 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
560 ppc->ppc_avm |= PPB_NIBBLE;
564 if (pcr & PC873_EPPEN) {
565 ppc->ppc_avm |= PPB_EPP;
570 if (pcr & PC873_EPP19)
571 ppc->ppc_epp = EPP_1_9;
573 ppc->ppc_epp = EPP_1_7;
575 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
576 outb(idport, PC873_PTR);
577 ptr = inb(idport + 1);
578 if (ptr & PC873_EPPRDIR)
579 printf(", Regular mode");
581 printf(", Automatic mode");
583 } else if (pcr & PC873_ECPEN) {
584 ppc->ppc_avm |= PPB_ECP;
588 if (pcr & PC873_ECPCLK) { /* XXX */
589 ppc->ppc_avm |= PPB_PS2;
594 outb(idport, PC873_PTR);
595 ptr = inb(idport + 1);
596 if (ptr & PC873_EXTENDED) {
597 ppc->ppc_avm |= PPB_SPP;
604 printf("PC873xx unlocked");
606 if (chipset_mode & PPB_ECP) {
607 if ((chipset_mode & PPB_EPP) && bootverbose)
608 printf(", ECP+EPP not supported");
611 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
612 outb(idport + 1, pcr);
613 outb(idport + 1, pcr);
618 } else if (chipset_mode & PPB_EPP) {
619 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
620 pcr |= (PC873_EPPEN | PC873_EPP19);
621 outb(idport + 1, pcr);
622 outb(idport + 1, pcr);
624 ppc->ppc_epp = EPP_1_9; /* XXX */
629 /* enable automatic direction turnover */
630 if (ppc->ppc_model == NS_PC87332) {
631 outb(idport, PC873_PTR);
632 ptr = inb(idport + 1);
633 ptr &= ~PC873_EPPRDIR;
634 outb(idport + 1, ptr);
635 outb(idport + 1, ptr);
638 printf(", Automatic mode");
641 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
642 outb(idport + 1, pcr);
643 outb(idport + 1, pcr);
645 /* configure extended bit in PTR */
646 outb(idport, PC873_PTR);
647 ptr = inb(idport + 1);
649 if (chipset_mode & PPB_PS2) {
650 ptr |= PC873_EXTENDED;
656 /* default to NIBBLE mode */
657 ptr &= ~PC873_EXTENDED;
662 outb(idport + 1, ptr);
663 outb(idport + 1, ptr);
666 ppc->ppc_avm = chipset_mode;
672 ppc->ppc_type = PPC_TYPE_GENERIC;
673 ppc_generic_setmode(ppc, chipset_mode);
675 return(chipset_mode);
681 * ppc_smc37c66xgt_detect
683 * SMC FDC37C66xGT configuration.
686 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
691 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
693 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
696 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
699 * Detection: enter configuration mode and read CRD register.
703 outb(csr, SMC665_iCODE);
704 outb(csr, SMC665_iCODE);
708 if (inb(cio) == 0x65) {
713 for (i = 0; i < 2; i++) {
715 outb(csr, SMC666_iCODE);
716 outb(csr, SMC666_iCODE);
720 if (inb(cio) == 0x66) {
725 /* Another chance, CSR may be hard-configured to be at 0x370 */
731 * If chipset not found, do not continue.
739 /* read the port's address: bits 0 and 1 of CR1 */
740 r = inb(cio) & SMC_CR1_ADDR;
741 if (port_address[(int)r] != ppc->ppc_base)
744 ppc->ppc_model = type;
747 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
748 * If SPP mode is detected, try to set ECP+EPP mode
753 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit,
757 printf(" CR4=0x%x", inb(cio) & 0xff);
764 /* autodetect mode */
766 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
767 if (type == SMC_37C666GT) {
768 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
770 printf(" configuration hardwired, supposing " \
774 if ((inb(cio) & SMC_CR1_MODE) == 0) {
775 /* already in extended parallel port mode, read CR4 */
777 r = (inb(cio) & SMC_CR4_EMODE);
781 ppc->ppc_avm |= PPB_SPP;
787 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
793 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
799 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
801 printf(" ECP+EPP SPP");
805 /* not an extended port mode */
806 ppc->ppc_avm |= PPB_SPP;
813 ppc->ppc_avm = chipset_mode;
815 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
816 if (type == SMC_37C666GT)
820 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
821 /* do not use ECP when the mode is not forced to */
822 outb(cio, r | SMC_CR1_MODE);
826 /* an extended mode is selected */
827 outb(cio, r & ~SMC_CR1_MODE);
829 /* read CR4 register and reset mode field */
831 r = inb(cio) & ~SMC_CR4_EMODE;
833 if (chipset_mode & PPB_ECP) {
834 if (chipset_mode & PPB_EPP) {
835 outb(cio, r | SMC_ECPEPP);
839 outb(cio, r | SMC_ECP);
845 outb(cio, r | SMC_EPPSPP);
850 ppc->ppc_avm = chipset_mode;
853 /* set FIFO threshold to 16 */
854 if (ppc->ppc_avm & PPB_ECP) {
865 if (ppc->ppc_avm & PPB_EPP) {
871 * Set the EPP protocol...
872 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
874 if (ppc->ppc_epp == EPP_1_9)
875 outb(cio, (r & ~SMC_CR4_EPPTYPE));
877 outb(cio, (r | SMC_CR4_EPPTYPE));
880 /* end config mode */
883 ppc->ppc_type = PPC_TYPE_SMCLIKE;
884 ppc_smclike_setmode(ppc, chipset_mode);
886 return (chipset_mode);
890 * SMC FDC37C935 configuration
891 * Found on many Alpha machines
894 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
900 outb(SMC935_CFG, 0x55); /* enter config mode */
901 outb(SMC935_CFG, 0x55);
904 outb(SMC935_IND, SMC935_ID); /* check device id */
905 if (inb(SMC935_DAT) == 0x2)
909 outb(SMC935_CFG, 0xaa); /* exit config mode */
913 ppc->ppc_model = type;
915 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
916 outb(SMC935_DAT, 3); /* which is logical device 3 */
918 /* set io port base */
919 outb(SMC935_IND, SMC935_PORTHI);
920 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
921 outb(SMC935_IND, SMC935_PORTLO);
922 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
925 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
927 ppc->ppc_avm = chipset_mode;
928 outb(SMC935_IND, SMC935_PPMODE);
929 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
931 /* SPP + EPP or just plain SPP */
932 if (chipset_mode & (PPB_SPP)) {
933 if (chipset_mode & PPB_EPP) {
934 if (ppc->ppc_epp == EPP_1_9) {
935 outb(SMC935_IND, SMC935_PPMODE);
936 outb(SMC935_DAT, SMC935_EPP19SPP);
938 if (ppc->ppc_epp == EPP_1_7) {
939 outb(SMC935_IND, SMC935_PPMODE);
940 outb(SMC935_DAT, SMC935_EPP17SPP);
943 outb(SMC935_IND, SMC935_PPMODE);
944 outb(SMC935_DAT, SMC935_SPP);
948 /* ECP + EPP or just plain ECP */
949 if (chipset_mode & PPB_ECP) {
950 if (chipset_mode & PPB_EPP) {
951 if (ppc->ppc_epp == EPP_1_9) {
952 outb(SMC935_IND, SMC935_PPMODE);
953 outb(SMC935_DAT, SMC935_ECPEPP19);
955 if (ppc->ppc_epp == EPP_1_7) {
956 outb(SMC935_IND, SMC935_PPMODE);
957 outb(SMC935_DAT, SMC935_ECPEPP17);
960 outb(SMC935_IND, SMC935_PPMODE);
961 outb(SMC935_DAT, SMC935_ECP);
966 outb(SMC935_CFG, 0xaa); /* exit config mode */
968 ppc->ppc_type = PPC_TYPE_SMCLIKE;
969 ppc_smclike_setmode(ppc, chipset_mode);
971 return (chipset_mode);
975 * Winbond W83877F stuff
977 * EFER: extended function enable register
978 * EFIR: extended function index register
979 * EFDR: extended function data register
981 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
982 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
984 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
985 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
986 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
987 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
990 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
993 unsigned char r, hefere, hefras;
995 for (i = 0; i < 4; i ++) {
996 /* first try to enable configuration registers */
997 efer = w83877f_efers[i];
999 /* write the key to the EFER */
1000 for (j = 0; j < w83877f_keyiter[i]; j ++)
1001 outb (efer, w83877f_keys[i]);
1003 /* then check HEFERE and HEFRAS bits */
1005 hefere = inb(efdr) & WINB_HEFERE;
1008 hefras = inb(efdr) & WINB_HEFRAS;
1012 * 0 1 write 89h to 250h (power-on default)
1013 * 1 0 write 86h twice to 3f0h
1014 * 1 1 write 87h twice to 3f0h
1015 * 0 0 write 88h to 250h
1017 if ((hefere | hefras) == w83877f_hefs[i])
1021 return (-1); /* failed */
1024 /* check base port address - read from CR23 */
1026 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1029 /* read CHIP ID from CR9/bits0-3 */
1032 switch (inb(efdr) & WINB_CHIPID) {
1033 case WINB_W83877F_ID:
1034 ppc->ppc_model = WINB_W83877F;
1037 case WINB_W83877AF_ID:
1038 ppc->ppc_model = WINB_W83877AF;
1042 ppc->ppc_model = WINB_UNKNOWN;
1046 /* dump of registers */
1047 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]);
1048 for (i = 0; i <= 0xd; i ++) {
1050 printf("0x%x ", inb(efdr));
1052 for (i = 0x10; i <= 0x17; i ++) {
1054 printf("0x%x ", inb(efdr));
1057 printf("0x%x ", inb(efdr));
1058 for (i = 0x20; i <= 0x29; i ++) {
1060 printf("0x%x ", inb(efdr));
1063 printf("ppc%d:", ppc->ppc_unit);
1066 ppc->ppc_type = PPC_TYPE_GENERIC;
1068 if (!chipset_mode) {
1069 /* autodetect mode */
1073 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1077 r |= (inb(efdr) & WINB_PRTMODS2);
1082 printf("ppc%d: W83757 compatible mode\n",
1084 return (-1); /* generic or SMC-like */
1091 printf(" not in parallel port mode\n");
1094 case (WINB_PARALLEL | WINB_EPP_SPP):
1095 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1100 case (WINB_PARALLEL | WINB_ECP):
1101 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1106 case (WINB_PARALLEL | WINB_ECP_EPP):
1107 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1108 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1111 printf(" ECP+EPP SPP");
1114 printf("%s: unknown case (0x%x)!\n", __func__, r);
1120 /* select CR9 and set PRTMODS2 bit */
1122 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1124 /* select CR0 and reset PRTMODSx bits */
1126 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1128 if (chipset_mode & PPB_ECP) {
1129 if (chipset_mode & PPB_EPP) {
1130 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1134 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1137 outb(efdr, inb(efdr) | WINB_ECP);
1142 /* select EPP_SPP otherwise */
1143 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1147 ppc->ppc_avm = chipset_mode;
1153 /* exit configuration mode */
1156 switch (ppc->ppc_type) {
1157 case PPC_TYPE_SMCLIKE:
1158 ppc_smclike_setmode(ppc, chipset_mode);
1161 ppc_generic_setmode(ppc, chipset_mode);
1165 return (chipset_mode);
1170 * ppc_generic_detect
1173 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1175 /* default to generic */
1176 ppc->ppc_type = PPC_TYPE_GENERIC;
1179 printf("ppc%d:", ppc->ppc_unit);
1181 /* first, check for ECP */
1182 w_ecr(ppc, PPC_ECR_PS2);
1183 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1184 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1188 /* search for SMC style ECP+EPP mode */
1189 w_ecr(ppc, PPC_ECR_EPP);
1192 /* try to reset EPP timeout bit */
1193 if (ppc_check_epp_timeout(ppc)) {
1194 ppc->ppc_dtm |= PPB_EPP;
1196 if (ppc->ppc_dtm & PPB_ECP) {
1197 /* SMC like chipset found */
1198 ppc->ppc_model = SMC_LIKE;
1199 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1208 /* restore to standard mode */
1209 w_ecr(ppc, PPC_ECR_STD);
1212 /* XXX try to detect NIBBLE and PS2 modes */
1213 ppc->ppc_dtm |= PPB_NIBBLE;
1219 ppc->ppc_avm = chipset_mode;
1221 ppc->ppc_avm = ppc->ppc_dtm;
1226 switch (ppc->ppc_type) {
1227 case PPC_TYPE_SMCLIKE:
1228 ppc_smclike_setmode(ppc, chipset_mode);
1231 ppc_generic_setmode(ppc, chipset_mode);
1235 return (chipset_mode);
1241 * mode is the mode suggested at boot
1244 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1246 #ifdef PPC_PROBE_CHIPSET
1249 /* list of supported chipsets */
1250 int (*chipset_detect[])(struct ppc_data *, int) = {
1252 ppc_smc37c66xgt_detect,
1254 ppc_smc37c935_detect,
1260 /* if can't find the port and mode not forced return error */
1261 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1262 return (EIO); /* failed, port not present */
1264 /* assume centronics compatible mode is supported */
1265 ppc->ppc_avm = PPB_COMPATIBLE;
1267 #ifdef PPC_PROBE_CHIPSET
1268 /* we have to differenciate available chipset modes,
1269 * chipset running modes and IEEE-1284 operating modes
1271 * after detection, the port must support running in compatible mode
1273 if (ppc->ppc_flags & 0x40) {
1275 printf("ppc: chipset forced to generic\n");
1278 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1280 #ifdef PPC_PROBE_CHIPSET
1282 for (i=0; chipset_detect[i] != NULL; i++) {
1283 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1284 ppc->ppc_mode = mode;
1291 /* configure/detect ECP FIFO */
1292 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1293 ppc_detect_fifo(ppc);
1299 * ppc_exec_microseq()
1301 * Execute a microsequence.
1302 * Microsequence mechanism is supposed to handle fast I/O operations.
1305 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1307 struct ppc_data *ppc = DEVTOSOFTC(dev);
1308 struct ppb_microseq *mi;
1315 register int accum = 0;
1316 register char *ptr = 0;
1318 struct ppb_microseq *stack = 0;
1320 /* microsequence registers are equivalent to PC-like port registers */
1322 #define r_reg(reg,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, reg))
1323 #define w_reg(reg, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, reg, byte))
1325 #define INCR_PC (mi ++) /* increment program counter */
1329 switch (mi->opcode) {
1331 cc = r_reg(mi->arg[0].i, ppc);
1332 cc &= (char)mi->arg[2].i; /* clear mask */
1333 cc |= (char)mi->arg[1].i; /* assert mask */
1334 w_reg(mi->arg[0].i, ppc, cc);
1338 case MS_OP_RASSERT_P:
1342 if ((len = mi->arg[0].i) == MS_ACCUM) {
1343 accum = ppc->ppc_accum;
1344 for (; accum; accum--)
1345 w_reg(reg, ppc, *ptr++);
1346 ppc->ppc_accum = accum;
1348 for (i=0; i<len; i++)
1349 w_reg(reg, ppc, *ptr++);
1355 case MS_OP_RFETCH_P:
1357 mask = (char)mi->arg[2].i;
1360 if ((len = mi->arg[0].i) == MS_ACCUM) {
1361 accum = ppc->ppc_accum;
1362 for (; accum; accum--)
1363 *ptr++ = r_reg(reg, ppc) & mask;
1364 ppc->ppc_accum = accum;
1366 for (i=0; i<len; i++)
1367 *ptr++ = r_reg(reg, ppc) & mask;
1374 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1382 /* let's suppose the next instr. is the same */
1384 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1385 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1387 if (mi->opcode == MS_OP_DELAY) {
1388 DELAY(mi->arg[0].i);
1396 pause("ppbdelay", mi->arg[0].i * (hz/1000));
1402 iter = mi->arg[1].i;
1403 p = (char *)mi->arg[2].p;
1405 /* XXX delay limited to 255 us */
1406 for (i=0; i<iter; i++) {
1407 w_reg(reg, ppc, *p++);
1408 DELAY((unsigned char)*p++);
1414 ppc->ppc_accum = mi->arg[0].i;
1419 if (--ppc->ppc_accum > 0)
1426 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1433 if ((cc & (char)mi->arg[0].i) == 0)
1440 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1448 * If the C call returns !0 then end the microseq.
1449 * The current state of ptr is passed to the C function
1451 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1458 ppc->ppc_ptr = (char *)mi->arg[0].p;
1464 panic("%s: too much calls", __func__);
1467 /* store the state of the actual
1472 /* jump to the new microsequence */
1473 mi = (struct ppb_microseq *)mi->arg[0].p;
1480 /* retrieve microseq and pc state before the call */
1483 /* reset the stack */
1486 /* XXX return code */
1494 /* can't return to ppb level during the execution
1495 * of a submicrosequence */
1497 panic("%s: can't return to ppb level",
1500 /* update pc for ppb level of execution */
1503 /* return to ppb level of execution */
1507 panic("%s: unknown microsequence opcode 0x%x",
1508 __func__, mi->opcode);
1518 device_t dev = (device_t)arg;
1519 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev);
1520 u_char ctr, ecr, str;
1526 #if defined(PPC_DEBUG) && PPC_DEBUG > 1
1527 printf("![%x/%x/%x]", ctr, ecr, str);
1530 /* don't use ecp mode with IRQENABLE set */
1531 if (ctr & IRQENABLE) {
1535 /* interrupts are generated by nFault signal
1536 * only in ECP mode */
1537 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1538 /* check if ppc driver has programmed the
1539 * nFault interrupt */
1540 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1542 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1543 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1545 /* shall be handled by underlying layers XXX */
1550 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1551 /* disable interrupts (should be done by hardware though) */
1552 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1553 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1556 /* check if DMA completed */
1557 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1562 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1565 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1569 ppc->ppc_dmadone(ppc);
1570 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1572 /* wakeup the waiting process */
1576 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1578 /* classic interrupt I/O */
1579 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1586 ppc_read(device_t dev, char *buf, int len, int mode)
1592 ppc_write(device_t dev, char *buf, int len, int how)
1598 ppc_reset_epp(device_t dev)
1600 struct ppc_data *ppc = DEVTOSOFTC(dev);
1602 ppc_reset_epp_timeout(ppc);
1608 ppc_setmode(device_t dev, int mode)
1610 struct ppc_data *ppc = DEVTOSOFTC(dev);
1612 switch (ppc->ppc_type) {
1613 case PPC_TYPE_SMCLIKE:
1614 return (ppc_smclike_setmode(ppc, mode));
1617 case PPC_TYPE_GENERIC:
1619 return (ppc_generic_setmode(ppc, mode));
1628 ppc_probe(device_t dev, int rid)
1631 static short next_bios_ppc = 0;
1633 unsigned int pc98_ieee_mode = 0x00;
1637 struct ppc_data *ppc;
1642 * Allocate the ppc_data structure.
1644 ppc = DEVTOSOFTC(dev);
1645 bzero(ppc, sizeof(struct ppc_data));
1647 ppc->rid_ioport = rid;
1649 /* retrieve ISA parameters */
1650 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL);
1654 * If port not specified, use bios list.
1658 if (next_bios_ppc == 0) {
1659 /* Use default IEEE-1284 port of NEC PC-98x1 */
1660 port = PC98_IEEE_1284_PORT;
1664 "parallel port found at 0x%x\n",
1668 if((next_bios_ppc < BIOS_MAX_PPC) &&
1669 (*(BIOS_PORTS+next_bios_ppc) != 0) ) {
1670 port = *(BIOS_PORTS+next_bios_ppc++);
1672 device_printf(dev, "parallel port found at 0x%x\n",
1675 device_printf(dev, "parallel port not found.\n");
1679 bus_set_resource(dev, SYS_RES_IOPORT, rid, port,
1680 IO_LPTSIZE_EXTENDED);
1684 /* IO port is mandatory */
1686 /* Try "extended" IO port range...*/
1687 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1688 &ppc->rid_ioport, 0, ~0,
1689 IO_LPTSIZE_EXTENDED, RF_ACTIVE);
1691 if (ppc->res_ioport != 0) {
1693 device_printf(dev, "using extended I/O port range\n");
1695 /* Failed? If so, then try the "normal" IO port range... */
1696 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1697 &ppc->rid_ioport, 0, ~0,
1700 if (ppc->res_ioport != 0) {
1702 device_printf(dev, "using normal I/O port range\n");
1704 device_printf(dev, "cannot reserve I/O port range\n");
1709 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1711 ppc->bsh = rman_get_bushandle(ppc->res_ioport);
1712 ppc->bst = rman_get_bustag(ppc->res_ioport);
1714 ppc->ppc_flags = device_get_flags(dev);
1716 if (!(ppc->ppc_flags & 0x20)) {
1717 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1720 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1726 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1728 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1730 ppc->ppc_unit = device_get_unit(dev);
1731 ppc->ppc_model = GENERIC;
1733 ppc->ppc_mode = PPB_COMPATIBLE;
1734 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1736 ppc->ppc_type = PPC_TYPE_GENERIC;
1738 #if defined(__i386__) && defined(PC98)
1740 * IEEE STD 1284 Function Check and Enable
1741 * for default IEEE-1284 port of NEC PC-98x1
1743 if (ppc->ppc_base == PC98_IEEE_1284_PORT &&
1744 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1745 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1746 pc98_ieee_mode = tmp;
1747 if ((tmp & 0x10) == 0x10) {
1748 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10);
1749 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1750 if ((tmp & 0x10) == 0x10)
1753 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10);
1754 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1755 if ((tmp & 0x10) != 0x10)
1758 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10);
1763 * Try to detect the chipset and its mode.
1765 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1771 #if defined(__i386__) && defined(PC98)
1772 if (ppc->ppc_base == PC98_IEEE_1284_PORT &&
1773 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1774 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode);
1777 if (ppc->res_irq != 0) {
1778 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1781 if (ppc->res_ioport != 0) {
1782 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1785 if (ppc->res_drq != 0) {
1786 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1793 ppc_attach(device_t dev)
1795 struct ppc_data *ppc = DEVTOSOFTC(dev);
1799 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1800 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1801 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1802 ppc_epp_protocol[ppc->ppc_epp] : "");
1805 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1806 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1808 /* add ppbus as a child of this isa to parallel bridge */
1809 ppbus = device_add_child(dev, "ppbus", -1);
1812 * Probe the ppbus and attach devices found.
1814 device_probe_and_attach(ppbus);
1816 /* register the ppc interrupt handler as default */
1818 /* default to the tty mask for registration */ /* XXX */
1819 if (bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY,
1820 NULL, ppcintr, dev, &ppc->intr_cookie) == 0) {
1822 /* remember the ppcintr is registered */
1823 ppc->ppc_registered = 1;
1831 ppc_detach(device_t dev)
1833 struct ppc_data *ppc = DEVTOSOFTC(dev);
1837 if (ppc->res_irq == 0) {
1841 /* detach & delete all children */
1842 if (!device_get_children(dev, &children, &nchildren)) {
1843 for (i = 0; i < nchildren; i++)
1845 device_delete_child(dev, children[i]);
1846 free(children, M_TEMP);
1849 if (ppc->res_irq != 0) {
1850 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie);
1851 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1854 if (ppc->res_ioport != 0) {
1855 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1858 if (ppc->res_drq != 0) {
1859 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1867 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
1869 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
1872 bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
1875 bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1878 bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1881 bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
1884 bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1887 bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1890 return (r_dtr(ppc));
1892 return (r_str(ppc));
1894 return (r_ctr(ppc));
1896 return (r_epp_A(ppc));
1898 return (r_epp_D(ppc));
1900 return (r_ecr(ppc));
1902 return (r_fifo(ppc));
1925 panic("%s: unknown I/O operation", __func__);
1929 return (0); /* not significative */
1933 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
1935 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1938 case PPC_IVAR_EPP_PROTO:
1939 *val = (u_long)ppc->ppc_epp;
1942 *val = (u_long)ppc->ppc_irq;
1952 * Resource is useless here since ppbus devices' interrupt handlers are
1953 * multiplexed to the same resource initially allocated by ppc
1956 ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
1957 driver_filter_t *filt, void (*ihand)(void *), void *arg, void **cookiep)
1960 struct ppc_data *ppc = DEVTOSOFTC(bus);
1962 if (ppc->ppc_registered) {
1963 /* XXX refuse registration if DMA is in progress */
1965 /* first, unregister the default interrupt handler */
1966 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus),
1967 bus, ppc->res_irq, ppc->intr_cookie)))
1970 /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */
1971 /* ppc->res_irq); */
1973 /* DMA/FIFO operation won't be possible anymore */
1974 ppc->ppc_registered = 0;
1978 * pass registration to the upper layer, ignore the incoming
1981 return (BUS_SETUP_INTR(device_get_parent(bus), child,
1982 r, flags, filt, ihand, arg, cookiep));
1986 * When no underlying device has a registered interrupt, register the ppc
1990 ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih)
1993 struct ppc_data *ppc = DEVTOSOFTC(bus);
1994 device_t parent = device_get_parent(bus);
1996 /* pass unregistration to the upper layer */
1997 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih)))
2000 /* default to the tty mask for registration */ /* XXX */
2002 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq,
2003 INTR_TYPE_TTY, NULL, ppcintr, bus, &ppc->intr_cookie))) {
2005 /* remember the ppcintr is registered */
2006 ppc->ppc_registered = 1;
2012 MODULE_DEPEND(ppc, ppbus, 1, 1, 1);