2 * Copyright (c) 2001 Alcove - Nicolas Souchu
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * Parallel Port Chipset type.
36 #define SMC_37C665GT 1
37 #define SMC_37C666GT 2
40 #define INTEL_820191AA 5 /* XXX not implemented */
42 #define WINB_W83877F 7
43 #define WINB_W83877AF 8
44 #define WINB_UNKNOWN 9
50 * Parallel Port Chipset Type. SMC versus GENERIC (others)
52 #define PPC_TYPE_SMCLIKE 0
53 #define PPC_TYPE_GENERIC 1
56 * Generic structure to hold parallel port chipset info.
61 int ppc_model; /* chipset model if detected */
62 int ppc_type; /* generic or smclike chipset type */
64 int ppc_mode; /* chipset current mode */
65 int ppc_avm; /* chipset available modes */
66 int ppc_dtm; /* chipset detected modes */
68 #define PPC_IRQ_NONE 0x0
69 #define PPC_IRQ_nACK 0x1
70 #define PPC_IRQ_DMA 0x2
71 #define PPC_IRQ_FIFO 0x4
72 #define PPC_IRQ_nFAULT 0x8
73 int ppc_irqstat; /* remind irq settings */
75 #define PPC_DMA_INIT 0x01
76 #define PPC_DMA_STARTED 0x02
77 #define PPC_DMA_COMPLETE 0x03
78 #define PPC_DMA_INTERRUPTED 0x04
79 #define PPC_DMA_ERROR 0x05
80 int ppc_dmastat; /* dma state */
81 int ppc_dmachan; /* dma channel */
82 int ppc_dmaflags; /* dma transfer flags */
83 caddr_t ppc_dmaddr; /* buffer address */
84 u_int ppc_dmacnt; /* count of bytes sent with dma */
85 void (*ppc_dmadone)(struct ppc_data*);
87 #define PPC_PWORD_MASK 0x30
88 #define PPC_PWORD_16 0x00
89 #define PPC_PWORD_8 0x10
90 #define PPC_PWORD_32 0x20
91 char ppc_pword; /* PWord size */
92 short ppc_fifo; /* FIFO threshold */
94 short ppc_wthr; /* writeIntrThresold */
95 short ppc_rthr; /* readIntrThresold */
97 char *ppc_ptr; /* microseq current pointer */
98 int ppc_accum; /* microseq accumulator */
99 int ppc_base; /* parallel port base address */
100 int ppc_epp; /* EPP mode (1.7 or 1.9) */
103 unsigned char ppc_flags;
105 device_t ppbus; /* parallel port chipset corresponding ppbus */
107 int rid_irq, rid_drq, rid_ioport;
108 struct resource *res_irq, *res_drq, *res_ioport;
110 bus_space_handle_t bsh;
115 int ppc_registered; /* 1 if ppcintr() is the registered interrupt */
119 * Parallel Port Chipset registers.
121 #define PPC_SPP_DTR 0 /* SPP data register */
122 #define PPC_ECP_A_FIFO 0 /* ECP Address fifo register */
123 #define PPC_SPP_STR 1 /* SPP status register */
124 #define PPC_SPP_CTR 2 /* SPP control register */
125 #define PPC_EPP_ADDR 3 /* EPP address register (8 bit) */
126 #define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */
127 #if defined(__i386__) && defined(PC98)
128 #define PPC_1284_ENABLE 0x09 /* IEEE STD 1284 Enable register */
129 #define PPC_ECP_D_FIFO 0x0c /* ECP Data fifo register */
130 #define PPC_ECP_CNFGA 0x0c /* Configuration register A */
131 #define PPC_ECP_CNFGB 0x0d /* Configuration register B */
132 #define PPC_ECP_ECR 0x0e /* ECP extended control register */
134 #define PPC_ECP_D_FIFO 0x400 /* ECP Data fifo register */
135 #define PPC_ECP_CNFGA 0x400 /* Configuration register A */
136 #define PPC_ECP_CNFGB 0x401 /* Configuration register B */
137 #define PPC_ECP_ECR 0x402 /* ECP extended control register */
140 #define PPC_FIFO_EMPTY 0x1 /* ecr register - bit 0 */
141 #define PPC_FIFO_FULL 0x2 /* ecr register - bit 1 */
142 #define PPC_SERVICE_INTR 0x4 /* ecr register - bit 2 */
143 #define PPC_ENABLE_DMA 0x8 /* ecr register - bit 3 */
144 #define PPC_nFAULT_INTR 0x10 /* ecr register - bit 4 */
145 #define PPC_ECR_STD 0x0
146 #define PPC_ECR_PS2 0x20
147 #define PPC_ECR_FIFO 0x40
148 #define PPC_ECR_ECP 0x60
149 #define PPC_ECR_EPP 0x80
151 #define PPC_DISABLE_INTR (PPC_SERVICE_INTR | PPC_nFAULT_INTR)
152 #define PPC_ECR_RESET (PPC_ECR_PS2 | PPC_DISABLE_INTR)
154 #define r_dtr(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_SPP_DTR))
155 #define r_str(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_SPP_STR))
156 #define r_ctr(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_SPP_CTR))
158 #define r_epp_A(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_EPP_ADDR))
159 #define r_epp_D(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_EPP_DATA))
160 #define r_cnfgA(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_ECP_CNFGA))
161 #define r_cnfgB(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_ECP_CNFGB))
162 #define r_ecr(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_ECP_ECR))
163 #define r_fifo(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_ECP_D_FIFO))
165 #define w_dtr(ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, PPC_SPP_DTR, byte))
166 #define w_str(ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, PPC_SPP_STR, byte))
167 #define w_ctr(ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, PPC_SPP_CTR, byte))
169 #define w_epp_A(ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, PPC_EPP_ADDR, byte))
170 #define w_epp_D(ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, PPC_EPP_DATA, byte))
171 #define w_ecr(ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, PPC_ECP_ECR, byte))
172 #define w_fifo(ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, PPC_ECP_D_FIFO, byte))
175 * Register defines for the PC873xx parts
178 #define PC873_FER 0x00
179 #define PC873_PPENABLE (1<<0)
180 #define PC873_FAR 0x01
181 #define PC873_PTR 0x02
182 #define PC873_CFGLOCK (1<<6)
183 #define PC873_EPPRDIR (1<<7)
184 #define PC873_EXTENDED (1<<7)
185 #define PC873_LPTBIRQ7 (1<<3)
186 #define PC873_FCR 0x03
187 #define PC873_ZWS (1<<5)
188 #define PC873_ZWSPWDN (1<<6)
189 #define PC873_PCR 0x04
190 #define PC873_EPPEN (1<<0)
191 #define PC873_EPP19 (1<<1)
192 #define PC873_ECPEN (1<<2)
193 #define PC873_ECPCLK (1<<3)
194 #define PC873_PMC 0x06
195 #define PC873_TUP 0x07
196 #define PC873_SID 0x08
197 #define PC873_PNP0 0x1b
198 #define PC873_PNP1 0x1c
199 #define PC873_LPTBA 0x19
202 * Register defines for the SMC FDC37C66xGT parts
206 #define SMC665_iCODE 0x55
207 #define SMC666_iCODE 0x44
209 /* Base configuration ports */
210 #define SMC66x_CSR 0x3F0
211 #define SMC666_CSR 0x370 /* hard-configured value for 666 */
214 #define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */
215 #define SMC_CR1_MODE (1<<3) /* bit 3 */
216 #define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */
217 #define SMC_CR4_EPPTYPE (1<<6) /* bit 6 */
220 #define SMC_SPP 0x0 /* SPP */
221 #define SMC_EPPSPP 0x1 /* EPP and SPP */
222 #define SMC_ECP 0x2 /* ECP */
223 #define SMC_ECPEPP 0x3 /* ECP and EPP */
226 * Register defines for the SMC FDC37C935 parts
229 /* Configuration ports */
230 #define SMC935_CFG 0x370
231 #define SMC935_IND 0x370
232 #define SMC935_DAT 0x371
235 #define SMC935_LOGDEV 0x7
236 #define SMC935_ID 0x20
237 #define SMC935_PORTHI 0x60
238 #define SMC935_PORTLO 0x61
239 #define SMC935_PPMODE 0xf0
241 /* Parallel port modes */
242 #define SMC935_SPP 0x38 + 0
243 #define SMC935_EPP19SPP 0x38 + 1
244 #define SMC935_ECP 0x38 + 2
245 #define SMC935_ECPEPP19 0x38 + 3
246 #define SMC935_CENT 0x38 + 4
247 #define SMC935_EPP17SPP 0x38 + 5
248 #define SMC935_UNUSED 0x38 + 6
249 #define SMC935_ECPEPP17 0x38 + 7
252 * Register defines for the Winbond W83877F parts
255 #define WINB_W83877F_ID 0xa
256 #define WINB_W83877AF_ID 0xb
258 /* Configuration bits */
259 #define WINB_HEFERE (1<<5) /* CROC bit 5 */
260 #define WINB_HEFRAS (1<<0) /* CR16 bit 0 */
262 #define WINB_PNPCVS (1<<2) /* CR16 bit 2 */
263 #define WINB_CHIPID 0xf /* CR9 bits 0-3 */
265 #define WINB_PRTMODS0 (1<<2) /* CR0 bit 2 */
266 #define WINB_PRTMODS1 (1<<3) /* CR0 bit 3 */
267 #define WINB_PRTMODS2 (1<<7) /* CR9 bit 7 */
269 /* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */
270 #define WINB_W83757 0x0
271 #define WINB_EXTFDC 0x4
272 #define WINB_EXTADP 0x8
273 #define WINB_EXT2FDD 0xc
274 #define WINB_JOYSTICK 0x80
276 #define WINB_PARALLEL 0x80
277 #define WINB_EPP_SPP 0x4
279 #define WINB_ECP_EPP 0xc