2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
26 * This driver exists largely as a result of other people's efforts.
27 * Much of register handling is based on NetBSD CMI8x38 audio driver
28 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien
29 * <cltien@cmedia.com.tw> clarified points regarding the DMA related
30 * registers and the 8738 mixer devices. His Linux driver was also a
31 * useful reference point.
35 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>.
37 * This card/code does not always manage to sample at 44100 - actual
38 * rate drifts slightly between recordings (usually 0-3%). No
39 * differences visible in register dumps between times that work and
43 #include <dev/sound/pcm/sound.h>
44 #include <dev/sound/pci/cmireg.h>
45 #include <dev/sound/isa/sb.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
50 #include <sys/sysctl.h>
51 #include <dev/sound/midi/mpu401.h>
54 #include "mpufoi_if.h"
56 SND_DECLARE_FILE("$FreeBSD$");
58 /* Supported chip ID's */
59 #define CMI8338A_PCI_ID 0x010013f6
60 #define CMI8338B_PCI_ID 0x010113f6
61 #define CMI8738_PCI_ID 0x011113f6
62 #define CMI8738B_PCI_ID 0x011213f6
63 #define CMI120_USB_ID 0x01030d8c
65 /* Buffer size max is 64k for permitted DMA boundaries */
66 #define CMI_DEFAULT_BUFSZ 16384
68 /* Interrupts per length of buffer */
69 #define CMI_INTR_PER_BUFFER 2
71 /* Clarify meaning of named defines in cmireg.h */
72 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES
73 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES
74 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES
75 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES
77 /* Our indication of custom mixer control */
78 #define CMPCI_NON_SB16_CONTROL 0xff
80 /* Debugging macro's */
83 #define DEB(x) /* x */
87 #define DEBMIX(x) /* x */
90 /* ------------------------------------------------------------------------- */
96 struct sc_info *parent;
97 struct pcm_channel *channel;
98 struct snd_dbuf *buffer;
99 u_int32_t fmt, spd, phys_buf, bps;
100 u_int32_t dma_active:1, dma_was_active:1;
108 bus_space_handle_t sh;
109 bus_dma_tag_t parent_dmat;
110 struct resource *reg, *irq;
117 struct sc_chinfo pch, rch;
120 mpu401_intr_t *mpu_intr;
121 struct resource *mpu_reg;
123 bus_space_tag_t mpu_bt;
124 bus_space_handle_t mpu_bh;
129 static u_int32_t cmi_fmt[] = {
131 AFMT_STEREO | AFMT_U8,
133 AFMT_STEREO | AFMT_S16_LE,
137 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0};
139 /* ------------------------------------------------------------------------- */
140 /* Register Utilities */
143 cmi_rd(struct sc_info *sc, int regno, int size)
147 return bus_space_read_1(sc->st, sc->sh, regno);
149 return bus_space_read_2(sc->st, sc->sh, regno);
151 return bus_space_read_4(sc->st, sc->sh, regno);
153 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size));
159 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
163 bus_space_write_1(sc->st, sc->sh, regno, data);
166 bus_space_write_2(sc->st, sc->sh, regno, data);
169 bus_space_write_4(sc->st, sc->sh, regno, data);
175 cmi_partial_wr4(struct sc_info *sc,
176 int reg, int shift, u_int32_t mask, u_int32_t val)
180 r = cmi_rd(sc, reg, 4);
181 r &= ~(mask << shift);
183 cmi_wr(sc, reg, r, 4);
187 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask)
191 r = cmi_rd(sc, reg, 4);
193 cmi_wr(sc, reg, r, 4);
197 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask)
201 r = cmi_rd(sc, reg, 4);
203 cmi_wr(sc, reg, r, 4);
206 /* ------------------------------------------------------------------------- */
209 static int cmi_rates[] = {5512, 8000, 11025, 16000,
210 22050, 32000, 44100, 48000};
211 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0]))
213 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1
214 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */
217 cmpci_rate_to_regvalue(int rate)
221 for(i = 0; i < NUM_CMI_RATES - 1; i++) {
222 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) {
227 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i]));
229 r = ((i >> 1) | (i << 2)) & 0x07;
234 cmpci_regvalue_to_rate(u_int32_t r)
238 i = ((r << 1) | (r >> 2)) & 0x07;
239 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i));
243 /* ------------------------------------------------------------------------- */
244 /* ADC/DAC control - there are 2 dma channels on 8738, either can be
245 * playback or capture. We use ch0 for playback and ch1 for capture. */
248 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base)
252 ch->phys_buf = sndbuf_getbufaddr(ch->buffer);
254 cmi_wr(sc, base, ch->phys_buf, 4);
255 sz = (u_int32_t)sndbuf_getsize(ch->buffer);
257 s = sz / ch->bps - 1;
258 cmi_wr(sc, base + 4, s, 2);
260 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1;
261 cmi_wr(sc, base + 6, i, 2);
266 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch)
268 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
270 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
271 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
272 CMPCI_REG_CH0_INTR_ENABLE);
278 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch)
280 u_int32_t r = ch->dma_active;
282 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
283 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
284 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
285 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
291 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch)
293 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
294 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
295 /* Enable Interrupts */
296 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
297 CMPCI_REG_CH1_INTR_ENABLE);
298 DEB(printf("cmi_ch1_start: dma prog\n"));
303 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch)
305 u_int32_t r = ch->dma_active;
307 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
308 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
309 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
310 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
316 cmi_spdif_speed(struct sc_info *sc, int speed) {
317 u_int32_t fcr1, lcr, mcr;
319 if (speed >= 44100) {
320 fcr1 = CMPCI_REG_SPDIF0_ENABLE;
321 lcr = CMPCI_REG_XSPDIF_ENABLE;
322 mcr = (speed == 48000) ?
323 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0;
325 fcr1 = mcr = lcr = 0;
328 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0,
329 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr);
330 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0,
331 CMPCI_REG_SPDIF0_ENABLE, fcr1);
332 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0,
333 CMPCI_REG_XSPDIF_ENABLE, lcr);
336 /* ------------------------------------------------------------------------- */
337 /* Channel Interface implementation */
340 cmichan_init(kobj_t obj, void *devinfo,
341 struct snd_dbuf *b, struct pcm_channel *c, int dir)
343 struct sc_info *sc = devinfo;
344 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
350 ch->spd = DSP_DEFAULT_SPEED;
353 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
354 DEB(printf("cmichan_init failed\n"));
359 snd_mtxlock(sc->lock);
360 if (ch->dir == PCMDIR_PLAY) {
361 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
363 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
365 snd_mtxunlock(sc->lock);
371 cmichan_setformat(kobj_t obj, void *data, u_int32_t format)
373 struct sc_chinfo *ch = data;
374 struct sc_info *sc = ch->parent;
377 if (format & AFMT_S16_LE) {
378 f = CMPCI_REG_FORMAT_16BIT;
381 f = CMPCI_REG_FORMAT_8BIT;
385 if (format & AFMT_STEREO) {
386 f |= CMPCI_REG_FORMAT_STEREO;
389 f |= CMPCI_REG_FORMAT_MONO;
392 snd_mtxlock(sc->lock);
393 if (ch->dir == PCMDIR_PLAY) {
394 cmi_partial_wr4(ch->parent,
395 CMPCI_REG_CHANNEL_FORMAT,
396 CMPCI_REG_CH0_FORMAT_SHIFT,
397 CMPCI_REG_CH0_FORMAT_MASK,
400 cmi_partial_wr4(ch->parent,
401 CMPCI_REG_CHANNEL_FORMAT,
402 CMPCI_REG_CH1_FORMAT_SHIFT,
403 CMPCI_REG_CH1_FORMAT_MASK,
406 snd_mtxunlock(sc->lock);
413 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed)
415 struct sc_chinfo *ch = data;
416 struct sc_info *sc = ch->parent;
419 r = cmpci_rate_to_regvalue(speed);
420 snd_mtxlock(sc->lock);
421 if (ch->dir == PCMDIR_PLAY) {
423 /* disable if req before rate change */
424 cmi_spdif_speed(ch->parent, speed);
426 cmi_partial_wr4(ch->parent,
428 CMPCI_REG_DAC_FS_SHIFT,
429 CMPCI_REG_DAC_FS_MASK,
431 if (speed >= 44100 && ch->parent->spdif_enabled) {
432 /* enable if req after rate change */
433 cmi_spdif_speed(ch->parent, speed);
435 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
436 rsp >>= CMPCI_REG_DAC_FS_SHIFT;
437 rsp &= CMPCI_REG_DAC_FS_MASK;
439 cmi_partial_wr4(ch->parent,
441 CMPCI_REG_ADC_FS_SHIFT,
442 CMPCI_REG_ADC_FS_MASK,
444 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
445 rsp >>= CMPCI_REG_ADC_FS_SHIFT;
446 rsp &= CMPCI_REG_ADC_FS_MASK;
448 snd_mtxunlock(sc->lock);
449 ch->spd = cmpci_regvalue_to_rate(r);
451 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n",
452 (ch->dir == PCMDIR_PLAY) ? "play" : "rec",
453 speed, ch->spd, cmpci_regvalue_to_rate(rsp)));
459 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
461 struct sc_chinfo *ch = data;
462 struct sc_info *sc = ch->parent;
464 /* user has requested interrupts every blocksize bytes */
465 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) {
466 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER;
468 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize);
474 cmichan_trigger(kobj_t obj, void *data, int go)
476 struct sc_chinfo *ch = data;
477 struct sc_info *sc = ch->parent;
479 if (!PCMTRIG_COMMON(go))
482 snd_mtxlock(sc->lock);
483 if (ch->dir == PCMDIR_PLAY) {
486 cmi_ch0_start(sc, ch);
490 cmi_ch0_stop(sc, ch);
496 cmi_ch1_start(sc, ch);
500 cmi_ch1_stop(sc, ch);
504 snd_mtxunlock(sc->lock);
509 cmichan_getptr(kobj_t obj, void *data)
511 struct sc_chinfo *ch = data;
512 struct sc_info *sc = ch->parent;
513 u_int32_t physptr, bufptr, sz;
515 snd_mtxlock(sc->lock);
516 if (ch->dir == PCMDIR_PLAY) {
517 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4);
519 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4);
521 snd_mtxunlock(sc->lock);
523 sz = sndbuf_getsize(ch->buffer);
524 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz;
532 struct sc_info *sc = data;
536 snd_mtxlock(sc->lock);
537 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4);
538 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) {
541 if (intrstat & CMPCI_REG_CH0_INTR) {
542 toclear |= CMPCI_REG_CH0_INTR_ENABLE;
543 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
546 if (intrstat & CMPCI_REG_CH1_INTR) {
547 toclear |= CMPCI_REG_CH1_INTR_ENABLE;
548 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
552 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear);
553 snd_mtxunlock(sc->lock);
555 /* Signal interrupts to channel */
556 if (intrstat & CMPCI_REG_CH0_INTR) {
557 chn_intr(sc->pch.channel);
560 if (intrstat & CMPCI_REG_CH1_INTR) {
561 chn_intr(sc->rch.channel);
564 snd_mtxlock(sc->lock);
565 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear);
570 (sc->mpu_intr)(sc->mpu);
572 snd_mtxunlock(sc->lock);
576 static struct pcmchan_caps *
577 cmichan_getcaps(kobj_t obj, void *data)
582 static kobj_method_t cmichan_methods[] = {
583 KOBJMETHOD(channel_init, cmichan_init),
584 KOBJMETHOD(channel_setformat, cmichan_setformat),
585 KOBJMETHOD(channel_setspeed, cmichan_setspeed),
586 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize),
587 KOBJMETHOD(channel_trigger, cmichan_trigger),
588 KOBJMETHOD(channel_getptr, cmichan_getptr),
589 KOBJMETHOD(channel_getcaps, cmichan_getcaps),
592 CHANNEL_DECLARE(cmichan);
594 /* ------------------------------------------------------------------------- */
595 /* Mixer - sb16 with kinks */
598 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val)
600 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
601 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1);
605 cmimix_rd(struct sc_info *sc, u_int8_t port)
607 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
608 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1);
612 u_int8_t rreg; /* right reg chan register */
613 u_int8_t stereo:1; /* (no explanation needed, honest) */
614 u_int8_t rec:1; /* recording source */
615 u_int8_t bits:3; /* num bits to represent maximum gain rep */
616 u_int8_t oselect; /* output select mask */
617 u_int8_t iselect; /* right input select mask */
618 } static const cmt[SOUND_MIXER_NRDEVICES] = {
619 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5,
620 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R},
621 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5,
622 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R},
623 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5,
624 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R},
625 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5,
626 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC},
627 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0},
628 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0},
629 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0},
630 /* These controls are not implemented in CMI8738, but maybe at a
631 future date. They are not documented in C-Media documentation,
632 though appear in other drivers for future h/w (ALSA, Linux, NetBSD).
634 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0},
635 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0},
636 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0},
637 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0},
638 /* The mic pre-amp is implemented with non-SB16 compatible
640 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0},
643 #define MIXER_GAIN_REG_RTOL(r) (r - 1)
646 cmimix_init(struct snd_mixer *m)
648 struct sc_info *sc = mix_getdevinfo(m);
651 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
652 if (cmt[i].bits) v |= 1 << i;
656 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
657 if (cmt[i].rec) v |= 1 << i;
659 mix_setrecdevs(m, v);
661 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0);
662 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
663 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
664 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX,
665 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
670 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
672 struct sc_info *sc = mix_getdevinfo(m);
676 max = (1 << cmt[dev].bits) - 1;
678 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) {
679 /* For time being this can only be one thing (mic in
681 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0;
682 l = left * max / 100;
683 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */
684 v |= ((l << 1) | (~l >> 3)) & 0x0f;
685 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1);
689 l = (left * max / 100) << (8 - cmt[dev].bits);
690 if (cmt[dev].stereo) {
691 r = (right * max / 100) << (8 - cmt[dev].bits);
692 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l);
693 cmimix_wr(sc, cmt[dev].rreg, r);
694 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\
695 "value 0x%02x:0x%02x\n",
696 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r));
699 cmimix_wr(sc, cmt[dev].rreg, l);
700 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \
701 "value 0x%02x:0x%02x\n",
702 dev, cmt[dev].rreg, l, l));
705 /* Zero gain does not mute channel from output, but this does... */
706 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX);
707 if (l == 0 && r == 0) {
708 v &= ~cmt[dev].oselect;
710 v |= cmt[dev].oselect;
712 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v);
718 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src)
720 struct sc_info *sc = mix_getdevinfo(m);
724 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
727 sl |= cmt[i].iselect;
729 ml |= cmt[i].iselect;
733 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml);
734 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
735 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml));
736 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml);
737 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml);
738 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
739 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml));
744 /* Optional SPDIF support. */
747 cmi_initsys(struct sc_info* sc)
750 /* XXX: an user should be able to set this with a control tool,
751 if not done before 7.0-RELEASE, this needs to be converted
752 to a device specific sysctl "dev.pcm.X.yyy" via
753 device_get_sysctl_*() as discussed on multimedia@ in msg-id
754 <861wujij2q.fsf@xps.des.no> */
755 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev),
756 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
757 OID_AUTO, "spdif_enabled", CTLFLAG_RW,
758 &sc->spdif_enabled, 0,
759 "enable SPDIF output at 44.1 kHz and above");
760 #endif /* SND_DYNSYSCTL */
764 /* ------------------------------------------------------------------------- */
765 static kobj_method_t cmi_mixer_methods[] = {
766 KOBJMETHOD(mixer_init, cmimix_init),
767 KOBJMETHOD(mixer_set, cmimix_set),
768 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc),
771 MIXER_DECLARE(cmi_mixer);
778 cmi_mread(void *arg, struct sc_info *sc, int reg)
782 d = bus_space_read_1(0,0, 0x330 + reg);
783 /* printf("cmi_mread: reg %x %x\n",reg, d);
789 cmi_mwrite(void *arg, struct sc_info *sc, int reg, unsigned char b)
792 bus_space_write_1(0,0,0x330 + reg , b);
796 cmi_muninit(void *arg, struct sc_info *sc)
799 snd_mtxlock(sc->lock);
802 snd_mtxunlock(sc->lock);
807 static kobj_method_t cmi_mpu_methods[] = {
808 KOBJMETHOD(mpufoi_read, cmi_mread),
809 KOBJMETHOD(mpufoi_write, cmi_mwrite),
810 KOBJMETHOD(mpufoi_uninit, cmi_muninit),
814 static DEFINE_CLASS(cmi_mpu, cmi_mpu_methods, 0);
817 cmi_midiattach(struct sc_info *sc) {
827 Notes, CMPCI_REG_VMPUSEL sets the io port for the mpu. Does
828 anyone know how to bus_space tag?
830 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
831 cmi_clr4(sc, CMPCI_REG_LEGACY_CTRL,
832 CMPCI_REG_VMPUSEL_MASK << CMPCI_REG_VMPUSEL_SHIFT);
833 cmi_set4(sc, CMPCI_REG_LEGACY_CTRL,
834 0 << CMPCI_REG_VMPUSEL_SHIFT );
835 cmi_set4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
836 sc->mpu = mpu401_init(&cmi_mpu_class, sc, cmi_intr, &sc->mpu_intr);
841 /* ------------------------------------------------------------------------- */
842 /* Power and reset */
845 cmi_power(struct sc_info *sc, int state)
848 case 0: /* full power */
849 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
853 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
859 cmi_init(struct sc_info *sc)
862 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
864 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
866 /* Disable interrupts and channels */
867 cmi_clr4(sc, CMPCI_REG_FUNC_0,
868 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
869 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
870 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE);
872 /* Configure DMA channels, ch0 = play, ch1 = capture */
873 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR);
874 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR);
876 /* Attempt to enable 4 Channel output */
877 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D);
879 /* Disable SPDIF1 - not compatible with config */
880 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE);
881 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
887 cmi_uninit(struct sc_info *sc)
889 /* Disable interrupts and channels */
890 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
891 CMPCI_REG_CH0_INTR_ENABLE |
892 CMPCI_REG_CH1_INTR_ENABLE |
893 CMPCI_REG_TDMA_INTR_ENABLE);
894 cmi_clr4(sc, CMPCI_REG_FUNC_0,
895 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
896 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
902 /* ------------------------------------------------------------------------- */
903 /* Bus and device registration */
905 cmi_probe(device_t dev)
907 switch(pci_get_devid(dev)) {
908 case CMI8338A_PCI_ID:
909 device_set_desc(dev, "CMedia CMI8338A");
910 return BUS_PROBE_DEFAULT;
911 case CMI8338B_PCI_ID:
912 device_set_desc(dev, "CMedia CMI8338B");
913 return BUS_PROBE_DEFAULT;
915 device_set_desc(dev, "CMedia CMI8738");
916 return BUS_PROBE_DEFAULT;
917 case CMI8738B_PCI_ID:
918 device_set_desc(dev, "CMedia CMI8738B");
919 return BUS_PROBE_DEFAULT;
921 device_set_desc(dev, "CMedia CMI120");
922 return BUS_PROBE_DEFAULT;
929 cmi_attach(device_t dev)
933 char status[SND_STATUSLEN];
935 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
936 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_cmi softc");
937 data = pci_read_config(dev, PCIR_COMMAND, 2);
938 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN);
939 pci_write_config(dev, PCIR_COMMAND, data, 2);
940 data = pci_read_config(dev, PCIR_COMMAND, 2);
943 sc->regid = PCIR_BAR(0);
944 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid,
947 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n");
950 sc->st = rman_get_bustag(sc->reg);
951 sc->sh = rman_get_bushandle(sc->reg);
957 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
958 RF_ACTIVE | RF_SHAREABLE);
960 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) {
961 device_printf(dev, "cmi_attach: Unable to map interrupt\n");
965 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536);
967 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
969 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
970 /*highaddr*/BUS_SPACE_MAXADDR,
971 /*filter*/NULL, /*filterarg*/NULL,
972 /*maxsize*/sc->bufsz, /*nsegments*/1,
973 /*maxsegz*/0x3ffff, /*flags*/0,
976 &sc->parent_dmat) != 0) {
977 device_printf(dev, "cmi_attach: Unable to create dma tag\n");
985 if (mixer_init(dev, &cmi_mixer_class, sc))
988 if (pcm_register(dev, sc, 1, 1))
993 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc);
994 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc);
996 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s",
997 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi));
998 pcm_setstatus(dev, status);
1000 DEB(printf("cmi_attach: succeeded\n"));
1004 if (sc->parent_dmat)
1005 bus_dma_tag_destroy(sc->parent_dmat);
1007 bus_teardown_intr(dev, sc->irq, sc->ih);
1009 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1011 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
1013 snd_mtxfree(sc->lock);
1021 cmi_detach(device_t dev)
1026 r = pcm_unregister(dev);
1029 sc = pcm_getdevinfo(dev);
1033 bus_dma_tag_destroy(sc->parent_dmat);
1034 bus_teardown_intr(dev, sc->irq, sc->ih);
1035 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1037 mpu401_uninit(sc->mpu);
1038 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
1040 bus_release_resource(dev, SYS_RES_IOPORT, sc->mpu_regid, sc->mpu_reg);
1042 snd_mtxfree(sc->lock);
1049 cmi_suspend(device_t dev)
1051 struct sc_info *sc = pcm_getdevinfo(dev);
1053 snd_mtxlock(sc->lock);
1054 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch);
1055 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch);
1057 snd_mtxunlock(sc->lock);
1062 cmi_resume(device_t dev)
1064 struct sc_info *sc = pcm_getdevinfo(dev);
1066 snd_mtxlock(sc->lock);
1068 if (cmi_init(sc) != 0) {
1069 device_printf(dev, "unable to reinitialize the card\n");
1070 snd_mtxunlock(sc->lock);
1074 if (mixer_reinit(dev) == -1) {
1075 device_printf(dev, "unable to reinitialize the mixer\n");
1076 snd_mtxunlock(sc->lock);
1080 if (sc->pch.dma_was_active) {
1081 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd);
1082 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt);
1083 cmi_ch0_start(sc, &sc->pch);
1086 if (sc->rch.dma_was_active) {
1087 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd);
1088 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt);
1089 cmi_ch1_start(sc, &sc->rch);
1091 snd_mtxunlock(sc->lock);
1095 static device_method_t cmi_methods[] = {
1096 DEVMETHOD(device_probe, cmi_probe),
1097 DEVMETHOD(device_attach, cmi_attach),
1098 DEVMETHOD(device_detach, cmi_detach),
1099 DEVMETHOD(device_resume, cmi_resume),
1100 DEVMETHOD(device_suspend, cmi_suspend),
1104 static driver_t cmi_driver = {
1110 DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, 0, 0);
1111 MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1112 MODULE_DEPEND(snd_cmi, midi, 1,1,1);
1113 MODULE_VERSION(snd_cmi, 1);