2 * Copyright (c) 2000 Cameron Grant <cg@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
27 #include <dev/sound/pcm/sound.h>
28 #include <dev/sound/pcm/ac97.h>
30 #include <dev/pci/pcireg.h>
31 #include <dev/pci/pcivar.h>
33 #include <dev/sound/pci/ds1.h>
34 #include <dev/sound/pci/ds1-fw.h>
36 SND_DECLARE_FILE("$FreeBSD$");
38 /* -------------------------------------------------------------------- */
41 #define DS1_RECPRIMARY 0
42 #define DS1_IRQHZ ((48000 << 8) / 256)
43 #define DS1_BUFFSIZE 4096
46 volatile u_int32_t Format;
47 volatile u_int32_t LoopDefault;
48 volatile u_int32_t PgBase;
49 volatile u_int32_t PgLoop;
50 volatile u_int32_t PgLoopEnd;
51 volatile u_int32_t PgLoopFrac;
52 volatile u_int32_t PgDeltaEnd;
53 volatile u_int32_t LpfKEnd;
54 volatile u_int32_t EgGainEnd;
55 volatile u_int32_t LchGainEnd;
56 volatile u_int32_t RchGainEnd;
57 volatile u_int32_t Effect1GainEnd;
58 volatile u_int32_t Effect2GainEnd;
59 volatile u_int32_t Effect3GainEnd;
60 volatile u_int32_t LpfQ;
61 volatile u_int32_t Status;
62 volatile u_int32_t NumOfFrames;
63 volatile u_int32_t LoopCount;
64 volatile u_int32_t PgStart;
65 volatile u_int32_t PgStartFrac;
66 volatile u_int32_t PgDelta;
67 volatile u_int32_t LpfK;
68 volatile u_int32_t EgGain;
69 volatile u_int32_t LchGain;
70 volatile u_int32_t RchGain;
71 volatile u_int32_t Effect1Gain;
72 volatile u_int32_t Effect2Gain;
73 volatile u_int32_t Effect3Gain;
74 volatile u_int32_t LpfD1;
75 volatile u_int32_t LpfD2;
79 volatile u_int32_t PgBase;
80 volatile u_int32_t PgLoopEnd;
81 volatile u_int32_t PgStart;
82 volatile u_int32_t NumOfLoops;
87 /* channel registers */
89 int run, spd, dir, fmt;
90 struct snd_dbuf *buffer;
91 struct pcm_channel *channel;
92 volatile struct pbank *lslot, *rslot;
94 struct sc_info *parent;
98 int run, spd, dir, fmt, num;
99 struct snd_dbuf *buffer;
100 struct pcm_channel *channel;
101 volatile struct rbank *slot;
102 struct sc_info *parent;
105 /* device private data */
109 u_int32_t cd2id, ctrlbase;
112 bus_space_handle_t sh;
113 bus_dma_tag_t buffer_dmat, control_dmat;
116 struct resource *reg, *irq;
122 u_int32_t *pbase, pbankbase, pbanksize;
123 volatile struct pbank *pbank[2 * 64];
124 volatile struct rbank *rbank;
125 int pslotfree, currbank, pchn, rchn;
128 struct sc_pchinfo pch[DS1_CHANS];
129 struct sc_rchinfo rch[2];
133 u_int32_t dev, subdev;
137 {0x00041073, 0, "Yamaha DS-1 (YMF724)", CntrlInst},
138 {0x000d1073, 0, "Yamaha DS-1E (YMF724F)", CntrlInst1E},
139 {0x00051073, 0, "Yamaha DS-1? (YMF734)", CntrlInst},
140 {0x00081073, 0, "Yamaha DS-1? (YMF737)", CntrlInst},
141 {0x00201073, 0, "Yamaha DS-1? (YMF738)", CntrlInst},
142 {0x00061073, 0, "Yamaha DS-1? (YMF738_TEG)", CntrlInst},
143 {0x000a1073, 0x00041073, "Yamaha DS-1 (YMF740)", CntrlInst},
144 {0x000a1073, 0x000a1073, "Yamaha DS-1 (YMF740B)", CntrlInst},
145 {0x000a1073, 0x53328086, "Yamaha DS-1 (YMF740I)", CntrlInst},
146 {0x000a1073, 0, "Yamaha DS-1 (YMF740?)", CntrlInst},
147 {0x000c1073, 0, "Yamaha DS-1E (YMF740C)", CntrlInst1E},
148 {0x00101073, 0, "Yamaha DS-1E (YMF744)", CntrlInst1E},
149 {0x00121073, 0, "Yamaha DS-1E (YMF754)", CntrlInst1E},
153 /* -------------------------------------------------------------------- */
160 static int ds_init(struct sc_info *);
161 static void ds_intr(void *);
163 /* talk to the card */
164 static u_int32_t ds_rd(struct sc_info *, int, int);
165 static void ds_wr(struct sc_info *, int, u_int32_t, int);
167 /* -------------------------------------------------------------------- */
169 static u_int32_t ds_recfmt[] = {
171 AFMT_STEREO | AFMT_U8,
173 AFMT_STEREO | AFMT_S8,
175 AFMT_STEREO | AFMT_S16_LE,
177 AFMT_STEREO | AFMT_U16_LE,
180 static struct pcmchan_caps ds_reccaps = {4000, 48000, ds_recfmt, 0};
182 static u_int32_t ds_playfmt[] = {
184 AFMT_STEREO | AFMT_U8,
186 AFMT_STEREO | AFMT_S16_LE,
189 static struct pcmchan_caps ds_playcaps = {4000, 96000, ds_playfmt, 0};
191 /* -------------------------------------------------------------------- */
194 ds_rd(struct sc_info *sc, int regno, int size)
198 return bus_space_read_1(sc->st, sc->sh, regno);
200 return bus_space_read_2(sc->st, sc->sh, regno);
202 return bus_space_read_4(sc->st, sc->sh, regno);
209 ds_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
213 bus_space_write_1(sc->st, sc->sh, regno, data);
216 bus_space_write_2(sc->st, sc->sh, regno, data);
219 bus_space_write_4(sc->st, sc->sh, regno, data);
225 wrl(struct sc_info *sc, u_int32_t *ptr, u_int32_t val)
227 *(volatile u_int32_t *)ptr = val;
228 bus_space_barrier(sc->st, sc->sh, 0, 0, BUS_SPACE_BARRIER_WRITE);
231 /* -------------------------------------------------------------------- */
234 ds_cdbusy(struct sc_info *sc, int sec)
238 reg = sec? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
239 i = YDSXG_AC97TIMEOUT;
241 if (!(ds_rd(sc, reg, 2) & 0x8000))
249 ds_initcd(kobj_t obj, void *devinfo)
251 struct sc_info *sc = (struct sc_info *)devinfo;
254 x = pci_read_config(sc->dev, PCIR_DSXGCTRL, 1);
256 pci_write_config(sc->dev, PCIR_DSXGCTRL, x & ~0x03, 1);
257 pci_write_config(sc->dev, PCIR_DSXGCTRL, x | 0x03, 1);
258 pci_write_config(sc->dev, PCIR_DSXGCTRL, x & ~0x03, 1);
260 * The YMF740 on some Intel motherboards requires a pretty
261 * hefty delay after this reset for some reason... Otherwise:
262 * "pcm0: ac97 codec init failed"
263 * Maybe this is needed for all YMF740's?
264 * 400ms and 500ms here seem to work, 300ms does not.
266 * do it for all chips -cg
271 return ds_cdbusy(sc, 0)? 0 : 1;
275 ds_rdcd(kobj_t obj, void *devinfo, int regno)
277 struct sc_info *sc = (struct sc_info *)devinfo;
283 cid = sec? (sc->cd2id << 8) : 0;
284 reg = sec? YDSXGR_SECSTATUSDATA : YDSXGR_PRISTATUSDATA;
288 cmd = YDSXG_AC97READCMD | cid | regno;
289 ds_wr(sc, YDSXGR_AC97CMDADR, cmd, 2);
291 if (ds_cdbusy(sc, sec))
294 if (sc->type == 11 && sc->rev < 2)
295 for (i = 0; i < 600; i++)
298 return ds_rd(sc, reg, 2);
302 ds_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
304 struct sc_info *sc = (struct sc_info *)devinfo;
310 cid = sec? (sc->cd2id << 8) : 0;
314 cmd = YDSXG_AC97WRITECMD | cid | regno;
317 ds_wr(sc, YDSXGR_AC97CMDDATA, cmd, 4);
319 return ds_cdbusy(sc, sec);
322 static kobj_method_t ds_ac97_methods[] = {
323 KOBJMETHOD(ac97_init, ds_initcd),
324 KOBJMETHOD(ac97_read, ds_rdcd),
325 KOBJMETHOD(ac97_write, ds_wrcd),
328 AC97_DECLARE(ds_ac97);
330 /* -------------------------------------------------------------------- */
333 ds_enadsp(struct sc_info *sc, int on)
339 ds_wr(sc, YDSXGR_CONFIG, 0x00000001, 4);
341 if (ds_rd(sc, YDSXGR_CONFIG, 4))
342 ds_wr(sc, YDSXGR_CONFIG, 0x00000000, 4);
343 i = YDSXG_WORKBITTIMEOUT;
345 if (!(ds_rd(sc, YDSXGR_CONFIG, 4) & 0x00000002))
352 static volatile struct pbank *
353 ds_allocpslot(struct sc_info *sc)
357 if (sc->pslotfree > 63)
359 slot = sc->pslotfree++;
360 return sc->pbank[slot * 2];
364 ds_initpbank(volatile struct pbank *pb, int ch, int b16, int stereo, u_int32_t rate, bus_addr_t base, u_int32_t len)
366 u_int32_t lv[] = {1, 1, 0, 0, 0};
367 u_int32_t rv[] = {1, 0, 1, 0, 0};
368 u_int32_t e1[] = {0, 0, 0, 0, 0};
369 u_int32_t e2[] = {1, 0, 0, 1, 0};
370 u_int32_t e3[] = {1, 0, 0, 0, 1};
377 { 100, 0x00570000, 0x35280000},
378 { 2000, 0x06aa0000, 0x34a70000},
379 { 8000, 0x18b20000, 0x32020000},
380 {11025, 0x20930000, 0x31770000},
381 {16000, 0x2b9a0000, 0x31390000},
382 {22050, 0x35a10000, 0x31c90000},
383 {32000, 0x3eaa0000, 0x33d00000},
384 /* {44100, 0x04646000, 0x370a0000},
385 */ {48000, 0x40000000, 0x40000000},
390 delta = (65536 * rate) / 48000;
392 while (i < 7 && speedinfo[i].rate < rate)
395 pb->Format = stereo? 0x00010000 : 0;
396 pb->Format |= b16? 0 : 0x80000000;
397 pb->Format |= (stereo && (ch == 2 || ch == 4))? 0x00000001 : 0;
401 pb->PgLoopEnd = len >> ss;
408 pb->PgDelta = pb->PgDeltaEnd = delta << 12;
409 pb->LpfQ = speedinfo[i].fQ;
410 pb->LpfK = pb->LpfKEnd = speedinfo[i].fK;
411 pb->LpfD1 = pb->LpfD2 = 0;
412 pb->EgGain = pb->EgGainEnd = 0x40000000;
413 pb->LchGain = pb->LchGainEnd = lv[ch] * 0x40000000;
414 pb->RchGain = pb->RchGainEnd = rv[ch] * 0x40000000;
415 pb->Effect1Gain = pb->Effect1GainEnd = e1[ch] * 0x40000000;
416 pb->Effect2Gain = pb->Effect2GainEnd = e2[ch] * 0x40000000;
417 pb->Effect3Gain = pb->Effect3GainEnd = e3[ch] * 0x40000000;
423 ds_enapslot(struct sc_info *sc, int slot, int go)
425 wrl(sc, &sc->pbase[slot + 1], go? (sc->pbankbase + 2 * slot * sc->pbanksize) : 0);
426 /* printf("pbase[%d] = 0x%x\n", slot + 1, go? (sc->pbankbase + 2 * slot * sc->pbanksize) : 0); */
430 ds_setuppch(struct sc_pchinfo *ch)
432 int stereo, b16, c, sz;
435 stereo = (ch->fmt & AFMT_STEREO)? 1 : 0;
436 b16 = (ch->fmt & AFMT_16BIT)? 1 : 0;
438 addr = sndbuf_getbufaddr(ch->buffer);
439 sz = sndbuf_getsize(ch->buffer);
441 ds_initpbank(ch->lslot, c, stereo, b16, ch->spd, addr, sz);
442 ds_initpbank(ch->lslot + 1, c, stereo, b16, ch->spd, addr, sz);
443 ds_initpbank(ch->rslot, 2, stereo, b16, ch->spd, addr, sz);
444 ds_initpbank(ch->rslot + 1, 2, stereo, b16, ch->spd, addr, sz);
448 ds_setuprch(struct sc_rchinfo *ch)
450 struct sc_info *sc = ch->parent;
451 int stereo, b16, i, sz, pri;
455 stereo = (ch->fmt & AFMT_STEREO)? 1 : 0;
456 b16 = (ch->fmt & AFMT_16BIT)? 1 : 0;
457 addr = sndbuf_getbufaddr(ch->buffer);
458 sz = sndbuf_getsize(ch->buffer);
459 pri = (ch->num == DS1_RECPRIMARY)? 1 : 0;
461 for (i = 0; i < 2; i++) {
462 ch->slot[i].PgBase = addr;
463 ch->slot[i].PgLoopEnd = sz;
464 ch->slot[i].PgStart = 0;
465 ch->slot[i].NumOfLoops = 0;
467 x = (b16? 0x00 : 0x01) | (stereo? 0x02 : 0x00);
468 y = (48000 * 4096) / ch->spd;
470 /* printf("pri = %d, x = %d, y = %d\n", pri, x, y); */
471 ds_wr(sc, pri? YDSXGR_ADCFORMAT : YDSXGR_RECFORMAT, x, 4);
472 ds_wr(sc, pri? YDSXGR_ADCSLOTSR : YDSXGR_RECSLOTSR, y, 4);
475 /* -------------------------------------------------------------------- */
476 /* play channel interface */
478 ds1pchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
480 struct sc_info *sc = devinfo;
481 struct sc_pchinfo *ch;
483 KASSERT(dir == PCMDIR_PLAY, ("ds1pchan_init: bad direction"));
485 ch = &sc->pch[sc->pchn++];
493 if (sndbuf_alloc(ch->buffer, sc->buffer_dmat, 0, sc->bufsz) != 0)
496 ch->lsnum = sc->pslotfree;
497 ch->lslot = ds_allocpslot(sc);
498 ch->rsnum = sc->pslotfree;
499 ch->rslot = ds_allocpslot(sc);
506 ds1pchan_setformat(kobj_t obj, void *data, u_int32_t format)
508 struct sc_pchinfo *ch = data;
516 ds1pchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
518 struct sc_pchinfo *ch = data;
526 ds1pchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
528 struct sc_pchinfo *ch = data;
529 struct sc_info *sc = ch->parent;
532 /* irq rate is fixed at 187.5hz */
533 drate = ch->spd * sndbuf_getbps(ch->buffer);
534 blocksize = roundup2((drate << 8) / DS1_IRQHZ, 4);
535 sndbuf_resize(ch->buffer, sc->bufsz / blocksize, blocksize);
540 /* semantic note: must start at beginning of buffer */
542 ds1pchan_trigger(kobj_t obj, void *data, int go)
544 struct sc_pchinfo *ch = data;
545 struct sc_info *sc = ch->parent;
548 if (!PCMTRIG_COMMON(go))
550 stereo = (ch->fmt & AFMT_STEREO)? 1 : 0;
551 if (go == PCMTRIG_START) {
554 ds_enapslot(sc, ch->lsnum, 1);
555 ds_enapslot(sc, ch->rsnum, stereo);
556 snd_mtxlock(sc->lock);
557 ds_wr(sc, YDSXGR_MODE, 0x00000003, 4);
558 snd_mtxunlock(sc->lock);
561 /* ds_setuppch(ch); */
562 ds_enapslot(sc, ch->lsnum, 0);
563 ds_enapslot(sc, ch->rsnum, 0);
570 ds1pchan_getptr(kobj_t obj, void *data)
572 struct sc_pchinfo *ch = data;
573 struct sc_info *sc = ch->parent;
574 volatile struct pbank *bank;
578 ss = (ch->fmt & AFMT_STEREO)? 1 : 0;
579 ss += (ch->fmt & AFMT_16BIT)? 1 : 0;
581 bank = ch->lslot + sc->currbank;
582 /* printf("getptr: %d\n", bank->PgStart << ss); */
588 static struct pcmchan_caps *
589 ds1pchan_getcaps(kobj_t obj, void *data)
594 static kobj_method_t ds1pchan_methods[] = {
595 KOBJMETHOD(channel_init, ds1pchan_init),
596 KOBJMETHOD(channel_setformat, ds1pchan_setformat),
597 KOBJMETHOD(channel_setspeed, ds1pchan_setspeed),
598 KOBJMETHOD(channel_setblocksize, ds1pchan_setblocksize),
599 KOBJMETHOD(channel_trigger, ds1pchan_trigger),
600 KOBJMETHOD(channel_getptr, ds1pchan_getptr),
601 KOBJMETHOD(channel_getcaps, ds1pchan_getcaps),
604 CHANNEL_DECLARE(ds1pchan);
606 /* -------------------------------------------------------------------- */
607 /* record channel interface */
609 ds1rchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
611 struct sc_info *sc = devinfo;
612 struct sc_rchinfo *ch;
614 KASSERT(dir == PCMDIR_REC, ("ds1rchan_init: bad direction"));
616 ch = &sc->rch[sc->rchn];
617 ch->num = sc->rchn++;
624 if (sndbuf_alloc(ch->buffer, sc->buffer_dmat, 0, sc->bufsz) != 0)
627 ch->slot = (ch->num == DS1_RECPRIMARY)? sc->rbank + 2: sc->rbank;
634 ds1rchan_setformat(kobj_t obj, void *data, u_int32_t format)
636 struct sc_rchinfo *ch = data;
644 ds1rchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
646 struct sc_rchinfo *ch = data;
654 ds1rchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
656 struct sc_rchinfo *ch = data;
657 struct sc_info *sc = ch->parent;
660 /* irq rate is fixed at 187.5hz */
661 drate = ch->spd * sndbuf_getbps(ch->buffer);
662 blocksize = roundup2((drate << 8) / DS1_IRQHZ, 4);
663 sndbuf_resize(ch->buffer, sc->bufsz / blocksize, blocksize);
668 /* semantic note: must start at beginning of buffer */
670 ds1rchan_trigger(kobj_t obj, void *data, int go)
672 struct sc_rchinfo *ch = data;
673 struct sc_info *sc = ch->parent;
676 if (!PCMTRIG_COMMON(go))
678 if (go == PCMTRIG_START) {
681 snd_mtxlock(sc->lock);
682 x = ds_rd(sc, YDSXGR_MAPOFREC, 4);
683 x |= (ch->num == DS1_RECPRIMARY)? 0x02 : 0x01;
684 ds_wr(sc, YDSXGR_MAPOFREC, x, 4);
685 ds_wr(sc, YDSXGR_MODE, 0x00000003, 4);
686 snd_mtxunlock(sc->lock);
689 snd_mtxlock(sc->lock);
690 x = ds_rd(sc, YDSXGR_MAPOFREC, 4);
691 x &= ~((ch->num == DS1_RECPRIMARY)? 0x02 : 0x01);
692 ds_wr(sc, YDSXGR_MAPOFREC, x, 4);
693 snd_mtxunlock(sc->lock);
700 ds1rchan_getptr(kobj_t obj, void *data)
702 struct sc_rchinfo *ch = data;
703 struct sc_info *sc = ch->parent;
705 return ch->slot[sc->currbank].PgStart;
708 static struct pcmchan_caps *
709 ds1rchan_getcaps(kobj_t obj, void *data)
714 static kobj_method_t ds1rchan_methods[] = {
715 KOBJMETHOD(channel_init, ds1rchan_init),
716 KOBJMETHOD(channel_setformat, ds1rchan_setformat),
717 KOBJMETHOD(channel_setspeed, ds1rchan_setspeed),
718 KOBJMETHOD(channel_setblocksize, ds1rchan_setblocksize),
719 KOBJMETHOD(channel_trigger, ds1rchan_trigger),
720 KOBJMETHOD(channel_getptr, ds1rchan_getptr),
721 KOBJMETHOD(channel_getcaps, ds1rchan_getcaps),
724 CHANNEL_DECLARE(ds1rchan);
726 /* -------------------------------------------------------------------- */
727 /* The interrupt handler */
731 struct sc_info *sc = (struct sc_info *)p;
734 snd_mtxlock(sc->lock);
735 i = ds_rd(sc, YDSXGR_STATUS, 4);
737 device_printf(sc->dev, "timeout irq\n");
738 if (i & 0x80008000) {
739 ds_wr(sc, YDSXGR_STATUS, i & 0x80008000, 4);
740 sc->currbank = ds_rd(sc, YDSXGR_CTRLSELECT, 4) & 0x00000001;
743 for (i = 0; i < DS1_CHANS; i++) {
744 if (sc->pch[i].run) {
746 snd_mtxunlock(sc->lock);
747 chn_intr(sc->pch[i].channel);
748 snd_mtxlock(sc->lock);
751 for (i = 0; i < 2; i++) {
752 if (sc->rch[i].run) {
754 snd_mtxunlock(sc->lock);
755 chn_intr(sc->rch[i].channel);
756 snd_mtxlock(sc->lock);
759 i = ds_rd(sc, YDSXGR_MODE, 4);
761 ds_wr(sc, YDSXGR_MODE, i | 0x00000002, 4);
764 snd_mtxunlock(sc->lock);
767 /* -------------------------------------------------------------------- */
770 * Probe and attach the card
774 ds_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
776 struct sc_info *sc = arg;
778 sc->ctrlbase = error? 0 : (u_int32_t)segs->ds_addr;
781 printf("ds1: setmap (%lx, %lx), nseg=%d, error=%d\n",
782 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
788 ds_init(struct sc_info *sc)
791 u_int32_t *ci, r, pcs, rcs, ecs, ws, memsz, cb;
795 ci = ds_devs[sc->type].mcode;
797 ds_wr(sc, YDSXGR_NATIVEDACOUTVOL, 0x00000000, 4);
799 ds_wr(sc, YDSXGR_MODE, 0x00010000, 4);
800 ds_wr(sc, YDSXGR_MODE, 0x00000000, 4);
801 ds_wr(sc, YDSXGR_MAPOFREC, 0x00000000, 4);
802 ds_wr(sc, YDSXGR_MAPOFEFFECT, 0x00000000, 4);
803 ds_wr(sc, YDSXGR_PLAYCTRLBASE, 0x00000000, 4);
804 ds_wr(sc, YDSXGR_RECCTRLBASE, 0x00000000, 4);
805 ds_wr(sc, YDSXGR_EFFCTRLBASE, 0x00000000, 4);
806 r = ds_rd(sc, YDSXGR_GLOBALCTRL, 2);
807 ds_wr(sc, YDSXGR_GLOBALCTRL, r & ~0x0007, 2);
809 for (i = 0; i < YDSXG_DSPLENGTH; i += 4)
810 ds_wr(sc, YDSXGR_DSPINSTRAM + i, DspInst[i >> 2], 4);
812 for (i = 0; i < YDSXG_CTRLLENGTH; i += 4)
813 ds_wr(sc, YDSXGR_CTRLINSTRAM + i, ci[i >> 2], 4);
818 for (i = 100; i > 0; i--) {
819 pcs = ds_rd(sc, YDSXGR_PLAYCTRLSIZE, 4) << 2;
820 if (pcs == sizeof(struct pbank))
824 if (pcs != sizeof(struct pbank)) {
825 device_printf(sc->dev, "preposterous playctrlsize (%d)\n", pcs);
828 rcs = ds_rd(sc, YDSXGR_RECCTRLSIZE, 4) << 2;
829 ecs = ds_rd(sc, YDSXGR_EFFCTRLSIZE, 4) << 2;
830 ws = ds_rd(sc, YDSXGR_WORKSIZE, 4) << 2;
832 memsz = 64 * 2 * pcs + 2 * 2 * rcs + 5 * 2 * ecs + ws;
833 memsz += (64 + 1) * 4;
835 if (sc->regbase == NULL) {
836 if (bus_dma_tag_create(bus_get_dma_tag(sc->dev), 2, 0,
837 BUS_SPACE_MAXADDR_32BIT,
839 NULL, NULL, memsz, 1, memsz, 0, NULL,
840 NULL, &sc->control_dmat))
842 if (bus_dmamem_alloc(sc->control_dmat, &buf, BUS_DMA_NOWAIT, &sc->map))
844 if (bus_dmamap_load(sc->control_dmat, sc->map, buf, memsz, ds_setmap, sc, 0) || !sc->ctrlbase) {
845 device_printf(sc->dev, "pcs=%d, rcs=%d, ecs=%d, ws=%d, memsz=%d\n",
846 pcs, rcs, ecs, ws, memsz);
855 ds_wr(sc, YDSXGR_WORKBASE, sc->ctrlbase + cb, 4);
857 sc->pbase = (u_int32_t *)(t + cb);
858 /* printf("pbase = %p -> 0x%x\n", sc->pbase, sc->ctrlbase + cb); */
859 ds_wr(sc, YDSXGR_PLAYCTRLBASE, sc->ctrlbase + cb, 4);
861 sc->rbank = (struct rbank *)(t + cb);
862 ds_wr(sc, YDSXGR_RECCTRLBASE, sc->ctrlbase + cb, 4);
864 ds_wr(sc, YDSXGR_EFFCTRLBASE, sc->ctrlbase + cb, 4);
867 sc->pbankbase = sc->ctrlbase + cb;
869 for (i = 0; i < 64; i++) {
870 wrl(sc, &sc->pbase[i + 1], 0);
871 sc->pbank[i * 2] = (struct pbank *)(t + cb);
872 /* printf("pbank[%d] = %p -> 0x%x; ", i * 2, (struct pbank *)(t + cb), sc->ctrlbase + cb - vtophys(t + cb)); */
874 sc->pbank[i * 2 + 1] = (struct pbank *)(t + cb);
875 /* printf("pbank[%d] = %p -> 0x%x\n", i * 2 + 1, (struct pbank *)(t + cb), sc->ctrlbase + cb - vtophys(t + cb)); */
878 wrl(sc, &sc->pbase[0], DS1_CHANS * 2);
880 sc->pchn = sc->rchn = 0;
881 ds_wr(sc, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff, 4);
882 ds_wr(sc, YDSXGR_NATIVEADCINVOL, 0x3fff3fff, 4);
883 ds_wr(sc, YDSXGR_NATIVEDACINVOL, 0x3fff3fff, 4);
889 ds_uninit(struct sc_info *sc)
891 ds_wr(sc, YDSXGR_NATIVEDACOUTVOL, 0x00000000, 4);
892 ds_wr(sc, YDSXGR_NATIVEADCINVOL, 0, 4);
893 ds_wr(sc, YDSXGR_NATIVEDACINVOL, 0, 4);
895 ds_wr(sc, YDSXGR_MODE, 0x00010000, 4);
896 ds_wr(sc, YDSXGR_MAPOFREC, 0x00000000, 4);
897 ds_wr(sc, YDSXGR_MAPOFEFFECT, 0x00000000, 4);
898 ds_wr(sc, YDSXGR_PLAYCTRLBASE, 0x00000000, 4);
899 ds_wr(sc, YDSXGR_RECCTRLBASE, 0x00000000, 4);
900 ds_wr(sc, YDSXGR_EFFCTRLBASE, 0x00000000, 4);
901 ds_wr(sc, YDSXGR_GLOBALCTRL, 0, 2);
903 bus_dmamap_unload(sc->control_dmat, sc->map);
904 bus_dmamem_free(sc->control_dmat, sc->regbase, sc->map);
910 ds_finddev(u_int32_t dev, u_int32_t subdev)
914 for (i = 0; ds_devs[i].dev; i++) {
915 if (ds_devs[i].dev == dev &&
916 (ds_devs[i].subdev == subdev || ds_devs[i].subdev == 0))
923 ds_pci_probe(device_t dev)
928 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev);
929 i = ds_finddev(pci_get_devid(dev), subdev);
931 device_set_desc(dev, ds_devs[i].name);
932 return BUS_PROBE_DEFAULT;
938 ds_pci_attach(device_t dev)
943 struct ac97_info *codec = NULL;
944 char status[SND_STATUSLEN];
946 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
947 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_ds1 softc");
949 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev);
950 sc->type = ds_finddev(pci_get_devid(dev), subdev);
951 sc->rev = pci_get_revid(dev);
953 data = pci_read_config(dev, PCIR_COMMAND, 2);
954 data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
955 pci_write_config(dev, PCIR_COMMAND, data, 2);
956 data = pci_read_config(dev, PCIR_COMMAND, 2);
958 sc->regid = PCIR_BAR(0);
959 sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->regid,
962 device_printf(dev, "unable to map register space\n");
966 sc->st = rman_get_bustag(sc->reg);
967 sc->sh = rman_get_bushandle(sc->reg);
969 sc->bufsz = pcm_getbuffersize(dev, 4096, DS1_BUFFSIZE, 65536);
971 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
973 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
974 /*highaddr*/BUS_SPACE_MAXADDR,
975 /*filter*/NULL, /*filterarg*/NULL,
976 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
977 /*flags*/0, /*lockfunc*/NULL,
978 /*lockarg*/NULL, &sc->buffer_dmat) != 0) {
979 device_printf(dev, "unable to create dma tag\n");
984 if (ds_init(sc) == -1) {
985 device_printf(dev, "unable to initialize the card\n");
989 codec = AC97_CREATE(dev, sc, ds_ac97);
993 * Turn on inverted external amplifier sense flags for few
997 case 0x81171033: /* NEC ValueStar (VT550/0) */
998 ac97_setflags(codec, ac97_getflags(codec) | AC97_F_EAPD_INV);
1003 mixer_init(dev, ac97_getmixerclass(), codec);
1006 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
1007 RF_ACTIVE | RF_SHAREABLE);
1008 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ds_intr, sc, &sc->ih)) {
1009 device_printf(dev, "unable to map interrupt\n");
1013 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s",
1014 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_ds1));
1016 if (pcm_register(dev, sc, DS1_CHANS, 2))
1018 for (i = 0; i < DS1_CHANS; i++)
1019 pcm_addchan(dev, PCMDIR_PLAY, &ds1pchan_class, sc);
1020 for (i = 0; i < 2; i++)
1021 pcm_addchan(dev, PCMDIR_REC, &ds1rchan_class, sc);
1022 pcm_setstatus(dev, status);
1028 ac97_destroy(codec);
1030 bus_release_resource(dev, SYS_RES_MEMORY, sc->regid, sc->reg);
1032 bus_teardown_intr(dev, sc->irq, sc->ih);
1034 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1035 if (sc->buffer_dmat)
1036 bus_dma_tag_destroy(sc->buffer_dmat);
1037 if (sc->control_dmat)
1038 bus_dma_tag_destroy(sc->control_dmat);
1040 snd_mtxfree(sc->lock);
1046 ds_pci_resume(device_t dev)
1050 sc = pcm_getdevinfo(dev);
1052 if (ds_init(sc) == -1) {
1053 device_printf(dev, "unable to reinitialize the card\n");
1056 if (mixer_reinit(dev) == -1) {
1057 device_printf(dev, "unable to reinitialize the mixer\n");
1064 ds_pci_detach(device_t dev)
1069 r = pcm_unregister(dev);
1073 sc = pcm_getdevinfo(dev);
1075 bus_release_resource(dev, SYS_RES_MEMORY, sc->regid, sc->reg);
1076 bus_teardown_intr(dev, sc->irq, sc->ih);
1077 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1078 bus_dma_tag_destroy(sc->buffer_dmat);
1079 bus_dma_tag_destroy(sc->control_dmat);
1080 snd_mtxfree(sc->lock);
1085 static device_method_t ds1_methods[] = {
1086 /* Device interface */
1087 DEVMETHOD(device_probe, ds_pci_probe),
1088 DEVMETHOD(device_attach, ds_pci_attach),
1089 DEVMETHOD(device_detach, ds_pci_detach),
1090 DEVMETHOD(device_resume, ds_pci_resume),
1094 static driver_t ds1_driver = {
1100 DRIVER_MODULE(snd_ds1, pci, ds1_driver, pcm_devclass, 0, 0);
1101 MODULE_DEPEND(snd_ds1, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1102 MODULE_VERSION(snd_ds1, 1);