2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp>
3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
28 #include <dev/sound/pcm/sound.h>
29 #include <dev/sound/pcm/ac97.h>
30 #include <dev/sound/pci/ich.h>
32 #include <dev/pci/pcireg.h>
33 #include <dev/pci/pcivar.h>
35 SND_DECLARE_FILE("$FreeBSD$");
37 /* -------------------------------------------------------------------- */
39 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */
40 #define ICH_DTBL_LENGTH 32
41 #define ICH_DEFAULT_BUFSZ 16384
42 #define ICH_MAX_BUFSZ 65536
43 #define ICH_MIN_BUFSZ 4096
44 #define ICH_DEFAULT_BLKCNT 2
45 #define ICH_MAX_BLKCNT 32
46 #define ICH_MIN_BLKCNT 2
47 #define ICH_MIN_BLKSZ 64
49 #define INTEL_VENDORID 0x8086
50 #define SIS_VENDORID 0x1039
51 #define NVIDIA_VENDORID 0x10de
52 #define AMD_VENDORID 0x1022
54 #define INTEL_82440MX 0x7195
55 #define INTEL_82801AA 0x2415
56 #define INTEL_82801AB 0x2425
57 #define INTEL_82801BA 0x2445
58 #define INTEL_82801CA 0x2485
59 #define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */
60 #define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */
61 #define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */
62 #define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */
63 #define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */
64 #define SIS_7012 0x7012 /* SiS 7012 needs special handling */
65 #define NVIDIA_NFORCE 0x01b1
66 #define NVIDIA_NFORCE2 0x006a
67 #define NVIDIA_NFORCE2_400 0x008a
68 #define NVIDIA_NFORCE3 0x00da
69 #define NVIDIA_NFORCE3_250 0x00ea
70 #define NVIDIA_NFORCE4 0x0059
71 #define NVIDIA_NFORCE_410_MCP 0x026b
72 #define NVIDIA_NFORCE4_MCP 0x003a
73 #define AMD_768 0x7445
74 #define AMD_8111 0x746d
76 #define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock)
77 #define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock)
78 #define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock)
81 #define ICH_DEBUG(stmt) do { \
85 #define ICH_DEBUG(...)
88 #define ICH_CALIBRATE_DONE (1 << 0)
89 #define ICH_IGNORE_PCR (1 << 1)
90 #define ICH_IGNORE_RESET (1 << 2)
91 #define ICH_FIXED_RATE (1 << 3)
92 #define ICH_DMA_NOCACHE (1 << 4)
93 #define ICH_HIGH_LATENCY (1 << 5)
95 static const struct ich_type {
99 #define PROBE_LOW 0x01
102 { INTEL_VENDORID, INTEL_82440MX, 0,
104 { INTEL_VENDORID, INTEL_82801AA, 0,
105 "Intel ICH (82801AA)" },
106 { INTEL_VENDORID, INTEL_82801AB, 0,
107 "Intel ICH (82801AB)" },
108 { INTEL_VENDORID, INTEL_82801BA, 0,
109 "Intel ICH2 (82801BA)" },
110 { INTEL_VENDORID, INTEL_82801CA, 0,
111 "Intel ICH3 (82801CA)" },
112 { INTEL_VENDORID, INTEL_82801DB, PROBE_LOW,
113 "Intel ICH4 (82801DB)" },
114 { INTEL_VENDORID, INTEL_82801EB, PROBE_LOW,
115 "Intel ICH5 (82801EB)" },
116 { INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW,
118 { INTEL_VENDORID, INTEL_82801FB, PROBE_LOW,
119 "Intel ICH6 (82801FB)" },
120 { INTEL_VENDORID, INTEL_82801GB, PROBE_LOW,
121 "Intel ICH7 (82801GB)" },
122 { SIS_VENDORID, SIS_7012, 0,
124 { NVIDIA_VENDORID, NVIDIA_NFORCE, 0,
126 { NVIDIA_VENDORID, NVIDIA_NFORCE2, 0,
128 { NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0,
129 "nVidia nForce2 400" },
130 { NVIDIA_VENDORID, NVIDIA_NFORCE3, 0,
132 { NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0,
133 "nVidia nForce3 250" },
134 { NVIDIA_VENDORID, NVIDIA_NFORCE4, 0,
136 { NVIDIA_VENDORID, NVIDIA_NFORCE_410_MCP, 0,
137 "nVidia nForce 410 MCP" },
138 { NVIDIA_VENDORID, NVIDIA_NFORCE4_MCP, 0,
139 "nVidia nForce 4 MCP" },
140 { AMD_VENDORID, AMD_768, 0,
142 { AMD_VENDORID, AMD_8111, 0,
146 /* buffer descriptor */
148 volatile uint32_t buffer;
149 volatile uint32_t length;
154 /* channel registers */
156 uint32_t num:8, run:1, run_save:1;
157 uint32_t blksz, blkcnt, spd;
158 uint32_t regbase, spdreg;
162 struct snd_dbuf *buffer;
163 struct pcm_channel *channel;
164 struct sc_info *parent;
166 struct ich_desc *dtbl;
167 bus_addr_t desc_addr;
170 /* device private data */
173 int hasvra, hasvrm, hasmic;
174 unsigned int chnum, bufsz, blkcnt;
175 int sample_size, swap_reg;
177 struct resource *nambar, *nabmbar, *irq;
178 int regtype, nambarid, nabmbarid, irqid;
179 bus_space_tag_t nambart, nabmbart;
180 bus_space_handle_t nambarh, nabmbarh;
181 bus_dma_tag_t dmat, chan_dmat;
185 struct ac97_info *codec;
186 struct sc_chinfo ch[3];
188 struct ich_desc *dtbl;
189 unsigned int dtbl_size;
190 bus_addr_t desc_addr;
191 struct intr_config_hook intrhook;
195 struct mtx *ich_lock;
198 /* -------------------------------------------------------------------- */
200 static uint32_t ich_fmt[] = {
201 AFMT_STEREO | AFMT_S16_LE,
204 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0};
205 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0};
207 /* -------------------------------------------------------------------- */
209 static __inline uint32_t
210 ich_rd(struct sc_info *sc, int regno, int size)
214 return (bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno));
216 return (bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno));
218 return (bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno));
225 ich_wr(struct sc_info *sc, int regno, uint32_t data, int size)
229 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data);
232 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data);
235 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data);
242 ich_waitcd(void *devinfo)
244 struct sc_info *sc = (struct sc_info *)devinfo;
248 for (i = 0; i < ICH_TIMEOUT; i++) {
249 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1);
250 if ((data & 0x01) == 0)
254 if ((sc->flags & ICH_IGNORE_PCR) != 0)
256 device_printf(sc->dev, "CODEC semaphore timeout\n");
261 ich_rdcd(kobj_t obj, void *devinfo, int regno)
263 struct sc_info *sc = (struct sc_info *)devinfo;
268 return (bus_space_read_2(sc->nambart, sc->nambarh, regno));
272 ich_wrcd(kobj_t obj, void *devinfo, int regno, uint16_t data)
274 struct sc_info *sc = (struct sc_info *)devinfo;
278 bus_space_write_2(sc->nambart, sc->nambarh, regno, data);
283 static kobj_method_t ich_ac97_methods[] = {
284 KOBJMETHOD(ac97_read, ich_rdcd),
285 KOBJMETHOD(ac97_write, ich_wrcd),
288 AC97_DECLARE(ich_ac97);
290 /* -------------------------------------------------------------------- */
291 /* common routines */
294 ich_filldtbl(struct sc_chinfo *ch)
296 struct sc_info *sc = ch->parent;
300 base = sndbuf_getbufaddr(ch->buffer);
301 if ((ch->blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->buffer))
302 ch->blksz = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt;
303 if ((sndbuf_getblksz(ch->buffer) != ch->blksz ||
304 sndbuf_getblkcnt(ch->buffer) != ch->blkcnt) &&
305 sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz) != 0)
306 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
307 __func__, ch->blksz, ch->blkcnt);
308 ch->blksz = sndbuf_getblksz(ch->buffer);
310 for (i = 0; i < ICH_DTBL_LENGTH; i++) {
311 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt));
312 ch->dtbl[i].length = ICH_BDC_IOC
313 | (ch->blksz / ch->parent->sample_size);
318 ich_resetchan(struct sc_info *sc, int num)
323 regbase = ICH_REG_PO_BASE;
325 regbase = ICH_REG_PI_BASE;
327 regbase = ICH_REG_MC_BASE;
331 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1);
333 /* This may result in no sound output on NForce 2 MBs, see PR 73987 */
336 (void)ich_rd(sc, regbase + ICH_REG_X_CR, 1);
338 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
339 for (i = 0; i < ICH_TIMEOUT; i++) {
340 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1);
346 if (sc->flags & ICH_IGNORE_RESET)
349 else if (sc->vendor == NVIDIA_VENDORID) {
350 sc->flags |= ICH_IGNORE_RESET;
351 device_printf(sc->dev, "ignoring reset failure!\n");
356 device_printf(sc->dev, "cannot reset channel %d\n", num);
360 /* -------------------------------------------------------------------- */
361 /* channel interface */
364 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
366 struct sc_info *sc = devinfo;
367 struct sc_chinfo *ch;
378 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH);
379 ch->desc_addr = sc->desc_addr +
380 (ch->num * ICH_DTBL_LENGTH * sizeof(struct ich_desc));
381 ch->blkcnt = sc->blkcnt;
382 ch->blksz = sc->bufsz / ch->blkcnt;
386 KASSERT(dir == PCMDIR_PLAY, ("wrong direction"));
387 ch->regbase = ICH_REG_PO_BASE;
388 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_FDACRATE : 0;
389 ch->imask = ICH_GLOB_STA_POINT;
393 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
394 ch->regbase = ICH_REG_PI_BASE;
395 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_LADCRATE : 0;
396 ch->imask = ICH_GLOB_STA_PIINT;
400 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
401 ch->regbase = ICH_REG_MC_BASE;
402 ch->spdreg = (sc->hasvrm) ? AC97_REGEXT_MADCRATE : 0;
403 ch->imask = ICH_GLOB_STA_MINT;
410 if (sc->flags & ICH_FIXED_RATE)
414 if (sndbuf_alloc(ch->buffer, sc->chan_dmat,
415 ((sc->flags & ICH_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
420 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4);
427 ichchan_setformat(kobj_t obj, void *data, uint32_t format)
431 struct sc_chinfo *ch = data;
432 struct sc_info *sc = ch->parent;
433 if (!(sc->flags & ICH_CALIBRATE_DONE))
434 device_printf(sc->dev,
435 "WARNING: %s() called before calibration!\n",
443 ichchan_setspeed(kobj_t obj, void *data, uint32_t speed)
445 struct sc_chinfo *ch = data;
446 struct sc_info *sc = ch->parent;
449 if (!(sc->flags & ICH_CALIBRATE_DONE))
450 device_printf(sc->dev,
451 "WARNING: %s() called before calibration!\n",
459 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000)
460 sc->ac97rate = 48000;
461 ac97rate = sc->ac97rate;
463 r = (speed * 48000) / ac97rate;
465 * Cast the return value of ac97_setrate() to uint64 so that
466 * the math don't overflow into the negative range.
468 ch->spd = ((uint64_t)ac97_setrate(sc->codec, ch->spdreg, r) *
477 ichchan_setblocksize(kobj_t obj, void *data, uint32_t blocksize)
479 struct sc_chinfo *ch = data;
480 struct sc_info *sc = ch->parent;
483 if (!(sc->flags & ICH_CALIBRATE_DONE))
484 device_printf(sc->dev,
485 "WARNING: %s() called before calibration!\n",
489 if (sc->flags & ICH_HIGH_LATENCY)
490 blocksize = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt;
492 if (blocksize < ICH_MIN_BLKSZ)
493 blocksize = ICH_MIN_BLKSZ;
494 blocksize &= ~(ICH_MIN_BLKSZ - 1);
495 ch->blksz = blocksize;
498 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1);
505 ichchan_trigger(kobj_t obj, void *data, int go)
507 struct sc_chinfo *ch = data;
508 struct sc_info *sc = ch->parent;
511 if (!(sc->flags & ICH_CALIBRATE_DONE))
512 device_printf(sc->dev,
513 "WARNING: %s() called before calibration!\n",
521 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4);
522 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1);
528 ich_resetchan(sc, ch->num);
539 ichchan_getptr(kobj_t obj, void *data)
541 struct sc_chinfo *ch = data;
542 struct sc_info *sc = ch->parent;
546 if (!(sc->flags & ICH_CALIBRATE_DONE))
547 device_printf(sc->dev,
548 "WARNING: %s() called before calibration!\n",
553 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt;
556 pos = ch->civ * ch->blksz;
561 static struct pcmchan_caps *
562 ichchan_getcaps(kobj_t obj, void *data)
564 struct sc_chinfo *ch = data;
567 struct sc_info *sc = ch->parent;
569 if (!(sc->flags & ICH_CALIBRATE_DONE))
570 device_printf(ch->parent->dev,
571 "WARNING: %s() called before calibration!\n",
575 return ((ch->spdreg) ? &ich_vrcaps : &ich_caps);
578 static kobj_method_t ichchan_methods[] = {
579 KOBJMETHOD(channel_init, ichchan_init),
580 KOBJMETHOD(channel_setformat, ichchan_setformat),
581 KOBJMETHOD(channel_setspeed, ichchan_setspeed),
582 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize),
583 KOBJMETHOD(channel_trigger, ichchan_trigger),
584 KOBJMETHOD(channel_getptr, ichchan_getptr),
585 KOBJMETHOD(channel_getcaps, ichchan_getcaps),
588 CHANNEL_DECLARE(ichchan);
590 /* -------------------------------------------------------------------- */
591 /* The interrupt handler */
596 struct sc_info *sc = (struct sc_info *)p;
597 struct sc_chinfo *ch;
598 uint32_t cbi, lbi, lvi, st, gs;
604 if (!(sc->flags & ICH_CALIBRATE_DONE))
605 device_printf(sc->dev,
606 "WARNING: %s() called before calibration!\n",
610 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK;
611 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) {
612 /* Clear resume interrupt(s) - nothing doing with them */
613 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4);
615 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES);
617 for (i = 0; i < 3; i++) {
619 if ((ch->imask & gs) == 0)
622 st = ich_rd(sc, ch->regbase +
623 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR),
625 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI;
626 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) {
627 /* block complete - update buffer */
630 chn_intr(ch->channel);
633 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1);
634 cbi = ch->civ % ch->blkcnt;
636 cbi = ch->blkcnt - 1;
639 lbi = lvi % ch->blkcnt;
643 lvi += cbi + ch->blkcnt - lbi;
644 lvi %= ICH_DTBL_LENGTH;
645 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1);
648 /* clear status bit */
649 ich_wr(sc, ch->regbase +
650 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR),
655 device_printf(sc->dev,
656 "Unhandled interrupt, gs_intr = %x\n", gs);
660 /* ------------------------------------------------------------------------- */
661 /* Sysctl to control ac97 speed (some boards appear to end up using
662 * XTAL_IN rather than BIT_CLK for link timing).
666 ich_initsys(struct sc_info* sc)
669 /* XXX: this should move to a device specific sysctl "dev.pcm.X.yyy"
670 via device_get_sysctl_*() as discussed on multimedia@ in msg-id
671 <861wujij2q.fsf@xps.des.no> */
672 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev),
673 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
674 OID_AUTO, "ac97rate", CTLFLAG_RW,
675 &sc->ac97rate, 48000,
676 "AC97 link rate (default = 48000)");
677 #endif /* SND_DYNSYSCTL */
682 ich_setstatus(struct sc_info *sc)
684 char status[SND_STATUSLEN];
686 snprintf(status, SND_STATUSLEN,
687 "at io 0x%lx, 0x%lx irq %ld bufsz %u %s",
688 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar),
689 rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich));
691 if (bootverbose && (sc->flags & ICH_DMA_NOCACHE))
692 device_printf(sc->dev,
693 "PCI Master abort workaround enabled\n");
695 pcm_setstatus(sc->dev, status);
698 /* -------------------------------------------------------------------- */
699 /* Calibrate card to determine the clock source. The source maybe a
700 * function of the ac97 codec initialization code (to be investigated).
704 ich_calibrate(void *arg)
707 struct sc_chinfo *ch;
708 struct timeval t1, t2;
710 uint32_t wait_us, actual_48k_rate, oblkcnt;
712 sc = (struct sc_info *)arg;
716 if (sc->intrhook.ich_func != NULL) {
717 config_intrhook_disestablish(&sc->intrhook);
718 sc->intrhook.ich_func = NULL;
722 * Grab audio from input for fixed interval and compare how
723 * much we actually get with what we expect. Interval needs
724 * to be sufficiently short that no interrupts are
728 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction"));
730 oblkcnt = ch->blkcnt;
732 sc->flags |= ICH_CALIBRATE_DONE;
734 ichchan_setblocksize(0, ch, sndbuf_getmaxsize(ch->buffer) >> 1);
736 sc->flags &= ~ICH_CALIBRATE_DONE;
739 * our data format is stereo, 16 bit so each sample is 4 bytes.
740 * assuming we get 48000 samples per second, we get 192000 bytes/sec.
741 * we're going to start recording with interrupts disabled and measure
742 * the time taken for one block to complete. we know the block size,
743 * we know the time in microseconds, we calculate the sample rate:
745 * actual_rate [bps] = bytes / (time [s] * 4)
746 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4)
747 * actual_rate [Hz] = (bytes * 250000) / time [us]
751 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
753 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4);
757 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1);
762 if (t2.tv_sec - t1.tv_sec > 1)
764 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
765 } while (nciv == ociv);
768 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1);
772 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
773 ch->blkcnt = oblkcnt;
775 /* turn time delta into us */
776 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec;
779 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us);
780 sc->flags |= ICH_CALIBRATE_DONE;
786 /* Just in case the timecounter screwed. It is possible, really. */
788 actual_48k_rate = ((uint64_t)ch->blksz * 250000) / wait_us;
790 actual_48k_rate = 48000;
792 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) {
793 sc->ac97rate = actual_48k_rate;
795 sc->ac97rate = 48000;
798 if (bootverbose || sc->ac97rate != 48000) {
799 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate);
800 if (sc->ac97rate != actual_48k_rate)
801 printf(", will use %d Hz", sc->ac97rate);
804 sc->flags |= ICH_CALIBRATE_DONE;
812 /* -------------------------------------------------------------------- */
813 /* Probe and attach the card */
816 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
818 struct sc_info *sc = (struct sc_info *)arg;
819 sc->desc_addr = segs->ds_addr;
824 ich_init(struct sc_info *sc)
828 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4);
830 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4);
832 if ((stat & ICH_GLOB_STA_PCR) == 0) {
833 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */
834 if (sc->vendor == INTEL_VENDORID && (
835 sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB ||
836 sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB ||
837 sc->devid == INTEL_82801GB)) {
838 sc->flags |= ICH_IGNORE_PCR;
839 device_printf(sc->dev, "primary codec not ready!\n");
844 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4);
846 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4);
849 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1))
851 if (sc->hasmic && ich_resetchan(sc, 2))
858 ich_pci_probe(device_t dev)
861 uint16_t devid, vendor;
863 vendor = pci_get_vendor(dev);
864 devid = pci_get_device(dev);
865 for (i = 0; i < sizeof(ich_devs)/sizeof(ich_devs[0]); i++) {
866 if (vendor == ich_devs[i].vendor &&
867 devid == ich_devs[i].devid) {
868 device_set_desc(dev, ich_devs[i].name);
869 /* allow a better driver to override us */
870 if ((ich_devs[i].options & PROBE_LOW) != 0)
871 return (BUS_PROBE_LOW_PRIORITY);
872 return (BUS_PROBE_DEFAULT);
879 ich_pci_attach(device_t dev)
883 uint16_t devid, vendor;
887 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
888 sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "snd_ich softc");
891 vendor = sc->vendor = pci_get_vendor(dev);
892 devid = sc->devid = pci_get_device(dev);
893 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev);
895 * The SiS 7012 register set isn't quite like the standard ich.
896 * There really should be a general "quirks" mechanism.
898 if (vendor == SIS_VENDORID && devid == SIS_7012) {
907 * Intel 440MX Errata #36
908 * - AC97 Soft Audio and Soft Modem Master Abort Errata
910 * http://www.intel.com/design/chipsets/specupdt/245051.htm
912 if (vendor == INTEL_VENDORID && devid == INTEL_82440MX)
913 sc->flags |= ICH_DMA_NOCACHE;
916 * Enable bus master. On ich4/5 this may prevent the detection of
917 * the primary codec becoming ready in ich_init().
919 pci_enable_busmaster(dev);
922 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as
923 * read-only. Need to enable "legacy support", by poking into
924 * pci config space. The driver should use MMBAR and MBBAR,
925 * but doing so will mess things up here. ich4 has enough new
926 * features it warrants it's own driver.
928 if (vendor == INTEL_VENDORID && (devid == INTEL_82801DB ||
929 devid == INTEL_82801EB || devid == INTEL_6300ESB ||
930 devid == INTEL_82801FB || devid == INTEL_82801GB)) {
931 sc->nambarid = PCIR_MMBAR;
932 sc->nabmbarid = PCIR_MBBAR;
933 sc->regtype = SYS_RES_MEMORY;
934 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1);
936 sc->nambarid = PCIR_NAMBAR;
937 sc->nabmbarid = PCIR_NABMBAR;
938 sc->regtype = SYS_RES_IOPORT;
941 sc->nambar = bus_alloc_resource_any(dev, sc->regtype,
942 &sc->nambarid, RF_ACTIVE);
943 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype,
944 &sc->nabmbarid, RF_ACTIVE);
946 if (!sc->nambar || !sc->nabmbar) {
947 device_printf(dev, "unable to map IO port space\n");
951 sc->nambart = rman_get_bustag(sc->nambar);
952 sc->nambarh = rman_get_bushandle(sc->nambar);
953 sc->nabmbart = rman_get_bustag(sc->nabmbar);
954 sc->nabmbarh = rman_get_bushandle(sc->nabmbar);
956 sc->bufsz = pcm_getbuffersize(dev,
957 ICH_MIN_BUFSZ, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ);
959 if (resource_int_value(device_get_name(dev),
960 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
961 sc->blkcnt = sc->bufsz / i;
963 while (sc->blkcnt >> i)
965 sc->blkcnt = 1 << (i - 1);
966 if (sc->blkcnt < ICH_MIN_BLKCNT)
967 sc->blkcnt = ICH_MIN_BLKCNT;
968 else if (sc->blkcnt > ICH_MAX_BLKCNT)
969 sc->blkcnt = ICH_MAX_BLKCNT;
971 sc->blkcnt = ICH_DEFAULT_BLKCNT;
973 if (resource_int_value(device_get_name(dev),
974 device_get_unit(dev), "highlatency", &i) == 0 && i != 0) {
975 sc->flags |= ICH_HIGH_LATENCY;
976 sc->blkcnt = ICH_MIN_BLKCNT;
979 if (resource_int_value(device_get_name(dev),
980 device_get_unit(dev), "fixedrate", &i) == 0 && i != 0)
981 sc->flags |= ICH_FIXED_RATE;
983 if (resource_int_value(device_get_name(dev),
984 device_get_unit(dev), "micchannel_enabled", &i) == 0 && i != 0)
988 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
989 RF_ACTIVE | RF_SHAREABLE);
990 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr,
992 device_printf(dev, "unable to map interrupt\n");
997 device_printf(dev, "unable to initialize the card\n");
1001 sc->codec = AC97_CREATE(dev, sc, ich_ac97);
1002 if (sc->codec == NULL)
1006 * Turn on inverted external amplifier sense flags for few
1010 case 0x202f161f: /* Gateway 7326GZ */
1011 case 0x203a161f: /* Gateway 4028GZ */
1012 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */
1013 case 0x8144104d: /* Sony VAIO PCG-TR* */
1014 case 0x8197104d: /* Sony S1XP */
1015 case 0x81c0104d: /* Sony VAIO type T */
1016 case 0x81c5104d: /* Sony VAIO VGN B1VP/B1XP */
1017 case 0x3089103c: /* Compaq Presario B3800 */
1018 case 0x309a103c: /* HP Compaq nx4300 */
1019 case 0x82131033: /* NEC VersaPro VJ10F/BH */
1020 case 0x82be1033: /* NEC VersaPro VJ12F/CH */
1021 ac97_setflags(sc->codec, ac97_getflags(sc->codec) | AC97_F_EAPD_INV);
1027 mixer_init(dev, ac97_getmixerclass(), sc->codec);
1029 /* check and set VRA function */
1030 extcaps = ac97_getextcaps(sc->codec);
1031 sc->hasvra = extcaps & AC97_EXTCAP_VRA;
1032 sc->hasvrm = extcaps & AC97_EXTCAP_VRM;
1033 sc->hasmic = (sc->hasmic != 0 &&
1034 (ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL)) ? 1 : 0;
1035 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
1037 sc->dtbl_size = sizeof(struct ich_desc) * ICH_DTBL_LENGTH *
1038 ((sc->hasmic) ? 3 : 2);
1041 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1042 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1043 sc->dtbl_size, 1, 0x3ffff, 0, NULL, NULL, &sc->dmat) != 0) {
1044 device_printf(dev, "unable to create dma tag\n");
1048 /* PCM channel tag */
1049 if (bus_dma_tag_create(bus_get_dma_tag(dev), ICH_MIN_BLKSZ, 0,
1050 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1051 sc->bufsz, 1, 0x3ffff, 0, NULL, NULL, &sc->chan_dmat) != 0) {
1052 device_printf(dev, "unable to create dma tag\n");
1056 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT |
1057 ((sc->flags & ICH_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
1061 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sc->dtbl_size,
1065 if (pcm_register(dev, sc, 1, (sc->hasmic) ? 2 : 1))
1068 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */
1069 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */
1071 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */
1073 if (sc->flags & ICH_FIXED_RATE) {
1074 sc->flags |= ICH_CALIBRATE_DONE;
1079 sc->intrhook.ich_func = ich_calibrate;
1080 sc->intrhook.ich_arg = sc;
1082 config_intrhook_establish(&sc->intrhook) != 0) {
1083 sc->intrhook.ich_func = NULL;
1092 ac97_destroy(sc->codec);
1094 bus_teardown_intr(dev, sc->irq, sc->ih);
1096 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1098 bus_release_resource(dev, sc->regtype,
1099 sc->nambarid, sc->nambar);
1101 bus_release_resource(dev, sc->regtype,
1102 sc->nabmbarid, sc->nabmbar);
1104 bus_dmamap_unload(sc->dmat, sc->dtmap);
1106 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap);
1108 bus_dma_tag_destroy(sc->chan_dmat);
1110 bus_dma_tag_destroy(sc->dmat);
1112 snd_mtxfree(sc->ich_lock);
1118 ich_pci_detach(device_t dev)
1123 r = pcm_unregister(dev);
1126 sc = pcm_getdevinfo(dev);
1128 bus_teardown_intr(dev, sc->irq, sc->ih);
1129 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1130 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar);
1131 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar);
1132 bus_dmamap_unload(sc->dmat, sc->dtmap);
1133 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap);
1134 bus_dma_tag_destroy(sc->chan_dmat);
1135 bus_dma_tag_destroy(sc->dmat);
1136 snd_mtxfree(sc->ich_lock);
1142 ich_pci_codec_reset(struct sc_info *sc)
1147 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4);
1148 control &= ~(ICH_GLOB_CTL_SHUT);
1149 control |= (control & ICH_GLOB_CTL_COLD) ?
1150 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD;
1151 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4);
1153 for (i = 500000; i; i--) {
1154 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR)
1155 break; /* or ICH_SCR? */
1160 printf("%s: time out\n", __func__);
1164 ich_pci_suspend(device_t dev)
1169 sc = pcm_getdevinfo(dev);
1171 for (i = 0 ; i < 3; i++) {
1172 sc->ch[i].run_save = sc->ch[i].run;
1173 if (sc->ch[i].run) {
1175 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT);
1184 ich_pci_resume(device_t dev)
1189 sc = pcm_getdevinfo(dev);
1191 if (sc->regtype == SYS_RES_IOPORT)
1192 pci_enable_io(dev, SYS_RES_IOPORT);
1194 pci_enable_io(dev, SYS_RES_MEMORY);
1195 pci_enable_busmaster(dev);
1198 /* Reinit audio device */
1199 if (ich_init(sc) == -1) {
1200 device_printf(dev, "unable to reinitialize the card\n");
1205 ich_pci_codec_reset(sc);
1207 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
1208 if (mixer_reinit(dev) == -1) {
1209 device_printf(dev, "unable to reinitialize the mixer\n");
1212 /* Re-start DMA engines */
1213 for (i = 0 ; i < 3; i++) {
1214 struct sc_chinfo *ch = &sc->ch[i];
1215 if (sc->ch[i].run_save) {
1216 ichchan_setblocksize(0, ch, ch->blksz);
1217 ichchan_setspeed(0, ch, ch->spd);
1218 ichchan_trigger(0, ch, PCMTRIG_START);
1224 static device_method_t ich_methods[] = {
1225 /* Device interface */
1226 DEVMETHOD(device_probe, ich_pci_probe),
1227 DEVMETHOD(device_attach, ich_pci_attach),
1228 DEVMETHOD(device_detach, ich_pci_detach),
1229 DEVMETHOD(device_suspend, ich_pci_suspend),
1230 DEVMETHOD(device_resume, ich_pci_resume),
1234 static driver_t ich_driver = {
1240 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0);
1241 MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1242 MODULE_VERSION(snd_ich, 1);