2 * Copyright (c) 2000-2004 Taku YAMAMOTO <taku@tackymt.homeip.net>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * maestro.c,v 1.23.2.1 2003/10/03 18:21:38 taku Exp
32 * Part of this code (especially in many magic numbers) was heavily inspired
33 * by the Linux driver originally written by
34 * Alan Cox <alan.cox@linux.org>, modified heavily by
35 * Zach Brown <zab@zabbo.net>.
37 * busdma()-ize and buffer size reduction were suggested by
38 * Cameron Grant <cg@freebsd.org>.
39 * Also he showed me the way to use busdma() suite.
41 * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
43 * Munehiro Matsuda <haro@tk.kubota.co.jp>,
44 * who brought patches based on the Linux driver with some simplification.
46 * Hardware volume controller was implemented by
47 * John Baldwin <jhb@freebsd.org>.
50 #include <dev/sound/pcm/sound.h>
51 #include <dev/sound/pcm/ac97.h>
52 #include <dev/pci/pcireg.h>
53 #include <dev/pci/pcivar.h>
55 #include <dev/sound/pci/maestro_reg.h>
57 SND_DECLARE_FILE("$FreeBSD$");
60 * PCI IDs of supported chips:
62 * MAESTRO-1 0x01001285
63 * MAESTRO-2 0x1968125d
64 * MAESTRO-2E 0x1978125d
67 #define MAESTRO_1_PCI_ID 0x01001285
68 #define MAESTRO_2_PCI_ID 0x1968125d
69 #define MAESTRO_2E_PCI_ID 0x1978125d
71 #define NEC_SUBID1 0x80581033 /* Taken from Linux driver */
72 #define NEC_SUBID2 0x803c1033 /* NEC VersaProNX VA26D */
75 # if AGG_MAXPLAYCH > 4
77 # define AGG_MAXPLAYCH 4
80 # define AGG_MAXPLAYCH 4
83 #define AGG_DEFAULT_BUFSZ 0x4000 /* 0x1000, but gets underflows */
87 #if __FreeBSD_version < 500000
88 # define critical_enter() disable_intr()
89 # define critical_exit() enable_intr()
93 #define PCIR_BAR(x) (PCIR_MAPS + (x) * 4)
97 /* -----------------------------
102 struct agg_info *parent;
104 /* FreeBSD newpcm related */
105 struct pcm_channel *channel;
106 struct snd_dbuf *buffer;
109 bus_addr_t phys; /* channel buffer physical address */
110 bus_addr_t base; /* channel buffer segment base */
111 u_int32_t blklen; /* DMA block length in WORDs */
112 u_int32_t buflen; /* channel buffer length in WORDs */
116 unsigned qs16 : 1; /* quantum size is 16bit */
117 unsigned us : 1; /* in unsigned format */
122 struct agg_info *parent;
124 /* FreeBSD newpcm related */
125 struct pcm_channel *channel;
126 struct snd_dbuf *buffer;
129 bus_addr_t phys; /* channel buffer physical address */
130 bus_addr_t base; /* channel buffer segment base */
131 u_int32_t blklen; /* DMA block length in WORDs */
132 u_int32_t buflen; /* channel buffer length in WORDs */
137 int16_t *src; /* stereo peer buffer */
138 int16_t *sink; /* channel buffer pointer */
139 volatile u_int32_t hwptr; /* ready point in 16bit sample */
143 /* FreeBSD newbus related */
146 /* I wonder whether bus_space_* are in common in *BSD... */
147 struct resource *reg;
150 bus_space_handle_t sh;
152 struct resource *irq;
156 bus_dma_tag_t buf_dmat;
157 bus_dma_tag_t stat_dmat;
159 /* FreeBSD SMPng related */
161 struct mtx lock; /* mutual exclusion */
163 /* FreeBSD newpcm related */
164 struct ac97_info *codec;
167 u_int8_t *stat; /* status buffer pointer */
168 bus_addr_t phys; /* status buffer physical address */
169 unsigned int bufsz; /* channel buffer size in bytes */
171 volatile u_int active;
172 struct agg_chinfo pch[AGG_MAXPLAYCH];
173 struct agg_rchinfo rch;
174 volatile u_int8_t curpwr; /* current power status: D[0-3] */
178 /* -----------------------------
181 static unsigned int powerstate_active = PCI_POWERSTATE_D1;
182 #ifdef MAESTRO_AGGRESSIVE_POWERSAVE
183 static unsigned int powerstate_idle = PCI_POWERSTATE_D2;
185 static unsigned int powerstate_idle = PCI_POWERSTATE_D1;
187 static unsigned int powerstate_init = PCI_POWERSTATE_D2;
189 /* XXX: this should move to a device specific sysctl dev.pcm.X.debug.Y via
190 device_get_sysctl_*() as discussed on multimedia@ in msg-id
191 <861wujij2q.fsf@xps.des.no> */
192 SYSCTL_NODE(_debug, OID_AUTO, maestro, CTLFLAG_RD, 0, "");
193 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_active, CTLFLAG_RW,
194 &powerstate_active, 0, "The Dx power state when active (0-1)");
195 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_idle, CTLFLAG_RW,
196 &powerstate_idle, 0, "The Dx power state when idle (0-2)");
197 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_init, CTLFLAG_RW,
199 "The Dx power state prior to the first use (0-2)");
202 /* -----------------------------
206 static void agg_sleep(struct agg_info*, const char *wmesg, int msec);
208 static __inline u_int32_t agg_rd(struct agg_info*, int, int size);
209 static __inline void agg_wr(struct agg_info*, int, u_int32_t data,
211 static int agg_rdcodec(struct agg_info*, int);
212 static int agg_wrcodec(struct agg_info*, int, u_int32_t);
214 static void ringbus_setdest(struct agg_info*, int, int);
216 static u_int16_t wp_rdreg(struct agg_info*, u_int16_t);
217 static void wp_wrreg(struct agg_info*, u_int16_t, u_int16_t);
218 static u_int16_t wp_rdapu(struct agg_info*, unsigned, u_int16_t);
219 static void wp_wrapu(struct agg_info*, unsigned, u_int16_t, u_int16_t);
220 static void wp_settimer(struct agg_info*, u_int);
221 static void wp_starttimer(struct agg_info*);
222 static void wp_stoptimer(struct agg_info*);
225 static u_int16_t wc_rdreg(struct agg_info*, u_int16_t);
227 static void wc_wrreg(struct agg_info*, u_int16_t, u_int16_t);
229 static u_int16_t wc_rdchctl(struct agg_info*, int);
231 static void wc_wrchctl(struct agg_info*, int, u_int16_t);
233 static void agg_stopclock(struct agg_info*, int part, int st);
235 static void agg_initcodec(struct agg_info*);
236 static void agg_init(struct agg_info*);
237 static void agg_power(struct agg_info*, int);
239 static void aggch_start_dac(struct agg_chinfo*);
240 static void aggch_stop_dac(struct agg_chinfo*);
241 static void aggch_start_adc(struct agg_rchinfo*);
242 static void aggch_stop_adc(struct agg_rchinfo*);
243 static void aggch_feed_adc_stereo(struct agg_rchinfo*);
244 static void aggch_feed_adc_mono(struct agg_rchinfo*);
246 #ifdef AGG_JITTER_CORRECTION
247 static void suppress_jitter(struct agg_chinfo*);
248 static void suppress_rec_jitter(struct agg_rchinfo*);
251 static void set_timer(struct agg_info*);
253 static void agg_intr(void *);
254 static int agg_probe(device_t);
255 static int agg_attach(device_t);
256 static int agg_detach(device_t);
257 static int agg_suspend(device_t);
258 static int agg_resume(device_t);
259 static int agg_shutdown(device_t);
261 static void *dma_malloc(bus_dma_tag_t, u_int32_t, bus_addr_t*);
262 static void dma_free(bus_dma_tag_t, void *);
265 /* -----------------------------
270 #define agg_lock(sc) snd_mtxlock(&((sc)->lock))
271 #define agg_unlock(sc) snd_mtxunlock(&((sc)->lock))
274 agg_sleep(struct agg_info *sc, const char *wmesg, int msec)
278 timo = msec * hz / 1000;
282 msleep(sc, &sc->lock, PWAIT, wmesg, timo);
284 tsleep(sc, PWAIT, wmesg, timo);
291 static __inline u_int32_t
292 agg_rd(struct agg_info *sc, int regno, int size)
296 return bus_space_read_1(sc->st, sc->sh, regno);
298 return bus_space_read_2(sc->st, sc->sh, regno);
300 return bus_space_read_4(sc->st, sc->sh, regno);
302 return ~(u_int32_t)0;
306 #define AGG_RD(sc, regno, size) \
307 bus_space_read_##size( \
308 ((struct agg_info*)(sc))->st, \
309 ((struct agg_info*)(sc))->sh, (regno))
312 agg_wr(struct agg_info *sc, int regno, u_int32_t data, int size)
316 bus_space_write_1(sc->st, sc->sh, regno, data);
319 bus_space_write_2(sc->st, sc->sh, regno, data);
322 bus_space_write_4(sc->st, sc->sh, regno, data);
327 #define AGG_WR(sc, regno, data, size) \
328 bus_space_write_##size( \
329 ((struct agg_info*)(sc))->st, \
330 ((struct agg_info*)(sc))->sh, (regno), (data))
332 /* -------------------------------------------------------------------- */
337 agg_codec_wait4idle(struct agg_info *ess)
341 while (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK) {
344 DELAY(2); /* 20.8us / 13 */
351 agg_rdcodec(struct agg_info *ess, int regno)
355 /* We have to wait for a SAFE time to write addr/data */
356 if (agg_codec_wait4idle(ess)) {
357 /* Timed out. No read performed. */
358 device_printf(ess->dev, "agg_rdcodec() PROGLESS timed out.\n");
362 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_READ | regno, 1);
363 /*DELAY(21); * AC97 cycle = 20.8usec */
365 /* Wait for data retrieve */
366 if (!agg_codec_wait4idle(ess)) {
367 ret = AGG_RD(ess, PORT_CODEC_REG, 2);
369 /* Timed out. No read performed. */
370 device_printf(ess->dev, "agg_rdcodec() RW_DONE timed out.\n");
378 agg_wrcodec(struct agg_info *ess, int regno, u_int32_t data)
380 /* We have to wait for a SAFE time to write addr/data */
381 if (agg_codec_wait4idle(ess)) {
382 /* Timed out. Abort writing. */
383 device_printf(ess->dev, "agg_wrcodec() PROGLESS timed out.\n");
387 AGG_WR(ess, PORT_CODEC_REG, data, 2);
388 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_WRITE | regno, 1);
390 /* Wait for write completion */
391 if (agg_codec_wait4idle(ess)) {
393 device_printf(ess->dev, "agg_wrcodec() RW_DONE timed out.\n");
401 ringbus_setdest(struct agg_info *ess, int src, int dest)
405 data = AGG_RD(ess, PORT_RINGBUS_CTRL, 4);
406 data &= ~(0xfU << src);
407 data |= (0xfU & dest) << src;
408 AGG_WR(ess, PORT_RINGBUS_CTRL, data, 4);
411 /* -------------------------------------------------------------------- */
416 wp_rdreg(struct agg_info *ess, u_int16_t reg)
418 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
419 return AGG_RD(ess, PORT_DSP_DATA, 2);
423 wp_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
425 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
426 AGG_WR(ess, PORT_DSP_DATA, data, 2);
430 wp_wait_data(struct agg_info *ess, u_int16_t data)
434 while (AGG_RD(ess, PORT_DSP_DATA, 2) != data) {
438 AGG_WR(ess, PORT_DSP_DATA, data, 2);
445 wp_rdapu(struct agg_info *ess, unsigned ch, u_int16_t reg)
447 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
448 if (wp_wait_data(ess, reg | (ch << 4)) != 0)
449 device_printf(ess->dev, "wp_rdapu() indexing timed out.\n");
450 return wp_rdreg(ess, WPREG_DATA_PORT);
454 wp_wrapu(struct agg_info *ess, unsigned ch, u_int16_t reg, u_int16_t data)
456 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
457 if (wp_wait_data(ess, reg | (ch << 4)) == 0) {
458 wp_wrreg(ess, WPREG_DATA_PORT, data);
459 if (wp_wait_data(ess, data) != 0)
460 device_printf(ess->dev,
461 "wp_wrapu() write timed out.\n");
463 device_printf(ess->dev, "wp_wrapu() indexing timed out.\n");
468 apu_setparam(struct agg_info *ess, int apuch,
469 u_int32_t wpwa, u_int16_t size, int16_t pan, u_int dv)
471 wp_wrapu(ess, apuch, APUREG_WAVESPACE, (wpwa >> 8) & APU_64KPAGE_MASK);
472 wp_wrapu(ess, apuch, APUREG_CURPTR, wpwa);
473 wp_wrapu(ess, apuch, APUREG_ENDPTR, wpwa + size);
474 wp_wrapu(ess, apuch, APUREG_LOOPLEN, size);
475 wp_wrapu(ess, apuch, APUREG_ROUTING, 0);
476 wp_wrapu(ess, apuch, APUREG_AMPLITUDE, 0xf000);
477 wp_wrapu(ess, apuch, APUREG_POSITION, 0x8f00
478 | (APU_RADIUS_MASK & (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT))
479 | (APU_PAN_MASK & ((pan + PAN_FRONT) << APU_PAN_SHIFT)));
480 wp_wrapu(ess, apuch, APUREG_FREQ_LOBYTE,
481 APU_plus6dB | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT));
482 wp_wrapu(ess, apuch, APUREG_FREQ_HIWORD, dv >> 8);
486 wp_settimer(struct agg_info *ess, u_int divide)
490 RANGE(divide, 2, 32 << 7);
492 for (; divide > 32; divide >>= 1) {
497 for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1)
500 wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
501 wp_wrreg(ess, WPREG_TIMER_FREQ, 0x9000 |
502 (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1));
503 wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
507 wp_starttimer(struct agg_info *ess)
509 AGG_WR(ess, PORT_INT_STAT, 1, 2);
510 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_INT_ENABLED
511 | AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
512 wp_wrreg(ess, WPREG_TIMER_START, 1);
516 wp_stoptimer(struct agg_info *ess)
518 AGG_WR(ess, PORT_HOSTINT_CTRL, ~HOSTINT_CTRL_DSOUND_INT_ENABLED
519 & AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
520 AGG_WR(ess, PORT_INT_STAT, 1, 2);
521 wp_wrreg(ess, WPREG_TIMER_START, 0);
524 /* -------------------------------------------------------------------- */
530 wc_rdreg(struct agg_info *ess, u_int16_t reg)
532 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
533 return AGG_RD(ess, PORT_WAVCACHE_DATA, 2);
538 wc_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
540 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
541 AGG_WR(ess, PORT_WAVCACHE_DATA, data, 2);
546 wc_rdchctl(struct agg_info *ess, int ch)
548 return wc_rdreg(ess, ch << 3);
553 wc_wrchctl(struct agg_info *ess, int ch, u_int16_t data)
555 wc_wrreg(ess, ch << 3, data);
558 /* -------------------------------------------------------------------- */
560 /* Power management */
562 agg_stopclock(struct agg_info *ess, int part, int st)
566 data = pci_read_config(ess->dev, CONF_ACPI_STOPCLOCK, 4);
568 if (st == PCI_POWERSTATE_D1)
569 data &= ~(1 << part);
572 if (st == PCI_POWERSTATE_D1 || st == PCI_POWERSTATE_D2)
573 data |= (0x10000 << part);
575 data &= ~(0x10000 << part);
576 pci_write_config(ess->dev, CONF_ACPI_STOPCLOCK, data, 4);
581 /* -----------------------------
586 agg_initcodec(struct agg_info* ess)
590 if (AGG_RD(ess, PORT_RINGBUS_CTRL, 4) & RINGBUS_CTRL_ACLINK_ENABLED) {
591 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
592 DELAY(104); /* 20.8us * (4 + 1) */
594 /* XXX - 2nd codec should be looked at. */
595 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_AC97_SWRESET, 4);
597 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
600 if (agg_rdcodec(ess, 0) < 0) {
601 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
604 /* Try cold reset. */
605 device_printf(ess->dev, "will perform cold reset.\n");
606 data = AGG_RD(ess, PORT_GPIO_DIR, 2);
607 if (pci_read_config(ess->dev, 0x58, 2) & 1)
609 data |= 0x009 & ~AGG_RD(ess, PORT_GPIO_DATA, 2);
610 AGG_WR(ess, PORT_GPIO_MASK, 0xff6, 2);
611 AGG_WR(ess, PORT_GPIO_DIR, data | 0x009, 2);
612 AGG_WR(ess, PORT_GPIO_DATA, 0x000, 2);
614 AGG_WR(ess, PORT_GPIO_DATA, 0x001, 2);
616 AGG_WR(ess, PORT_GPIO_DATA, 0x009, 2);
617 agg_sleep(ess, "agginicd", 500);
618 AGG_WR(ess, PORT_GPIO_DIR, data, 2);
619 DELAY(84); /* 20.8us * 4 */
620 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
626 agg_init(struct agg_info* ess)
630 /* Setup PCI config registers. */
632 /* Disable all legacy emulations. */
633 data = pci_read_config(ess->dev, CONF_LEGACY, 2);
634 data |= LEGACY_DISABLED;
635 pci_write_config(ess->dev, CONF_LEGACY, data, 2);
637 /* Disconnect from CHI. (Makes Dell inspiron 7500 work?)
638 * Enable posted write.
639 * Prefer PCI timing rather than that of ISA.
641 data = pci_read_config(ess->dev, CONF_MAESTRO, 4);
643 data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING;
644 data &= ~MAESTRO_SWAP_LR;
645 pci_write_config(ess->dev, CONF_MAESTRO, data, 4);
647 /* Turn off unused parts if necessary. */
648 /* consult CONF_MAESTRO. */
649 if (data & MAESTRO_SPDIF)
650 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D2);
652 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D1);
653 if (data & MAESTRO_HWVOL)
654 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D3);
656 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D1);
658 /* parts that never be used */
659 agg_stopclock(ess, ACPI_PART_978, PCI_POWERSTATE_D1);
660 agg_stopclock(ess, ACPI_PART_DAA, PCI_POWERSTATE_D1);
661 agg_stopclock(ess, ACPI_PART_GPIO, PCI_POWERSTATE_D1);
662 agg_stopclock(ess, ACPI_PART_SB, PCI_POWERSTATE_D1);
663 agg_stopclock(ess, ACPI_PART_FM, PCI_POWERSTATE_D1);
664 agg_stopclock(ess, ACPI_PART_MIDI, PCI_POWERSTATE_D1);
665 agg_stopclock(ess, ACPI_PART_GAME_PORT, PCI_POWERSTATE_D1);
667 /* parts that will be used only when play/recording */
668 agg_stopclock(ess, ACPI_PART_WP, PCI_POWERSTATE_D2);
670 /* parts that should always be turned on */
671 agg_stopclock(ess, ACPI_PART_CODEC_CLOCK, PCI_POWERSTATE_D3);
672 agg_stopclock(ess, ACPI_PART_GLUE, PCI_POWERSTATE_D3);
673 agg_stopclock(ess, ACPI_PART_PCI_IF, PCI_POWERSTATE_D3);
674 agg_stopclock(ess, ACPI_PART_RINGBUS, PCI_POWERSTATE_D3);
676 /* Reset direct sound. */
677 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_SOFT_RESET, 2);
679 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
681 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_RESET, 2);
683 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
686 /* Enable hardware volume control interruption. */
687 if (data & MAESTRO_HWVOL) /* XXX - why not use device flags? */
688 AGG_WR(ess, PORT_HOSTINT_CTRL,HOSTINT_CTRL_HWVOL_ENABLED, 2);
690 /* Setup Wave Processor. */
692 /* Enable WaveCache, set DMA base address. */
693 wp_wrreg(ess, WPREG_WAVE_ROMRAM,
694 WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED);
695 wp_wrreg(ess, WPREG_CRAM_DATA, 0);
697 AGG_WR(ess, PORT_WAVCACHE_CTRL,
698 WAVCACHE_ENABLED | WAVCACHE_WTSIZE_2MB | WAVCACHE_SGC_32_47, 2);
700 for (data = WAVCACHE_PCMBAR; data < WAVCACHE_PCMBAR + 4; data++)
701 wc_wrreg(ess, data, ess->phys >> WAVCACHE_BASEADDR_SHIFT);
703 /* Setup Codec/Ringbus. */
705 AGG_WR(ess, PORT_RINGBUS_CTRL,
706 RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED, 4);
708 wp_wrreg(ess, 0x08, 0xB004);
709 wp_wrreg(ess, 0x09, 0x001B);
710 wp_wrreg(ess, 0x0A, 0x8000);
711 wp_wrreg(ess, 0x0B, 0x3F37);
712 wp_wrreg(ess, WPREG_BASE, 0x8598); /* Parallel I/O */
713 wp_wrreg(ess, WPREG_BASE + 1, 0x7632);
714 ringbus_setdest(ess, RINGBUS_SRC_ADC,
715 RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN);
716 ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
717 RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC);
719 /* Enable S/PDIF if necessary. */
720 if (pci_read_config(ess->dev, CONF_MAESTRO, 4) & MAESTRO_SPDIF)
721 /* XXX - why not use device flags? */
722 AGG_WR(ess, PORT_RINGBUS_CTRL_B, RINGBUS_CTRL_SPDIF |
723 AGG_RD(ess, PORT_RINGBUS_CTRL_B, 1), 1);
725 /* Setup ASSP. Needed for Dell Inspiron 7500? */
726 AGG_WR(ess, PORT_ASSP_CTRL_B, 0x00, 1);
727 AGG_WR(ess, PORT_ASSP_CTRL_A, 0x03, 1);
728 AGG_WR(ess, PORT_ASSP_CTRL_C, 0x00, 1);
732 * There seems to be speciality with NEC systems.
734 switch (pci_get_subvendor(ess->dev)
735 | (pci_get_subdevice(ess->dev) << 16)) {
738 /* Matthew Braithwaite <matt@braithwaite.net> reported that
739 * NEC Versa LX doesn't need GPIO operation. */
740 AGG_WR(ess, PORT_GPIO_MASK, 0x9ff, 2);
741 AGG_WR(ess, PORT_GPIO_DIR,
742 AGG_RD(ess, PORT_GPIO_DIR, 2) | 0x600, 2);
743 AGG_WR(ess, PORT_GPIO_DATA, 0x200, 2);
748 /* Deals power state transition. Must be called with softc->lock held. */
750 agg_power(struct agg_info *ess, int status)
754 lastpwr = ess->curpwr;
755 if (lastpwr == status)
759 case PCI_POWERSTATE_D0:
760 case PCI_POWERSTATE_D1:
762 case PCI_POWERSTATE_D2:
763 pci_set_powerstate(ess->dev, status);
764 /* Turn on PCM-related parts. */
765 agg_wrcodec(ess, AC97_REG_POWER, 0);
768 if ((agg_rdcodec(ess, AC97_REG_POWER) & 3) != 3)
769 device_printf(ess->dev,
770 "warning: codec not ready.\n");
772 AGG_WR(ess, PORT_RINGBUS_CTRL,
773 (AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
774 & ~RINGBUS_CTRL_ACLINK_ENABLED)
775 | RINGBUS_CTRL_RINGBUS_ENABLED, 4);
777 AGG_WR(ess, PORT_RINGBUS_CTRL,
778 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
779 | RINGBUS_CTRL_ACLINK_ENABLED, 4);
781 case PCI_POWERSTATE_D3:
783 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
787 case PCI_POWERSTATE_D0:
788 case PCI_POWERSTATE_D1:
789 pci_set_powerstate(ess->dev, status);
793 case PCI_POWERSTATE_D2:
795 case PCI_POWERSTATE_D3:
797 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
801 case PCI_POWERSTATE_D0:
802 case PCI_POWERSTATE_D1:
803 /* Turn off PCM-related parts. */
804 AGG_WR(ess, PORT_RINGBUS_CTRL,
805 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
806 & ~RINGBUS_CTRL_RINGBUS_ENABLED, 4);
808 agg_wrcodec(ess, AC97_REG_POWER, 0x300);
812 pci_set_powerstate(ess->dev, status);
814 case PCI_POWERSTATE_D3:
815 /* Entirely power down. */
816 agg_wrcodec(ess, AC97_REG_POWER, 0xdf00);
818 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
820 if (lastpwr != PCI_POWERSTATE_D2)
822 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
823 AGG_WR(ess, PORT_HOSTINT_STAT, 0xff, 1);
824 pci_set_powerstate(ess->dev, status);
827 /* Invalid power state; let it ignored. */
832 ess->curpwr = status;
835 /* -------------------------------------------------------------------- */
837 /* Channel controller. */
840 aggch_start_dac(struct agg_chinfo *ch)
844 u_int16_t size, apuch, wtbar, wcreg, aputype;
849 wpwa = (ch->phys - ch->base) >> 1;
850 wtbar = 0xc & (wpwa >> WPWA_WTBAR_SHIFT(2));
851 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
853 apuch = (ch->num << 1) | 32;
854 pan = PAN_RIGHT - PAN_FRONT;
857 wcreg |= WAVCACHE_CHCTL_STEREO;
859 aputype = APUTYPE_16BITSTEREO;
864 aputype = APUTYPE_8BITSTEREO;
868 aputype = APUTYPE_16BITLINEAR;
870 aputype = APUTYPE_8BITLINEAR;
875 wcreg |= WAVCACHE_CHCTL_U8;
878 wtbar = (wtbar >> 1) + 4;
880 dv = (((speed % 48000) << 16) + 24000) / 48000
881 + ((speed / 48000) << 16);
883 agg_lock(ch->parent);
884 agg_power(ch->parent, powerstate_active);
886 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar,
887 ch->base >> WAVCACHE_BASEADDR_SHIFT);
888 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 1,
889 ch->base >> WAVCACHE_BASEADDR_SHIFT);
891 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 2,
892 ch->base >> WAVCACHE_BASEADDR_SHIFT);
893 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 3,
894 ch->base >> WAVCACHE_BASEADDR_SHIFT);
896 wc_wrchctl(ch->parent, apuch, wcreg);
897 wc_wrchctl(ch->parent, apuch + 1, wcreg);
899 apu_setparam(ch->parent, apuch, wpwa, size, pan, dv);
902 wpwa |= (WPWA_STEREO >> 1);
903 apu_setparam(ch->parent, apuch + 1, wpwa, size, -pan, dv);
906 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
907 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
908 wp_wrapu(ch->parent, apuch + 1, APUREG_APUTYPE,
909 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
912 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
913 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
916 /* to mark that this channel is ready for intr. */
917 ch->parent->active |= (1 << ch->num);
919 set_timer(ch->parent);
920 wp_starttimer(ch->parent);
921 agg_unlock(ch->parent);
925 aggch_stop_dac(struct agg_chinfo *ch)
927 agg_lock(ch->parent);
929 /* to mark that this channel no longer needs further intrs. */
930 ch->parent->active &= ~(1 << ch->num);
932 wp_wrapu(ch->parent, (ch->num << 1) | 32, APUREG_APUTYPE,
933 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
934 wp_wrapu(ch->parent, (ch->num << 1) | 33, APUREG_APUTYPE,
935 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
937 if (ch->parent->active) {
938 set_timer(ch->parent);
939 wp_starttimer(ch->parent);
941 wp_stoptimer(ch->parent);
942 agg_power(ch->parent, powerstate_idle);
944 agg_unlock(ch->parent);
948 aggch_start_adc(struct agg_rchinfo *ch)
950 bus_addr_t wpwa, wpwa2;
951 u_int16_t wcreg, wcreg2;
955 /* speed > 48000 not cared */
956 dv = ((ch->speed << 16) + 24000) / 48000;
958 /* RATECONV doesn't seem to like dv == 0x10000. */
963 wpwa = (ch->srcphys - ch->base) >> 1;
964 wpwa2 = (ch->srcphys + ch->parent->bufsz/2 - ch->base) >> 1;
965 wcreg = (ch->srcphys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
966 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
967 pan = PAN_LEFT - PAN_FRONT;
969 wpwa = (ch->phys - ch->base) >> 1;
970 wpwa2 = (ch->srcphys - ch->base) >> 1;
971 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
972 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
976 agg_lock(ch->parent);
979 agg_power(ch->parent, powerstate_active);
981 /* Invalidate WaveCache. */
982 wc_wrchctl(ch->parent, 0, wcreg | WAVCACHE_CHCTL_STEREO);
983 wc_wrchctl(ch->parent, 1, wcreg | WAVCACHE_CHCTL_STEREO);
984 wc_wrchctl(ch->parent, 2, wcreg2 | WAVCACHE_CHCTL_STEREO);
985 wc_wrchctl(ch->parent, 3, wcreg2 | WAVCACHE_CHCTL_STEREO);
987 /* Load APU registers. */
988 /* APU #0 : Sample rate converter for left/center. */
989 apu_setparam(ch->parent, 0, WPWA_USE_SYSMEM | wpwa,
990 ch->buflen >> ch->stereo, 0, dv);
991 wp_wrapu(ch->parent, 0, APUREG_AMPLITUDE, 0);
992 wp_wrapu(ch->parent, 0, APUREG_ROUTING, 2 << APU_DATASRC_A_SHIFT);
994 /* APU #1 : Sample rate converter for right. */
995 apu_setparam(ch->parent, 1, WPWA_USE_SYSMEM | wpwa2,
996 ch->buflen >> ch->stereo, 0, dv);
997 wp_wrapu(ch->parent, 1, APUREG_AMPLITUDE, 0);
998 wp_wrapu(ch->parent, 1, APUREG_ROUTING, 3 << APU_DATASRC_A_SHIFT);
1000 /* APU #2 : Input mixer for left. */
1001 apu_setparam(ch->parent, 2, WPWA_USE_SYSMEM | 0,
1002 ch->parent->bufsz >> 2, pan, 0x10000);
1003 wp_wrapu(ch->parent, 2, APUREG_AMPLITUDE, 0);
1004 wp_wrapu(ch->parent, 2, APUREG_EFFECT_GAIN, 0xf0);
1005 wp_wrapu(ch->parent, 2, APUREG_ROUTING, 0x15 << APU_DATASRC_A_SHIFT);
1007 /* APU #3 : Input mixer for right. */
1008 apu_setparam(ch->parent, 3, WPWA_USE_SYSMEM | (ch->parent->bufsz >> 2),
1009 ch->parent->bufsz >> 2, -pan, 0x10000);
1010 wp_wrapu(ch->parent, 3, APUREG_AMPLITUDE, 0);
1011 wp_wrapu(ch->parent, 3, APUREG_EFFECT_GAIN, 0xf0);
1012 wp_wrapu(ch->parent, 3, APUREG_ROUTING, 0x14 << APU_DATASRC_A_SHIFT);
1014 /* to mark this channel ready for intr. */
1015 ch->parent->active |= (1 << ch->parent->playchns);
1019 wp_wrapu(ch->parent, 0, APUREG_APUTYPE,
1020 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1021 wp_wrapu(ch->parent, 1, APUREG_APUTYPE,
1022 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1023 wp_wrapu(ch->parent, 2, APUREG_APUTYPE,
1024 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1025 wp_wrapu(ch->parent, 3, APUREG_APUTYPE,
1026 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1029 set_timer(ch->parent);
1030 wp_starttimer(ch->parent);
1031 agg_unlock(ch->parent);
1035 aggch_stop_adc(struct agg_rchinfo *ch)
1039 agg_lock(ch->parent);
1041 /* to mark that this channel no longer needs further intrs. */
1042 ch->parent->active &= ~(1 << ch->parent->playchns);
1044 for (apuch = 0; apuch < 4; apuch++)
1045 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
1046 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1048 if (ch->parent->active) {
1049 set_timer(ch->parent);
1050 wp_starttimer(ch->parent);
1052 wp_stoptimer(ch->parent);
1053 agg_power(ch->parent, powerstate_idle);
1055 agg_unlock(ch->parent);
1059 * Feed from L/R channel of ADC to destination with stereo interleaving.
1060 * This function expects n not overwrapping the buffer boundary.
1061 * Note that n is measured in sample unit.
1063 * XXX - this function works in 16bit stereo format only.
1066 interleave(int16_t *l, int16_t *r, int16_t *p, unsigned n)
1070 for (end = l + n; l < end; ) {
1077 aggch_feed_adc_stereo(struct agg_rchinfo *ch)
1082 agg_lock(ch->parent);
1083 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1084 agg_unlock(ch->parent);
1085 cur -= 0xffff & ((ch->srcphys - ch->base) >> 1);
1087 src2 = ch->src + ch->parent->bufsz/4;
1090 interleave(ch->src + last, src2 + last,
1091 ch->sink + 2*last, ch->buflen/2 - last);
1092 interleave(ch->src, src2,
1094 } else if (cur > last)
1095 interleave(ch->src + last, src2 + last,
1096 ch->sink + 2*last, cur - last);
1101 * Feed from R channel of ADC and mixdown to destination L/center.
1102 * This function expects n not overwrapping the buffer boundary.
1103 * Note that n is measured in sample unit.
1105 * XXX - this function works in 16bit monoral format only.
1108 mixdown(int16_t *src, int16_t *dest, unsigned n)
1112 for (end = dest + n; dest < end; dest++)
1113 *dest = (int16_t)(((int)*dest - (int)*src++) / 2);
1117 aggch_feed_adc_mono(struct agg_rchinfo *ch)
1121 agg_lock(ch->parent);
1122 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1123 agg_unlock(ch->parent);
1124 cur -= 0xffff & ((ch->phys - ch->base) >> 1);
1128 mixdown(ch->src + last, ch->sink + last, ch->buflen - last);
1129 mixdown(ch->src, ch->sink, cur);
1130 } else if (cur > last)
1131 mixdown(ch->src + last, ch->sink + last, cur - last);
1135 #ifdef AGG_JITTER_CORRECTION
1137 * Stereo jitter suppressor.
1138 * Sometimes playback pointers differ in stereo-paired channels.
1139 * Calling this routine within intr fixes the problem.
1142 suppress_jitter(struct agg_chinfo *ch)
1145 int cp1, cp2, diff /*, halfsize*/ ;
1147 /*halfsize = (ch->qs16? ch->buflen >> 2 : ch->buflen >> 1);*/
1148 cp1 = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1149 cp2 = wp_rdapu(ch->parent, (ch->num << 1) | 33, APUREG_CURPTR);
1151 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1152 if (diff > 1 /* && diff < halfsize*/ )
1153 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1159 suppress_rec_jitter(struct agg_rchinfo *ch)
1161 int cp1, cp2, diff /*, halfsize*/ ;
1163 /*halfsize = (ch->stereo? ch->buflen >> 2 : ch->buflen >> 1);*/
1164 cp1 = (ch->stereo? ch->parent->bufsz >> 2 : ch->parent->bufsz >> 1)
1165 + wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1166 cp2 = wp_rdapu(ch->parent, 1, APUREG_CURPTR);
1168 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1169 if (diff > 1 /* && diff < halfsize*/ )
1170 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1176 calc_timer_div(struct agg_chinfo *ch)
1183 printf("snd_maestro: pch[%d].speed == 0, which shouldn't\n",
1188 return (48000 * (ch->blklen << (!ch->qs16 + !ch->stereo))
1189 + speed - 1) / speed;
1193 calc_timer_div_rch(struct agg_rchinfo *ch)
1200 printf("snd_maestro: rch.speed == 0, which shouldn't\n");
1204 return (48000 * (ch->blklen << (!ch->stereo))
1205 + speed - 1) / speed;
1209 set_timer(struct agg_info *ess)
1212 u_int dv = 32 << 7, newdv;
1214 for (i = 0; i < ess->playchns; i++)
1215 if ((ess->active & (1 << i)) &&
1216 (dv > (newdv = calc_timer_div(ess->pch + i))))
1218 if ((ess->active & (1 << i)) &&
1219 (dv > (newdv = calc_timer_div_rch(&ess->rch))))
1222 wp_settimer(ess, dv);
1226 /* -----------------------------
1230 /* AC97 mixer interface. */
1233 agg_ac97_init(kobj_t obj, void *sc)
1235 struct agg_info *ess = sc;
1237 return (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK)? 0 : 1;
1241 agg_ac97_read(kobj_t obj, void *sc, int regno)
1243 struct agg_info *ess = sc;
1246 /* XXX sound locking violation: agg_lock(ess); */
1247 ret = agg_rdcodec(ess, regno);
1248 /* agg_unlock(ess); */
1253 agg_ac97_write(kobj_t obj, void *sc, int regno, u_int32_t data)
1255 struct agg_info *ess = sc;
1258 /* XXX sound locking violation: agg_lock(ess); */
1259 ret = agg_wrcodec(ess, regno, data);
1260 /* agg_unlock(ess); */
1265 static kobj_method_t agg_ac97_methods[] = {
1266 KOBJMETHOD(ac97_init, agg_ac97_init),
1267 KOBJMETHOD(ac97_read, agg_ac97_read),
1268 KOBJMETHOD(ac97_write, agg_ac97_write),
1271 AC97_DECLARE(agg_ac97);
1274 /* -------------------------------------------------------------------- */
1276 /* Playback channel. */
1279 aggpch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
1280 struct pcm_channel *c, int dir)
1282 struct agg_info *ess = devinfo;
1283 struct agg_chinfo *ch;
1284 bus_addr_t physaddr;
1287 KASSERT((dir == PCMDIR_PLAY),
1288 ("aggpch_init() called for RECORDING channel!"));
1289 ch = ess->pch + ess->playchns;
1294 ch->num = ess->playchns;
1296 p = dma_malloc(ess->buf_dmat, ess->bufsz, &physaddr);
1299 ch->phys = physaddr;
1300 ch->base = physaddr & ((~(bus_addr_t)0) << WAVCACHE_BASEADDR_SHIFT);
1302 sndbuf_setup(b, p, ess->bufsz);
1303 ch->blklen = sndbuf_getblksz(b) / 2;
1304 ch->buflen = sndbuf_getsize(b) / 2;
1311 adjust_pchbase(struct agg_chinfo *chans, u_int n, u_int size)
1313 struct agg_chinfo *pchs[AGG_MAXPLAYCH];
1317 /* sort pchs by phys address */
1318 for (i = 0; i < n; i++) {
1319 for (j = 0; j < i; j++)
1320 if (chans[i].phys < pchs[j]->phys) {
1321 for (k = i; k > j; k--)
1322 pchs[k] = pchs[k - 1];
1325 pchs[j] = chans + i;
1328 /* use new base register if next buffer can not be addressed
1329 via current base. */
1330 #define BASE_SHIFT (WPWA_WTBAR_SHIFT(2) + 2 + 1)
1331 base = pchs[0]->base;
1332 for (k = 1, i = 1; i < n; i++) {
1333 if (pchs[i]->phys + size - base >= 1 << BASE_SHIFT)
1334 /* not addressable: assign new base */
1335 base = (pchs[i]->base -= k++ << BASE_SHIFT);
1337 pchs[i]->base = base;
1342 printf("Total of %d bases are assigned.\n", k);
1343 for (i = 0; i < n; i++) {
1344 printf("ch.%d: phys 0x%llx, wpwa 0x%llx\n",
1345 i, (long long)chans[i].phys,
1346 (long long)(chans[i].phys -
1347 chans[i].base) >> 1);
1353 aggpch_free(kobj_t obj, void *data)
1355 struct agg_chinfo *ch = data;
1356 struct agg_info *ess = ch->parent;
1358 /* free up buffer - called after channel stopped */
1359 dma_free(ess->buf_dmat, sndbuf_getbuf(ch->buffer));
1361 /* return 0 if ok */
1366 aggpch_setformat(kobj_t obj, void *data, u_int32_t format)
1368 struct agg_chinfo *ch = data;
1370 if (format & AFMT_BIGENDIAN || format & AFMT_U16_LE)
1372 ch->stereo = ch->qs16 = ch->us = 0;
1373 if (format & AFMT_STEREO)
1376 if (format & AFMT_U8 || format & AFMT_S8) {
1377 if (format & AFMT_U8)
1385 aggpch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1387 return ((struct agg_chinfo*)data)->speed = speed;
1391 aggpch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1393 struct agg_chinfo *ch = data;
1396 /* try to keep at least 20msec DMA space */
1397 blkcnt = (ch->speed << (ch->stereo + ch->qs16)) / (50 * blocksize);
1398 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1400 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1401 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1402 blkcnt = sndbuf_getblkcnt(ch->buffer);
1403 blocksize = sndbuf_getblksz(ch->buffer);
1405 sndbuf_setblkcnt(ch->buffer, blkcnt);
1406 sndbuf_setblksz(ch->buffer, blocksize);
1409 ch->blklen = blocksize / 2;
1410 ch->buflen = blkcnt * blocksize / 2;
1415 aggpch_trigger(kobj_t obj, void *data, int go)
1417 struct agg_chinfo *ch = data;
1420 case PCMTRIG_EMLDMAWR:
1423 aggch_start_dac(ch);
1434 aggpch_getptr(kobj_t obj, void *data)
1436 struct agg_chinfo *ch = data;
1439 agg_lock(ch->parent);
1440 cp = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1441 agg_unlock(ch->parent);
1443 return ch->qs16 && ch->stereo
1444 ? (cp << 2) - ((0xffff << 2) & (ch->phys - ch->base))
1445 : (cp << 1) - ((0xffff << 1) & (ch->phys - ch->base));
1448 static struct pcmchan_caps *
1449 aggpch_getcaps(kobj_t obj, void *data)
1451 static u_int32_t playfmt[] = {
1453 AFMT_STEREO | AFMT_U8,
1455 AFMT_STEREO | AFMT_S8,
1457 AFMT_STEREO | AFMT_S16_LE,
1460 static struct pcmchan_caps playcaps = {8000, 48000, playfmt, 0};
1466 static kobj_method_t aggpch_methods[] = {
1467 KOBJMETHOD(channel_init, aggpch_init),
1468 KOBJMETHOD(channel_free, aggpch_free),
1469 KOBJMETHOD(channel_setformat, aggpch_setformat),
1470 KOBJMETHOD(channel_setspeed, aggpch_setspeed),
1471 KOBJMETHOD(channel_setblocksize, aggpch_setblocksize),
1472 KOBJMETHOD(channel_trigger, aggpch_trigger),
1473 KOBJMETHOD(channel_getptr, aggpch_getptr),
1474 KOBJMETHOD(channel_getcaps, aggpch_getcaps),
1477 CHANNEL_DECLARE(aggpch);
1480 /* -------------------------------------------------------------------- */
1482 /* Recording channel. */
1485 aggrch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
1486 struct pcm_channel *c, int dir)
1488 struct agg_info *ess = devinfo;
1489 struct agg_rchinfo *ch;
1492 KASSERT((dir == PCMDIR_REC),
1493 ("aggrch_init() called for PLAYBACK channel!"));
1500 /* Uses the bottom-half of the status buffer. */
1501 p = ess->stat + ess->bufsz;
1502 ch->phys = ess->phys + ess->bufsz;
1503 ch->base = ess->phys;
1504 ch->src = (int16_t *)(p + ess->bufsz);
1505 ch->srcphys = ch->phys + ess->bufsz;
1506 ch->sink = (int16_t *)p;
1508 sndbuf_setup(b, p, ess->bufsz);
1509 ch->blklen = sndbuf_getblksz(b) / 2;
1510 ch->buflen = sndbuf_getsize(b) / 2;
1516 aggrch_setformat(kobj_t obj, void *data, u_int32_t format)
1518 struct agg_rchinfo *ch = data;
1520 if (!(format & AFMT_S16_LE))
1522 if (format & AFMT_STEREO)
1530 aggrch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1532 return ((struct agg_rchinfo*)data)->speed = speed;
1536 aggrch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1538 struct agg_rchinfo *ch = data;
1541 /* try to keep at least 20msec DMA space */
1542 blkcnt = (ch->speed << ch->stereo) / (25 * blocksize);
1543 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1545 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1546 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1547 blkcnt = sndbuf_getblkcnt(ch->buffer);
1548 blocksize = sndbuf_getblksz(ch->buffer);
1550 sndbuf_setblkcnt(ch->buffer, blkcnt);
1551 sndbuf_setblksz(ch->buffer, blocksize);
1554 ch->blklen = blocksize / 2;
1555 ch->buflen = blkcnt * blocksize / 2;
1560 aggrch_trigger(kobj_t obj, void *sc, int go)
1562 struct agg_rchinfo *ch = sc;
1565 case PCMTRIG_EMLDMARD:
1567 aggch_feed_adc_stereo(ch);
1569 aggch_feed_adc_mono(ch);
1572 aggch_start_adc(ch);
1583 aggrch_getptr(kobj_t obj, void *sc)
1585 struct agg_rchinfo *ch = sc;
1587 return ch->stereo? ch->hwptr << 2 : ch->hwptr << 1;
1590 static struct pcmchan_caps *
1591 aggrch_getcaps(kobj_t obj, void *sc)
1593 static u_int32_t recfmt[] = {
1595 AFMT_STEREO | AFMT_S16_LE,
1598 static struct pcmchan_caps reccaps = {8000, 48000, recfmt, 0};
1603 static kobj_method_t aggrch_methods[] = {
1604 KOBJMETHOD(channel_init, aggrch_init),
1605 /* channel_free: no-op */
1606 KOBJMETHOD(channel_setformat, aggrch_setformat),
1607 KOBJMETHOD(channel_setspeed, aggrch_setspeed),
1608 KOBJMETHOD(channel_setblocksize, aggrch_setblocksize),
1609 KOBJMETHOD(channel_trigger, aggrch_trigger),
1610 KOBJMETHOD(channel_getptr, aggrch_getptr),
1611 KOBJMETHOD(channel_getcaps, aggrch_getcaps),
1614 CHANNEL_DECLARE(aggrch);
1617 /* -----------------------------
1624 struct agg_info* ess = sc;
1625 register u_int8_t status;
1629 status = AGG_RD(ess, PORT_HOSTINT_STAT, 1);
1633 /* Acknowledge intr. */
1634 AGG_WR(ess, PORT_HOSTINT_STAT, status, 1);
1636 if (status & HOSTINT_STAT_DSOUND) {
1637 #ifdef AGG_JITTER_CORRECTION
1640 if (ess->curpwr <= PCI_POWERSTATE_D1) {
1641 AGG_WR(ess, PORT_INT_STAT, 1, 2);
1642 #ifdef AGG_JITTER_CORRECTION
1643 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1644 if (ess->active & m)
1645 suppress_jitter(ess->pch + i);
1647 if (ess->active & m)
1648 suppress_rec_jitter(&ess->rch);
1651 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1652 if (ess->active & m) {
1653 if (ess->curpwr <= PCI_POWERSTATE_D1)
1654 chn_intr(ess->pch[i].channel);
1661 if ((ess->active & m)
1662 && ess->curpwr <= PCI_POWERSTATE_D1)
1663 chn_intr(ess->rch.channel);
1665 #ifdef AGG_JITTER_CORRECTION
1671 if (status & HOSTINT_STAT_HWVOL) {
1672 register u_int8_t event;
1675 event = AGG_RD(ess, PORT_HWVOL_MASTER, 1);
1676 AGG_WR(ess, PORT_HWVOL_MASTER, HWVOL_NOP, 1);
1681 mixer_hwvol_step(ess->dev, 1, 1);
1684 mixer_hwvol_step(ess->dev, -1, -1);
1689 if (event & HWVOL_MUTE) {
1690 mixer_hwvol_mute(ess->dev);
1693 device_printf(ess->dev,
1694 "%s: unknown HWVOL event 0x%x\n",
1695 device_get_nameunit(ess->dev), event);
1701 setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1703 bus_addr_t *phys = arg;
1705 *phys = error? 0 : segs->ds_addr;
1708 printf("setmap (%lx, %lx), nseg=%d, error=%d\n",
1709 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
1715 dma_malloc(bus_dma_tag_t dmat, u_int32_t sz, bus_addr_t *phys)
1720 if (bus_dmamem_alloc(dmat, &buf, BUS_DMA_NOWAIT, &map))
1722 if (bus_dmamap_load(dmat, map, buf, sz, setmap, phys, 0)
1724 bus_dmamem_free(dmat, buf, map);
1731 dma_free(bus_dma_tag_t dmat, void *buf)
1733 bus_dmamem_free(dmat, buf, NULL);
1737 agg_probe(device_t dev)
1741 switch (pci_get_devid(dev)) {
1742 case MAESTRO_1_PCI_ID:
1743 s = "ESS Technology Maestro-1";
1746 case MAESTRO_2_PCI_ID:
1747 s = "ESS Technology Maestro-2";
1750 case MAESTRO_2E_PCI_ID:
1751 s = "ESS Technology Maestro-2E";
1755 if (s != NULL && pci_get_class(dev) == PCIC_MULTIMEDIA) {
1756 device_set_desc(dev, s);
1757 return BUS_PROBE_DEFAULT;
1763 agg_attach(device_t dev)
1765 struct agg_info *ess = NULL;
1767 int regid = PCIR_BAR(0);
1768 struct resource *reg = NULL;
1769 struct ac97_info *codec = NULL;
1771 struct resource *irq = NULL;
1773 char status[SND_STATUSLEN];
1776 ess = malloc(sizeof(*ess), M_DEVBUF, M_WAITOK | M_ZERO);
1780 mtx_init(&ess->lock, device_get_desc(dev), "snd_maestro softc",
1781 MTX_DEF | MTX_RECURSE);
1782 if (!mtx_initialized(&ess->lock)) {
1783 device_printf(dev, "failed to create a mutex.\n");
1789 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
1790 "dac", &dacn) == 0) {
1793 else if (dacn > AGG_MAXPLAYCH)
1794 dacn = AGG_MAXPLAYCH;
1796 dacn = AGG_MAXPLAYCH;
1798 ess->bufsz = pcm_getbuffersize(dev, 4096, AGG_DEFAULT_BUFSZ, 65536);
1799 if (bus_dma_tag_create(/*parent*/ bus_get_dma_tag(dev),
1800 /*align */ 4, 1 << (16+1),
1801 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1802 /*filter*/ NULL, NULL,
1803 /*size */ ess->bufsz, 1, 0x3ffff,
1805 #if __FreeBSD_version >= 501102
1806 /*lock */ busdma_lock_mutex, &Giant,
1808 &ess->buf_dmat) != 0) {
1809 device_printf(dev, "unable to create dma tag\n");
1814 if (bus_dma_tag_create(/*parent*/ bus_get_dma_tag(dev),
1815 /*align */ 1 << WAVCACHE_BASEADDR_SHIFT,
1817 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1818 /*filter*/ NULL, NULL,
1819 /*size */ 3*ess->bufsz, 1, 0x3ffff,
1821 #if __FreeBSD_version >= 501102
1822 /*lock */ busdma_lock_mutex, &Giant,
1824 &ess->stat_dmat) != 0) {
1825 device_printf(dev, "unable to create dma tag\n");
1830 /* Allocate the room for brain-damaging status buffer. */
1831 ess->stat = dma_malloc(ess->stat_dmat, 3*ess->bufsz, &ess->phys);
1832 if (ess->stat == NULL) {
1833 device_printf(dev, "cannot allocate status buffer\n");
1838 device_printf(dev, "Maestro status/record buffer: %#llx\n",
1839 (long long)ess->phys);
1841 /* State D0-uninitialized. */
1842 ess->curpwr = PCI_POWERSTATE_D3;
1843 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1845 data = pci_read_config(dev, PCIR_COMMAND, 2);
1846 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN);
1847 pci_write_config(dev, PCIR_COMMAND, data, 2);
1848 data = pci_read_config(dev, PCIR_COMMAND, 2);
1850 /* Allocate resources. */
1851 if (data & PCIM_CMD_PORTEN)
1852 reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, ®id,
1857 ess->st = rman_get_bustag(reg);
1858 ess->sh = rman_get_bushandle(reg);
1860 device_printf(dev, "unable to map register space\n");
1864 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqid,
1865 RF_ACTIVE | RF_SHAREABLE);
1870 device_printf(dev, "unable to map interrupt\n");
1875 /* Setup resources. */
1876 if (snd_setup_intr(dev, irq, INTR_MPSAFE, agg_intr, ess, &ih)) {
1877 device_printf(dev, "unable to setup interrupt\n");
1883 /* Transition from D0-uninitialized to D0. */
1885 agg_power(ess, PCI_POWERSTATE_D0);
1886 if (agg_rdcodec(ess, 0) == 0x80) {
1887 /* XXX - TODO: PT101 */
1889 device_printf(dev, "PT101 codec detected!\n");
1894 codec = AC97_CREATE(dev, ess, agg_ac97);
1895 if (codec == NULL) {
1896 device_printf(dev, "failed to create AC97 codec softc!\n");
1900 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) {
1901 device_printf(dev, "mixer initialization failed!\n");
1907 ret = pcm_register(dev, ess, dacn, 1);
1911 mixer_hwvol_init(dev);
1913 agg_power(ess, powerstate_init);
1915 for (data = 0; data < dacn; data++)
1916 pcm_addchan(dev, PCMDIR_PLAY, &aggpch_class, ess);
1917 pcm_addchan(dev, PCMDIR_REC, &aggrch_class, ess);
1918 adjust_pchbase(ess->pch, ess->playchns, ess->bufsz);
1920 snprintf(status, SND_STATUSLEN,
1921 "port 0x%lx-0x%lx irq %ld at device %d.%d on pci%d",
1922 rman_get_start(reg), rman_get_end(reg), rman_get_start(irq),
1923 pci_get_slot(dev), pci_get_function(dev), pci_get_bus(dev));
1924 pcm_setstatus(dev, status);
1930 ac97_destroy(codec);
1932 bus_teardown_intr(dev, irq, ih);
1934 bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
1936 bus_release_resource(dev, SYS_RES_IOPORT, regid, reg);
1938 if (ess->stat != NULL)
1939 dma_free(ess->stat_dmat, ess->stat);
1940 if (ess->stat_dmat != NULL)
1941 bus_dma_tag_destroy(ess->stat_dmat);
1942 if (ess->buf_dmat != NULL)
1943 bus_dma_tag_destroy(ess->buf_dmat);
1945 if (mtx_initialized(&ess->lock))
1946 mtx_destroy(&ess->lock);
1948 free(ess, M_DEVBUF);
1955 agg_detach(device_t dev)
1957 struct agg_info *ess = pcm_getdevinfo(dev);
1961 icr = AGG_RD(ess, PORT_HOSTINT_CTRL, 2);
1962 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
1966 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1972 r = pcm_unregister(dev);
1974 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1979 agg_power(ess, PCI_POWERSTATE_D3);
1982 bus_teardown_intr(dev, ess->irq, ess->ih);
1983 bus_release_resource(dev, SYS_RES_IRQ, ess->irqid, ess->irq);
1984 bus_release_resource(dev, SYS_RES_IOPORT, ess->regid, ess->reg);
1985 dma_free(ess->stat_dmat, ess->stat);
1986 bus_dma_tag_destroy(ess->stat_dmat);
1987 bus_dma_tag_destroy(ess->buf_dmat);
1989 mtx_destroy(&ess->lock);
1991 free(ess, M_DEVBUF);
1996 agg_suspend(device_t dev)
1998 struct agg_info *ess = pcm_getdevinfo(dev);
2004 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
2006 agg_power(ess, PCI_POWERSTATE_D3);
2016 agg_resume(device_t dev)
2019 struct agg_info *ess = pcm_getdevinfo(dev);
2025 for (i = 0; i < ess->playchns; i++)
2026 if (ess->active & (1 << i))
2027 aggch_start_dac(ess->pch + i);
2028 if (ess->active & (1 << i))
2029 aggch_start_adc(&ess->rch);
2033 agg_power(ess, powerstate_init);
2039 if (mixer_reinit(dev)) {
2040 device_printf(dev, "unable to reinitialize the mixer\n");
2048 agg_shutdown(device_t dev)
2050 struct agg_info *ess = pcm_getdevinfo(dev);
2053 agg_power(ess, PCI_POWERSTATE_D3);
2060 static device_method_t agg_methods[] = {
2061 DEVMETHOD(device_probe, agg_probe),
2062 DEVMETHOD(device_attach, agg_attach),
2063 DEVMETHOD(device_detach, agg_detach),
2064 DEVMETHOD(device_suspend, agg_suspend),
2065 DEVMETHOD(device_resume, agg_resume),
2066 DEVMETHOD(device_shutdown, agg_shutdown),
2071 static driver_t agg_driver = {
2077 /*static devclass_t pcm_devclass;*/
2079 DRIVER_MODULE(snd_maestro, pci, agg_driver, pcm_devclass, 0, 0);
2080 MODULE_DEPEND(snd_maestro, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2081 MODULE_VERSION(snd_maestro, 1);