2 * Copyright (c) 2001 Scott Long <scottl@freebsd.org>
3 * Copyright (c) 2001 Darrell Anderson <anderson@cs.duke.edu>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Maestro-3/Allegro FreeBSD pcm sound driver
31 * executive status summary:
32 * (+) /dev/dsp multiple concurrent play channels.
33 * (+) /dev/dsp config (speed, mono/stereo, 8/16 bit).
34 * (+) /dev/mixer sets left/right volumes.
35 * (+) /dev/dsp recording works. Tested successfully with the cdrom channel
36 * (+) apm suspend/resume works, and works properly!.
37 * (-) hardware volme controls don't work =-(
38 * (-) setblocksize() does nothing.
40 * The real credit goes to:
42 * Zach Brown for his Linux driver core and helpful technical comments.
43 * <zab@zabbo.net>, http://www.zabbo.net/maestro3
45 * Cameron Grant created the pcm framework used here nearly verbatim.
46 * <cg@freebsd.org>, http://people.freebsd.org/~cg/template.c
48 * Taku YAMAMOTO for his Maestro-1/2 FreeBSD driver and sanity reference.
49 * <taku@cent.saitama-u.ac.jp>
51 * ESS docs explained a few magic registers and numbers.
52 * http://virgo.caltech.edu/~dmoore/maestro3.pdf.gz
55 #include <dev/sound/pcm/sound.h>
56 #include <dev/sound/pcm/ac97.h>
58 #include <dev/pci/pcireg.h>
59 #include <dev/pci/pcivar.h>
61 #include <gnu/dev/sound/pci/maestro3_reg.h>
62 #include <gnu/dev/sound/pci/maestro3_dsp.h>
64 SND_DECLARE_FILE("$FreeBSD$");
66 /* -------------------------------------------------------------------- */
68 enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1};
69 #ifndef M3_DEBUG_LEVEL
70 #define M3_DEBUG_LEVEL NONE
72 #define M3_DEBUG(level, _msg) {if ((level) <= M3_DEBUG_LEVEL) {printf _msg;}}
74 /* -------------------------------------------------------------------- */
80 static struct m3_card_type {
81 u_int32_t pci_id; int which; int delay1; int delay2; char *name;
83 { 0x1988125d, ESS_ALLEGRO_1, 50, 800, "ESS Technology Allegro-1" },
84 { 0x1998125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" },
85 { 0x199a125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" },
89 #define M3_BUFSIZE_MIN 4096
90 #define M3_BUFSIZE_MAX 65536
91 #define M3_BUFSIZE_DEFAULT 4096
92 #define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */
94 #define M3_MAXADDR ((1 << 27) - 1)
101 struct snd_dbuf *buffer;
102 struct pcm_channel *channel;
103 struct sc_info *parent;
115 struct snd_dbuf *buffer;
116 struct pcm_channel *channel;
117 struct sc_info *parent;
134 bus_space_handle_t sh;
135 bus_dma_tag_t parent_dmat;
137 struct resource *reg;
138 struct resource *irq;
144 struct sc_pchinfo pch[M3_PCHANS];
145 struct sc_rchinfo rch[M3_RCHANS];
155 #define M3_LOCK(_sc) snd_mtxlock((_sc)->sc_lock)
156 #define M3_UNLOCK(_sc) snd_mtxunlock((_sc)->sc_lock)
157 #define M3_LOCK_ASSERT(_sc) snd_mtxassert((_sc)->sc_lock)
159 /* -------------------------------------------------------------------- */
161 /* play channel interface */
162 static void *m3_pchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int);
163 static int m3_pchan_free(kobj_t, void *);
164 static int m3_pchan_setformat(kobj_t, void *, u_int32_t);
165 static int m3_pchan_setspeed(kobj_t, void *, u_int32_t);
166 static int m3_pchan_setblocksize(kobj_t, void *, u_int32_t);
167 static int m3_pchan_trigger(kobj_t, void *, int);
168 static int m3_pchan_trigger_locked(kobj_t, void *, int);
169 static u_int32_t m3_pchan_getptr_internal(struct sc_pchinfo *);
170 static u_int32_t m3_pchan_getptr(kobj_t, void *);
171 static struct pcmchan_caps *m3_pchan_getcaps(kobj_t, void *);
173 /* record channel interface */
174 static void *m3_rchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int);
175 static int m3_rchan_free(kobj_t, void *);
176 static int m3_rchan_setformat(kobj_t, void *, u_int32_t);
177 static int m3_rchan_setspeed(kobj_t, void *, u_int32_t);
178 static int m3_rchan_setblocksize(kobj_t, void *, u_int32_t);
179 static int m3_rchan_trigger(kobj_t, void *, int);
180 static int m3_rchan_trigger_locked(kobj_t, void *, int);
181 static u_int32_t m3_rchan_getptr_internal(struct sc_rchinfo *);
182 static u_int32_t m3_rchan_getptr(kobj_t, void *);
183 static struct pcmchan_caps *m3_rchan_getcaps(kobj_t, void *);
185 static int m3_chan_active(struct sc_info *);
187 /* talk to the codec - called from ac97.c */
188 static int m3_initcd(kobj_t, void *);
189 static int m3_rdcd(kobj_t, void *, int);
190 static int m3_wrcd(kobj_t, void *, int, u_int32_t);
193 static void m3_intr(void *);
194 static int m3_power(struct sc_info *, int);
195 static int m3_init(struct sc_info *);
196 static int m3_uninit(struct sc_info *);
197 static u_int8_t m3_assp_halt(struct sc_info *);
198 static void m3_config(struct sc_info *);
199 static void m3_amp_enable(struct sc_info *);
200 static void m3_enable_ints(struct sc_info *);
201 static void m3_codec_reset(struct sc_info *);
203 /* -------------------------------------------------------------------- */
204 /* Codec descriptor */
205 static kobj_method_t m3_codec_methods[] = {
206 KOBJMETHOD(ac97_init, m3_initcd),
207 KOBJMETHOD(ac97_read, m3_rdcd),
208 KOBJMETHOD(ac97_write, m3_wrcd),
211 AC97_DECLARE(m3_codec);
213 /* -------------------------------------------------------------------- */
214 /* channel descriptors */
216 static u_int32_t m3_playfmt[] = {
218 AFMT_STEREO | AFMT_U8,
220 AFMT_STEREO | AFMT_S16_LE,
223 static struct pcmchan_caps m3_playcaps = {8000, 48000, m3_playfmt, 0};
225 static kobj_method_t m3_pch_methods[] = {
226 KOBJMETHOD(channel_init, m3_pchan_init),
227 KOBJMETHOD(channel_setformat, m3_pchan_setformat),
228 KOBJMETHOD(channel_setspeed, m3_pchan_setspeed),
229 KOBJMETHOD(channel_setblocksize, m3_pchan_setblocksize),
230 KOBJMETHOD(channel_trigger, m3_pchan_trigger),
231 KOBJMETHOD(channel_getptr, m3_pchan_getptr),
232 KOBJMETHOD(channel_getcaps, m3_pchan_getcaps),
233 KOBJMETHOD(channel_free, m3_pchan_free),
236 CHANNEL_DECLARE(m3_pch);
238 static u_int32_t m3_recfmt[] = {
240 AFMT_STEREO | AFMT_U8,
242 AFMT_STEREO | AFMT_S16_LE,
245 static struct pcmchan_caps m3_reccaps = {8000, 48000, m3_recfmt, 0};
247 static kobj_method_t m3_rch_methods[] = {
248 KOBJMETHOD(channel_init, m3_rchan_init),
249 KOBJMETHOD(channel_setformat, m3_rchan_setformat),
250 KOBJMETHOD(channel_setspeed, m3_rchan_setspeed),
251 KOBJMETHOD(channel_setblocksize, m3_rchan_setblocksize),
252 KOBJMETHOD(channel_trigger, m3_rchan_trigger),
253 KOBJMETHOD(channel_getptr, m3_rchan_getptr),
254 KOBJMETHOD(channel_getcaps, m3_rchan_getcaps),
255 KOBJMETHOD(channel_free, m3_rchan_free),
258 CHANNEL_DECLARE(m3_rch);
260 /* -------------------------------------------------------------------- */
261 /* some i/o convenience functions */
263 #define m3_rd_1(sc, regno) bus_space_read_1(sc->st, sc->sh, regno)
264 #define m3_rd_2(sc, regno) bus_space_read_2(sc->st, sc->sh, regno)
265 #define m3_rd_4(sc, regno) bus_space_read_4(sc->st, sc->sh, regno)
266 #define m3_wr_1(sc, regno, data) bus_space_write_1(sc->st, sc->sh, regno, data)
267 #define m3_wr_2(sc, regno, data) bus_space_write_2(sc->st, sc->sh, regno, data)
268 #define m3_wr_4(sc, regno, data) bus_space_write_4(sc->st, sc->sh, regno, data)
269 #define m3_rd_assp_code(sc, index) \
270 m3_rd_assp(sc, MEMTYPE_INTERNAL_CODE, index)
271 #define m3_wr_assp_code(sc, index, data) \
272 m3_wr_assp(sc, MEMTYPE_INTERNAL_CODE, index, data)
273 #define m3_rd_assp_data(sc, index) \
274 m3_rd_assp(sc, MEMTYPE_INTERNAL_DATA, index)
275 #define m3_wr_assp_data(sc, index, data) \
276 m3_wr_assp(sc, MEMTYPE_INTERNAL_DATA, index, data)
278 static __inline u_int16_t
279 m3_rd_assp(struct sc_info *sc, u_int16_t region, u_int16_t index)
281 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
282 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
283 return m3_rd_2(sc, DSP_PORT_MEMORY_DATA);
287 m3_wr_assp(struct sc_info *sc, u_int16_t region, u_int16_t index,
290 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
291 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
292 m3_wr_2(sc, DSP_PORT_MEMORY_DATA, data);
296 m3_wait(struct sc_info *sc)
300 for (i=0 ; i<20 ; i++) {
301 if ((m3_rd_1(sc, CODEC_STATUS) & 1) == 0) {
309 /* -------------------------------------------------------------------- */
313 m3_initcd(kobj_t kobj, void *devinfo)
315 struct sc_info *sc = (struct sc_info *)devinfo;
318 M3_DEBUG(CALL, ("m3_initcd\n"));
322 data = m3_rd_1(sc, CODEC_COMMAND);
323 return ((data & 0x1) ? 0 : 1);
327 m3_rdcd(kobj_t kobj, void *devinfo, int regno)
329 struct sc_info *sc = (struct sc_info *)devinfo;
333 device_printf(sc->dev, "m3_rdcd timed out.\n");
336 m3_wr_1(sc, CODEC_COMMAND, (regno & 0x7f) | 0x80);
337 DELAY(50); /* ac97 cycle = 20.8 usec */
339 device_printf(sc->dev, "m3_rdcd timed out.\n");
342 data = m3_rd_2(sc, CODEC_DATA);
347 m3_wrcd(kobj_t kobj, void *devinfo, int regno, u_int32_t data)
349 struct sc_info *sc = (struct sc_info *)devinfo;
351 device_printf(sc->dev, "m3_wrcd timed out.\n");
354 m3_wr_2(sc, CODEC_DATA, data);
355 m3_wr_1(sc, CODEC_COMMAND, regno & 0x7f);
356 DELAY(50); /* ac97 cycle = 20.8 usec */
360 /* -------------------------------------------------------------------- */
361 /* play channel interface */
363 #define LO(x) (((x) & 0x0000ffff) )
364 #define HI(x) (((x) & 0xffff0000) >> 16)
367 m3_pchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
369 struct sc_info *sc = devinfo;
370 struct sc_pchinfo *ch;
371 u_int32_t bus_addr, i;
372 int idx, data_bytes, dac_data;
373 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
376 idx = sc->pch_cnt; /* dac instance number, no active reuse! */
377 M3_DEBUG(CHANGE, ("m3_pchan_init(dac=%d)\n", idx));
379 if (dir != PCMDIR_PLAY) {
381 device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n");
385 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) +
386 (MINISRC_IN_BUFFER_SIZE & ~1) +
387 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255;
388 dac_data = 0x1100 + (data_bytes * idx);
390 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
391 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
392 dsp_in_buf = dac_data + (MINISRC_TMP_BUFFER_SIZE/2);
393 dsp_out_buf = dsp_in_buf + (dsp_in_size/2) + 1;
397 ch->dac_data = dac_data;
398 if (ch->dac_data + data_bytes/2 >= 0x1c00) {
400 device_printf(sc->dev, "m3_pchan_init: revb mem exhausted\n");
408 ch->spd = DSP_DEFAULT_SPEED;
409 M3_UNLOCK(sc); /* XXX */
410 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
411 device_printf(sc->dev, "m3_pchan_init chn_allocbuf failed\n");
415 ch->bufsize = sndbuf_getsize(ch->buffer);
417 /* host dma buffer pointers */
418 bus_addr = sndbuf_getbufaddr(ch->buffer);
420 device_printf(sc->dev, "m3_pchan_init unaligned bus_addr\n");
421 bus_addr = (bus_addr + 4) & ~3;
423 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
424 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
425 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1L,
426 LO(bus_addr + ch->bufsize));
427 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1H,
428 HI(bus_addr + ch->bufsize));
429 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL,
431 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH,
435 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
436 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_END_PLUS_1,
437 dsp_in_buf + dsp_in_size/2);
438 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
439 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
440 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
441 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_END_PLUS_1,
442 dsp_out_buf + dsp_out_size/2);
443 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
444 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
446 /* some per client initializers */
447 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 12,
448 ch->dac_data + 40 + 8);
449 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 19,
450 0x400 + MINISRC_COEF_LOC);
451 /* enable or disable low pass filter? (0xff if rate> 45000) */
452 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 22, 0);
453 /* tell it which way dma is going? */
454 m3_wr_assp_data(sc, ch->dac_data + CDATA_DMA_CONTROL,
455 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR +
456 DMAC_BLOCKF_SELECTOR);
458 /* set an armload of static initializers */
459 for(i = 0 ; i < (sizeof(pv) / sizeof(pv[0])) ; i++) {
460 m3_wr_assp_data(sc, ch->dac_data + pv[i].addr, pv[i].val);
463 /* put us in the packed task lists */
464 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
465 (sc->pch_cnt + sc->rch_cnt),
466 ch->dac_data >> DP_SHIFT_COUNT);
467 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
468 ch->dac_data >> DP_SHIFT_COUNT);
469 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + sc->pch_cnt,
470 ch->dac_data >> DP_SHIFT_COUNT);
472 /* gotta start before stop */
473 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_START);
474 /* silence noise on load */
475 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_STOP);
484 m3_pchan_free(kobj_t kobj, void *chdata)
486 struct sc_pchinfo *ch = chdata;
487 struct sc_info *sc = ch->parent;
490 M3_DEBUG(CHANGE, ("m3_pchan_free(dac=%d)\n", ch->dac_idx));
493 * should remove this exact instance from the packed lists, but all
494 * are released at once (and in a stopped state) so this is ok.
496 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
497 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
498 m3_wr_assp_data(sc, KDATA_DMA_XFER0 +
499 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
500 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + (sc->pch_cnt-1), 0);
508 m3_pchan_setformat(kobj_t kobj, void *chdata, u_int32_t format)
510 struct sc_pchinfo *ch = chdata;
511 struct sc_info *sc = ch->parent;
516 ("m3_pchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
518 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit",
519 format & AFMT_STEREO ? "STEREO":"MONO"));
522 data = (format & AFMT_STEREO) ? 0 : 1;
523 m3_wr_assp_data(sc, ch->dac_data + SRC3_MODE_OFFSET, data);
526 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0;
527 m3_wr_assp_data(sc, ch->dac_data + SRC3_WORD_LENGTH_OFFSET, data);
536 m3_pchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed)
538 struct sc_pchinfo *ch = chdata;
539 struct sc_info *sc = ch->parent;
543 M3_DEBUG(CHANGE, ("m3_pchan_setspeed(dac=%d, speed=%d)\n",
544 ch->dac_idx, speed));
546 if ((freq = ((speed << 15) + 24000) / 48000) != 0) {
550 m3_wr_assp_data(sc, ch->dac_data + CDATA_FREQUENCY, freq);
554 /* return closest possible speed */
559 m3_pchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize)
561 struct sc_pchinfo *ch = chdata;
563 M3_DEBUG(CHANGE, ("m3_pchan_setblocksize(dac=%d, blocksize=%d)\n",
564 ch->dac_idx, blocksize));
566 return (sndbuf_getblksz(ch->buffer));
570 m3_pchan_trigger(kobj_t kobj, void *chdata, int go)
572 struct sc_pchinfo *ch = chdata;
573 struct sc_info *sc = ch->parent;
576 if (!PCMTRIG_COMMON(go))
580 ret = m3_pchan_trigger_locked(kobj, chdata, go);
587 m3_chan_active(struct sc_info *sc)
593 for (i = 0; i < sc->pch_cnt; i++)
594 ret += sc->pch[i].active;
596 for (i = 0; i < sc->rch_cnt; i++)
597 ret += sc->rch[i].active;
603 m3_pchan_trigger_locked(kobj_t kobj, void *chdata, int go)
605 struct sc_pchinfo *ch = chdata;
606 struct sc_info *sc = ch->parent;
610 M3_DEBUG(go == PCMTRIG_START ? CHANGE :
611 go == PCMTRIG_STOP ? CHANGE :
612 go == PCMTRIG_ABORT ? CHANGE :
614 ("m3_pchan_trigger(dac=%d, go=0x%x{%s})\n", ch->dac_idx, go,
615 go == PCMTRIG_START ? "PCMTRIG_START" :
616 go == PCMTRIG_STOP ? "PCMTRIG_STOP" :
617 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore"));
627 sc->pch_active_cnt++;
629 /*[[inc_timer_users]]*/
630 if (m3_chan_active(sc) == 1) {
631 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240);
632 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240);
633 data = m3_rd_2(sc, HOST_INT_CTRL);
634 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
637 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 1);
638 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER,
644 if (ch->active == 0) {
648 sc->pch_active_cnt--;
650 /* XXX should the channel be drained? */
651 /*[[dec_timer_users]]*/
652 if (m3_chan_active(sc) == 0) {
653 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0);
654 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0);
655 data = m3_rd_2(sc, HOST_INT_CTRL);
656 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);
659 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 0);
660 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER,
664 case PCMTRIG_EMLDMAWR:
665 /* got play irq, transfer next buffer - ignore if using dma */
666 case PCMTRIG_EMLDMARD:
667 /* got rec irq, transfer next buffer - ignore if using dma */
675 m3_pchan_getptr_internal(struct sc_pchinfo *ch)
677 struct sc_info *sc = ch->parent;
678 u_int32_t hi, lo, bus_base, bus_crnt;
680 bus_base = sndbuf_getbufaddr(ch->buffer);
681 hi = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH);
682 lo = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL);
683 bus_crnt = lo | (hi << 16);
685 M3_DEBUG(CALL, ("m3_pchan_getptr(dac=%d) result=%d\n",
686 ch->dac_idx, bus_crnt - bus_base));
688 return (bus_crnt - bus_base); /* current byte offset of channel */
692 m3_pchan_getptr(kobj_t kobj, void *chdata)
694 struct sc_pchinfo *ch = chdata;
695 struct sc_info *sc = ch->parent;
705 static struct pcmchan_caps *
706 m3_pchan_getcaps(kobj_t kobj, void *chdata)
708 struct sc_pchinfo *ch = chdata;
710 M3_DEBUG(CALL, ("m3_pchan_getcaps(dac=%d)\n", ch->dac_idx));
715 /* -------------------------------------------------------------------- */
716 /* rec channel interface */
719 m3_rchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
721 struct sc_info *sc = devinfo;
722 struct sc_rchinfo *ch;
723 u_int32_t bus_addr, i;
725 int idx, data_bytes, adc_data;
726 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
729 idx = sc->rch_cnt; /* adc instance number, no active reuse! */
730 M3_DEBUG(CHANGE, ("m3_rchan_init(adc=%d)\n", idx));
732 if (dir != PCMDIR_REC) {
734 device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n");
738 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) +
739 (MINISRC_IN_BUFFER_SIZE & ~1) +
740 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255;
741 adc_data = 0x1100 + (data_bytes * idx) + data_bytes/2;
742 dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2);
743 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
744 dsp_in_buf = adc_data + (MINISRC_TMP_BUFFER_SIZE / 2);
745 dsp_out_buf = dsp_in_buf + (dsp_in_size / 2) + 1;
749 ch->adc_data = adc_data;
750 if (ch->adc_data + data_bytes/2 >= 0x1c00) {
752 device_printf(sc->dev, "m3_rchan_init: revb mem exhausted\n");
760 ch->spd = DSP_DEFAULT_SPEED;
761 M3_UNLOCK(sc); /* XXX */
762 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
763 device_printf(sc->dev, "m3_rchan_init chn_allocbuf failed\n");
767 ch->bufsize = sndbuf_getsize(ch->buffer);
769 /* host dma buffer pointers */
770 bus_addr = sndbuf_getbufaddr(ch->buffer);
772 device_printf(sc->dev, "m3_rchan_init unaligned bus_addr\n");
773 bus_addr = (bus_addr + 4) & ~3;
775 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
776 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
777 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1L,
778 LO(bus_addr + ch->bufsize));
779 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1H,
780 HI(bus_addr + ch->bufsize));
781 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL,
783 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH,
787 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
788 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_END_PLUS_1,
789 dsp_in_buf + dsp_in_size/2);
790 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
791 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
792 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
793 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_END_PLUS_1,
794 dsp_out_buf + dsp_out_size/2);
795 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
796 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
798 /* some per client initializers */
799 m3_wr_assp_data(sc, ch->adc_data + SRC3_DIRECTION_OFFSET + 12,
800 ch->adc_data + 40 + 8);
801 m3_wr_assp_data(sc, ch->adc_data + CDATA_DMA_CONTROL,
802 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
803 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
805 /* set an armload of static initializers */
806 for(i = 0 ; i < (sizeof(rv) / sizeof(rv[0])) ; i++) {
807 m3_wr_assp_data(sc, ch->adc_data + rv[i].addr, rv[i].val);
810 /* put us in the packed task lists */
811 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
812 (sc->pch_cnt + sc->rch_cnt),
813 ch->adc_data >> DP_SHIFT_COUNT);
814 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
815 ch->adc_data >> DP_SHIFT_COUNT);
816 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + sc->rch_cnt,
817 ch->adc_data >> DP_SHIFT_COUNT);
819 /* gotta start before stop */
820 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_START);
822 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_STOP);
831 m3_rchan_free(kobj_t kobj, void *chdata)
833 struct sc_rchinfo *ch = chdata;
834 struct sc_info *sc = ch->parent;
837 M3_DEBUG(CHANGE, ("m3_rchan_free(adc=%d)\n", ch->adc_idx));
840 * should remove this exact instance from the packed lists, but all
841 * are released at once (and in a stopped state) so this is ok.
843 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
844 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
845 m3_wr_assp_data(sc, KDATA_DMA_XFER0 +
846 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
847 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + (sc->rch_cnt - 1), 0);
855 m3_rchan_setformat(kobj_t kobj, void *chdata, u_int32_t format)
857 struct sc_rchinfo *ch = chdata;
858 struct sc_info *sc = ch->parent;
863 ("m3_rchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
865 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit",
866 format & AFMT_STEREO ? "STEREO":"MONO"));
869 data = (format & AFMT_STEREO) ? 0 : 1;
870 m3_wr_assp_data(sc, ch->adc_data + SRC3_MODE_OFFSET, data);
873 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0;
874 m3_wr_assp_data(sc, ch->adc_data + SRC3_WORD_LENGTH_OFFSET, data);
882 m3_rchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed)
884 struct sc_rchinfo *ch = chdata;
885 struct sc_info *sc = ch->parent;
889 M3_DEBUG(CHANGE, ("m3_rchan_setspeed(adc=%d, speed=%d)\n",
890 ch->adc_idx, speed));
892 if ((freq = ((speed << 15) + 24000) / 48000) != 0) {
896 m3_wr_assp_data(sc, ch->adc_data + CDATA_FREQUENCY, freq);
900 /* return closest possible speed */
905 m3_rchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize)
907 struct sc_rchinfo *ch = chdata;
909 M3_DEBUG(CHANGE, ("m3_rchan_setblocksize(adc=%d, blocksize=%d)\n",
910 ch->adc_idx, blocksize));
912 return (sndbuf_getblksz(ch->buffer));
916 m3_rchan_trigger(kobj_t kobj, void *chdata, int go)
918 struct sc_rchinfo *ch = chdata;
919 struct sc_info *sc = ch->parent;
922 if (!PCMTRIG_COMMON(go))
926 ret = m3_rchan_trigger_locked(kobj, chdata, go);
933 m3_rchan_trigger_locked(kobj_t kobj, void *chdata, int go)
935 struct sc_rchinfo *ch = chdata;
936 struct sc_info *sc = ch->parent;
940 M3_DEBUG(go == PCMTRIG_START ? CHANGE :
941 go == PCMTRIG_STOP ? CHANGE :
942 go == PCMTRIG_ABORT ? CHANGE :
944 ("m3_rchan_trigger(adc=%d, go=0x%x{%s})\n", ch->adc_idx, go,
945 go == PCMTRIG_START ? "PCMTRIG_START" :
946 go == PCMTRIG_STOP ? "PCMTRIG_STOP" :
947 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore"));
958 /*[[inc_timer_users]]*/
959 if (m3_chan_active(sc) == 1) {
960 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240);
961 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240);
962 data = m3_rd_2(sc, HOST_INT_CTRL);
963 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
966 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 1);
967 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 1);
972 if (ch->active == 0) {
977 /*[[dec_timer_users]]*/
978 if (m3_chan_active(sc) == 0) {
979 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0);
980 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0);
981 data = m3_rd_2(sc, HOST_INT_CTRL);
982 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);
985 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 0);
986 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 0);
989 case PCMTRIG_EMLDMAWR:
990 /* got play irq, transfer next buffer - ignore if using dma */
991 case PCMTRIG_EMLDMARD:
992 /* got rec irq, transfer next buffer - ignore if using dma */
1000 m3_rchan_getptr_internal(struct sc_rchinfo *ch)
1002 struct sc_info *sc = ch->parent;
1003 u_int32_t hi, lo, bus_base, bus_crnt;
1005 bus_base = sndbuf_getbufaddr(ch->buffer);
1006 hi = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH);
1007 lo = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL);
1008 bus_crnt = lo | (hi << 16);
1010 M3_DEBUG(CALL, ("m3_rchan_getptr(adc=%d) result=%d\n",
1011 ch->adc_idx, bus_crnt - bus_base));
1013 return (bus_crnt - bus_base); /* current byte offset of channel */
1017 m3_rchan_getptr(kobj_t kobj, void *chdata)
1019 struct sc_rchinfo *ch = chdata;
1020 struct sc_info *sc = ch->parent;
1030 static struct pcmchan_caps *
1031 m3_rchan_getcaps(kobj_t kobj, void *chdata)
1033 struct sc_rchinfo *ch = chdata;
1035 M3_DEBUG(CALL, ("m3_rchan_getcaps(adc=%d)\n", ch->adc_idx));
1040 /* -------------------------------------------------------------------- */
1041 /* The interrupt handler */
1046 struct sc_info *sc = (struct sc_info *)p;
1047 struct sc_pchinfo *pch;
1048 struct sc_rchinfo *rch;
1049 u_int32_t status, ctl, i, delta;
1051 M3_DEBUG(INTR, ("m3_intr\n"));
1054 status = m3_rd_1(sc, HOST_INT_STATUS);
1060 m3_wr_1(sc, HOST_INT_STATUS, 0xff); /* ack the int? */
1062 if (status & HV_INT_PENDING) {
1065 event = m3_rd_1(sc, HW_VOL_COUNTER_MASTER);
1068 mixer_hwvol_mute(sc->dev);
1071 mixer_hwvol_step(sc->dev, 1, 1);
1074 mixer_hwvol_step(sc->dev, -1, -1);
1079 device_printf(sc->dev, "Unknown HWVOL event\n");
1081 m3_wr_1(sc, HW_VOL_COUNTER_MASTER, 0x88);
1085 if (status & ASSP_INT_PENDING) {
1086 ctl = m3_rd_1(sc, ASSP_CONTROL_B);
1087 if (!(ctl & STOP_ASSP_CLOCK)) {
1088 ctl = m3_rd_1(sc, ASSP_HOST_INT_STATUS);
1089 if (ctl & DSP2HOST_REQ_TIMER) {
1090 m3_wr_1(sc, ASSP_HOST_INT_STATUS,
1091 DSP2HOST_REQ_TIMER);
1092 /*[[ess_update_ptr]]*/
1093 goto m3_handle_channel_intr;
1098 goto m3_handle_channel_intr_out;
1100 m3_handle_channel_intr:
1101 for (i=0 ; i<sc->pch_cnt ; i++) {
1104 pch->ptr = m3_pchan_getptr_internal(pch);
1105 delta = pch->bufsize + pch->ptr - pch->prevptr;
1106 delta %= pch->bufsize;
1107 if (delta < sndbuf_getblksz(pch->buffer))
1109 pch->prevptr = pch->ptr;
1111 chn_intr(pch->channel);
1115 for (i=0 ; i<sc->rch_cnt ; i++) {
1118 rch->ptr = m3_rchan_getptr_internal(rch);
1119 delta = rch->bufsize + rch->ptr - rch->prevptr;
1120 delta %= rch->bufsize;
1121 if (delta < sndbuf_getblksz(rch->buffer))
1123 rch->prevptr = rch->ptr;
1125 chn_intr(rch->channel);
1130 m3_handle_channel_intr_out:
1134 /* -------------------------------------------------------------------- */
1138 m3_power(struct sc_info *sc, int state)
1142 M3_DEBUG(CHANGE, ("m3_power(%d)\n", state));
1145 data = pci_read_config(sc->dev, 0x34, 1);
1146 if (pci_read_config(sc->dev, data, 1) == 1) {
1147 pci_write_config(sc->dev, data + 4, state, 1);
1154 m3_init(struct sc_info *sc)
1156 u_int32_t data, i, size;
1157 u_int8_t reset_state;
1160 M3_DEBUG(CHANGE, ("m3_init\n"));
1162 /* diable legacy emulations. */
1163 data = pci_read_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, 2);
1164 data |= DISABLE_LEGACY;
1165 pci_write_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, data, 2);
1169 reset_state = m3_assp_halt(sc);
1173 /* [m3_assp_init] */
1174 /* zero kernel data */
1175 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1176 for(i = 0 ; i < size / 2 ; i++) {
1177 m3_wr_assp_data(sc, KDATA_BASE_ADDR + i, 0);
1179 /* zero mixer data? */
1180 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1181 for(i = 0 ; i < size / 2 ; i++) {
1182 m3_wr_assp_data(sc, KDATA_BASE_ADDR2 + i, 0);
1184 /* init dma pointer */
1185 m3_wr_assp_data(sc, KDATA_CURRENT_DMA,
1187 /* write kernel into code memory */
1188 size = sizeof(assp_kernel_image);
1189 for(i = 0 ; i < size / 2; i++) {
1190 m3_wr_assp_code(sc, REV_B_CODE_MEMORY_BEGIN + i,
1191 assp_kernel_image[i]);
1194 * We only have this one client and we know that 0x400 is free in
1195 * our kernel's mem map, so lets just drop it there. It seems that
1196 * the minisrc doesn't need vectors, so we won't bother with them..
1198 size = sizeof(assp_minisrc_image);
1199 for(i = 0 ; i < size / 2; i++) {
1200 m3_wr_assp_code(sc, 0x400 + i, assp_minisrc_image[i]);
1202 /* write the coefficients for the low pass filter? */
1203 size = sizeof(minisrc_lpf_image);
1204 for(i = 0; i < size / 2 ; i++) {
1205 m3_wr_assp_code(sc,0x400 + MINISRC_COEF_LOC + i,
1206 minisrc_lpf_image[i]);
1208 m3_wr_assp_code(sc, 0x400 + MINISRC_COEF_LOC + size, 0x8000);
1209 /* the minisrc is the only thing on our task list */
1210 m3_wr_assp_data(sc, KDATA_TASK0, 0x400);
1211 /* init the mixer number */
1212 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 0);
1213 /* extreme kernel master volume */
1214 m3_wr_assp_data(sc, KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
1215 m3_wr_assp_data(sc, KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
1219 /* [m3_assp_client_init] (only one client at index 0) */
1220 for (i=0x1100 ; i<0x1c00 ; i++) {
1221 m3_wr_assp_data(sc, i, 0); /* zero entire dac/adc area */
1224 /* [m3_assp_continue] */
1225 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
1231 m3_uninit(struct sc_info *sc)
1233 M3_DEBUG(CHANGE, ("m3_uninit\n"));
1237 /* -------------------------------------------------------------------- */
1238 /* Probe and attach the card */
1241 m3_pci_probe(device_t dev)
1243 struct m3_card_type *card;
1245 M3_DEBUG(CALL, ("m3_pci_probe(0x%x)\n", pci_get_devid(dev)));
1247 for (card = m3_card_types ; card->pci_id ; card++) {
1248 if (pci_get_devid(dev) == card->pci_id) {
1249 device_set_desc(dev, card->name);
1250 return BUS_PROBE_DEFAULT;
1257 m3_pci_attach(device_t dev)
1260 struct ac97_info *codec = NULL;
1262 char status[SND_STATUSLEN];
1263 struct m3_card_type *card;
1264 int i, len, dacn, adcn;
1266 M3_DEBUG(CALL, ("m3_pci_attach\n"));
1268 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
1270 sc->type = pci_get_devid(dev);
1271 sc->sc_lock = snd_mtxcreate(device_get_nameunit(dev),
1272 "snd_maestro3 softc");
1273 for (card = m3_card_types ; card->pci_id ; card++) {
1274 if (sc->type == card->pci_id) {
1275 sc->which = card->which;
1276 sc->delay1 = card->delay1;
1277 sc->delay2 = card->delay2;
1282 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
1286 else if (i > M3_PCHANS)
1295 data = pci_read_config(dev, PCIR_COMMAND, 2);
1296 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
1297 pci_write_config(dev, PCIR_COMMAND, data, 2);
1299 sc->regid = PCIR_BAR(0);
1300 sc->regtype = SYS_RES_MEMORY;
1301 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
1304 sc->regtype = SYS_RES_IOPORT;
1305 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
1309 device_printf(dev, "unable to allocate register space\n");
1312 sc->st = rman_get_bustag(sc->reg);
1313 sc->sh = rman_get_bushandle(sc->reg);
1316 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
1317 RF_ACTIVE | RF_SHAREABLE);
1319 device_printf(dev, "unable to allocate interrupt\n");
1323 if (snd_setup_intr(dev, sc->irq, INTR_MPSAFE, m3_intr, sc, &sc->ih)) {
1324 device_printf(dev, "unable to setup interrupt\n");
1328 sc->bufsz = pcm_getbuffersize(dev, M3_BUFSIZE_MIN, M3_BUFSIZE_DEFAULT,
1331 if (bus_dma_tag_create(
1332 bus_get_dma_tag(dev), /* parent */
1333 2, 0, /* alignment, boundary */
1334 M3_MAXADDR, /* lowaddr */
1335 BUS_SPACE_MAXADDR, /* highaddr */
1336 NULL, NULL, /* filtfunc, filtfuncarg */
1337 sc->bufsz, /* maxsize */
1339 0x3ffff, /* maxsegz */
1341 NULL, /* lockfunc */
1342 NULL, /* lockfuncarg */
1343 &sc->parent_dmat) != 0) {
1344 device_printf(dev, "unable to create dma tag\n");
1349 m3_power(sc, 0); /* power up */
1354 device_printf(dev, "unable to initialize the card\n");
1358 /* create/init mixer */
1359 codec = AC97_CREATE(dev, sc, m3_codec);
1360 if (codec == NULL) {
1361 device_printf(dev, "ac97_create error\n");
1364 if (mixer_init(dev, ac97_getmixerclass(), codec)) {
1365 device_printf(dev, "mixer_init error\n");
1371 if (pcm_register(dev, sc, dacn, adcn)) {
1372 device_printf(dev, "pcm_register error\n");
1375 for (i=0 ; i<dacn ; i++) {
1376 if (pcm_addchan(dev, PCMDIR_PLAY, &m3_pch_class, sc)) {
1377 device_printf(dev, "pcm_addchan (play) error\n");
1381 for (i=0 ; i<adcn ; i++) {
1382 if (pcm_addchan(dev, PCMDIR_REC, &m3_rch_class, sc)) {
1383 device_printf(dev, "pcm_addchan (rec) error\n");
1387 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s",
1388 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
1389 rman_get_start(sc->reg), rman_get_start(sc->irq),
1390 PCM_KLDSTRING(snd_maestro3));
1391 if (pcm_setstatus(dev, status)) {
1392 device_printf(dev, "attach: pcm_setstatus error\n");
1396 mixer_hwvol_init(dev);
1398 /* Create the buffer for saving the card state during suspend */
1399 len = sizeof(u_int16_t) * (REV_B_CODE_MEMORY_LENGTH +
1400 REV_B_DATA_MEMORY_LENGTH);
1401 sc->savemem = (u_int16_t*)malloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1407 ac97_destroy(codec);
1409 bus_teardown_intr(dev, sc->irq, sc->ih);
1411 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1413 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1414 if (sc->parent_dmat)
1415 bus_dma_tag_destroy(sc->parent_dmat);
1417 snd_mtxfree(sc->sc_lock);
1423 m3_pci_detach(device_t dev)
1425 struct sc_info *sc = pcm_getdevinfo(dev);
1428 M3_DEBUG(CALL, ("m3_pci_detach\n"));
1430 if ((r = pcm_unregister(dev)) != 0) {
1435 m3_uninit(sc); /* shutdown chip */
1436 m3_power(sc, 3); /* power off */
1439 bus_teardown_intr(dev, sc->irq, sc->ih);
1440 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1441 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1442 bus_dma_tag_destroy(sc->parent_dmat);
1444 free(sc->savemem, M_DEVBUF);
1445 snd_mtxfree(sc->sc_lock);
1451 m3_pci_suspend(device_t dev)
1453 struct sc_info *sc = pcm_getdevinfo(dev);
1456 M3_DEBUG(CHANGE, ("m3_pci_suspend\n"));
1459 for (i=0 ; i<sc->pch_cnt ; i++) {
1460 if (sc->pch[i].active) {
1461 m3_pchan_trigger_locked(NULL, &sc->pch[i],
1465 for (i=0 ; i<sc->rch_cnt ; i++) {
1466 if (sc->rch[i].active) {
1467 m3_rchan_trigger_locked(NULL, &sc->rch[i],
1471 DELAY(10 * 1000); /* give things a chance to stop */
1473 /* Disable interrupts */
1474 m3_wr_2(sc, HOST_INT_CTRL, 0);
1475 m3_wr_1(sc, ASSP_CONTROL_C, 0);
1479 /* Save the state of the ASSP */
1480 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
1481 sc->savemem[index++] = m3_rd_assp_code(sc, i);
1482 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++)
1483 sc->savemem[index++] = m3_rd_assp_data(sc, i);
1485 /* Power down the card to D3 state */
1493 m3_pci_resume(device_t dev)
1495 struct sc_info *sc = pcm_getdevinfo(dev);
1497 u_int8_t reset_state;
1499 M3_DEBUG(CHANGE, ("m3_pci_resume\n"));
1502 /* Power the card back to D0 */
1507 reset_state = m3_assp_halt(sc);
1511 /* Restore the ASSP state */
1512 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
1513 m3_wr_assp_code(sc, i, sc->savemem[index++]);
1514 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++)
1515 m3_wr_assp_data(sc, i, sc->savemem[index++]);
1517 /* Restart the DMA engine */
1518 m3_wr_assp_data(sc, KDATA_DMA_ACTIVE, 0);
1520 /* [m3_assp_continue] */
1521 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
1527 M3_UNLOCK(sc); /* XXX */
1528 if (mixer_reinit(dev) == -1) {
1529 device_printf(dev, "unable to reinitialize the mixer\n");
1534 /* Turn the channels back on */
1535 for (i=0 ; i<sc->pch_cnt ; i++) {
1536 if (sc->pch[i].active) {
1537 m3_pchan_trigger_locked(NULL, &sc->pch[i],
1541 for (i=0 ; i<sc->rch_cnt ; i++) {
1542 if (sc->rch[i].active) {
1543 m3_rchan_trigger_locked(NULL, &sc->rch[i],
1553 m3_pci_shutdown(device_t dev)
1555 struct sc_info *sc = pcm_getdevinfo(dev);
1557 M3_DEBUG(CALL, ("m3_pci_shutdown\n"));
1560 m3_power(sc, 3); /* power off */
1567 m3_assp_halt(struct sc_info *sc)
1569 u_int8_t data, reset_state;
1573 data = m3_rd_1(sc, DSP_PORT_CONTROL_REG_B);
1574 reset_state = data & ~REGB_STOP_CLOCK; /* remember for continue */
1576 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state & ~REGB_ENABLE_RESET);
1577 DELAY(10 * 1000); /* necessary? */
1583 m3_config(struct sc_info *sc)
1585 u_int32_t data, hv_cfg;
1592 * The volume buttons can be wired up via two different sets of pins.
1593 * This presents a problem since we can't tell which way it's
1594 * configured. Allow the user to set a hint in order to twiddle
1597 if (resource_int_value(device_get_name(sc->dev),
1598 device_get_unit(sc->dev),
1599 "hwvol_config", &hint) == 0)
1600 hv_cfg = (hint > 0) ? HV_BUTTON_FROM_GD : 0;
1602 hv_cfg = HV_BUTTON_FROM_GD;
1605 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1606 data &= ~HV_BUTTON_FROM_GD;
1607 data |= REDUCED_DEBOUNCE | HV_CTRL_ENABLE | hv_cfg;
1608 data |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
1609 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1611 m3_wr_1(sc, ASSP_CONTROL_B, RESET_ASSP);
1612 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1613 data &= ~INT_CLK_SELECT;
1614 if (sc->which == ESS_MAESTRO3) {
1615 data &= ~INT_CLK_MULT_ENABLE;
1616 data |= INT_CLK_SRC_NOT_PCI;
1618 data &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2);
1619 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1621 if (sc->which == ESS_ALLEGRO_1) {
1622 data = pci_read_config(sc->dev, PCI_USER_CONFIG, 4);
1623 data |= IN_CLK_12MHZ_SELECT;
1624 pci_write_config(sc->dev, PCI_USER_CONFIG, data, 4);
1627 data = m3_rd_1(sc, ASSP_CONTROL_A);
1628 data &= ~(DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
1629 data |= ASSP_CLK_49MHZ_SELECT; /*XXX assumes 49MHZ dsp XXX*/
1630 data |= ASSP_0_WS_ENABLE;
1631 m3_wr_1(sc, ASSP_CONTROL_A, data);
1633 m3_wr_1(sc, ASSP_CONTROL_B, RUN_ASSP);
1637 m3_enable_ints(struct sc_info *sc)
1641 m3_wr_2(sc, HOST_INT_CTRL, ASSP_INT_ENABLE | HV_INT_ENABLE);
1642 data = m3_rd_1(sc, ASSP_CONTROL_C);
1643 m3_wr_1(sc, ASSP_CONTROL_C, data | ASSP_HOST_INT_ENABLE);
1647 m3_amp_enable(struct sc_info *sc)
1649 u_int32_t gpo, polarity_port, polarity;
1654 switch (sc->which) {
1656 polarity_port = 0x1800;
1659 polarity_port = 0x1100;
1662 panic("bad sc->which");
1664 gpo = (polarity_port >> 8) & 0x0f;
1665 polarity = polarity_port >> 12;
1666 polarity = !polarity; /* enable */
1667 polarity = polarity << gpo;
1669 m3_wr_2(sc, GPIO_MASK, ~gpo);
1670 data = m3_rd_2(sc, GPIO_DIRECTION);
1671 m3_wr_2(sc, GPIO_DIRECTION, data | gpo);
1672 data = GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity;
1673 m3_wr_2(sc, GPIO_DATA, data);
1674 m3_wr_2(sc, GPIO_MASK, ~0);
1678 m3_codec_reset(struct sc_info *sc)
1680 u_int16_t data, dir;
1685 data = m3_rd_2(sc, GPIO_DIRECTION);
1686 dir = data | 0x10; /* assuming pci bus master? */
1688 /* [[remote_codec_config]] */
1689 data = m3_rd_2(sc, RING_BUS_CTRL_B);
1690 m3_wr_2(sc, RING_BUS_CTRL_B, data & ~SECOND_CODEC_ID_MASK);
1691 data = m3_rd_2(sc, SDO_OUT_DEST_CTRL);
1692 m3_wr_2(sc, SDO_OUT_DEST_CTRL, data & ~COMMAND_ADDR_OUT);
1693 data = m3_rd_2(sc, SDO_IN_DEST_CTRL);
1694 m3_wr_2(sc, SDO_IN_DEST_CTRL, data & ~STATUS_ADDR_IN);
1696 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE);
1699 m3_wr_2(sc, GPIO_DIRECTION, dir & ~GPO_PRIMARY_AC97);
1700 m3_wr_2(sc, GPIO_MASK, ~GPO_PRIMARY_AC97);
1701 m3_wr_2(sc, GPIO_DATA, 0);
1702 m3_wr_2(sc, GPIO_DIRECTION, dir | GPO_PRIMARY_AC97);
1703 DELAY(sc->delay1 * 1000); /*delay1 (ALLEGRO:50, MAESTRO3:20)*/
1704 m3_wr_2(sc, GPIO_DATA, GPO_PRIMARY_AC97);
1706 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE |
1707 SERIAL_AC_LINK_ENABLE);
1708 m3_wr_2(sc, GPIO_MASK, ~0);
1709 DELAY(sc->delay2 * 1000); /*delay2 (ALLEGRO:800, MAESTRO3:500)*/
1711 /* [[try read vendor]] */
1712 data = m3_rdcd(NULL, sc, 0x7c);
1713 if ((data == 0) || (data == 0xffff)) {
1716 device_printf(sc->dev, "Codec reset failed\n");
1719 device_printf(sc->dev, "Codec reset retry\n");
1724 static device_method_t m3_methods[] = {
1725 DEVMETHOD(device_probe, m3_pci_probe),
1726 DEVMETHOD(device_attach, m3_pci_attach),
1727 DEVMETHOD(device_detach, m3_pci_detach),
1728 DEVMETHOD(device_suspend, m3_pci_suspend),
1729 DEVMETHOD(device_resume, m3_pci_resume),
1730 DEVMETHOD(device_shutdown, m3_pci_shutdown),
1734 static driver_t m3_driver = {
1740 DRIVER_MODULE(snd_maestro3, pci, m3_driver, pcm_devclass, 0, 0);
1741 MODULE_DEPEND(snd_maestro3, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1742 MODULE_VERSION(snd_maestro3, 1);