2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <machine/bus.h>
36 #include <dev/uart/uart.h>
37 #include <dev/uart/uart_cpu.h>
38 #include <dev/uart/uart_bus.h>
40 #include <dev/ic/ns16550.h>
44 #define DEFAULT_RCLK 1843200
47 * Clear pending interrupts. THRE is cleared by reading IIR. Data
48 * that may have been received gets lost here.
51 ns8250_clrint(struct uart_bas *bas)
55 iir = uart_getreg(bas, REG_IIR);
56 while ((iir & IIR_NOPEND) == 0) {
59 (void)uart_getreg(bas, REG_LSR);
60 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
61 (void)uart_getreg(bas, REG_DATA);
62 else if (iir == IIR_MLSC)
63 (void)uart_getreg(bas, REG_MSR);
65 iir = uart_getreg(bas, REG_IIR);
70 ns8250_delay(struct uart_bas *bas)
75 lcr = uart_getreg(bas, REG_LCR);
76 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
78 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
80 uart_setreg(bas, REG_LCR, lcr);
83 /* 1/10th the time to transmit 1 character (estimate). */
85 return (16000000 * divisor / bas->rclk);
86 return (16000 * divisor / (bas->rclk / 1000));
90 ns8250_divisor(int rclk, int baudrate)
92 int actual_baud, divisor;
98 divisor = (rclk / (baudrate << 3) + 1) >> 1;
99 if (divisor == 0 || divisor >= 65536)
101 actual_baud = rclk / (divisor << 4);
103 /* 10 times error in percent: */
104 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
106 /* 3.0% maximum error tolerance: */
107 if (error < -30 || error > 30)
114 ns8250_drain(struct uart_bas *bas, int what)
118 delay = ns8250_delay(bas);
120 if (what & UART_DRAIN_TRANSMITTER) {
122 * Pick an arbitrary high limit to avoid getting stuck in
123 * an infinite loop when the hardware is broken. Make the
124 * limit high enough to handle large FIFOs.
127 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
130 /* printf("ns8250: transmitter appears stuck... "); */
135 if (what & UART_DRAIN_RECEIVER) {
137 * Pick an arbitrary high limit to avoid getting stuck in
138 * an infinite loop when the hardware is broken. Make the
139 * limit high enough to handle large FIFOs and integrated
140 * UARTs. The HP rx2600 for example has 3 UARTs on the
141 * management board that tend to get a lot of data send
142 * to it when the UART is first activated.
145 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
146 (void)uart_getreg(bas, REG_DATA);
151 /* printf("ns8250: receiver appears broken... "); */
160 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
161 * drained. WARNING: this function clobbers the FIFO setting!
164 ns8250_flush(struct uart_bas *bas, int what)
169 if (what & UART_FLUSH_TRANSMITTER)
171 if (what & UART_FLUSH_RECEIVER)
173 uart_setreg(bas, REG_FCR, fcr);
178 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
187 else if (databits == 7)
189 else if (databits == 6)
199 divisor = ns8250_divisor(bas->rclk, baudrate);
202 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
204 uart_setreg(bas, REG_DLL, divisor & 0xff);
205 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
209 /* Set LCR and clear DLAB. */
210 uart_setreg(bas, REG_LCR, lcr);
216 * Low-level UART interface.
218 static int ns8250_probe(struct uart_bas *bas);
219 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
220 static void ns8250_term(struct uart_bas *bas);
221 static void ns8250_putc(struct uart_bas *bas, int);
222 static int ns8250_rxready(struct uart_bas *bas);
223 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
225 static struct uart_ops uart_ns8250_ops = {
226 .probe = ns8250_probe,
230 .rxready = ns8250_rxready,
235 ns8250_probe(struct uart_bas *bas)
239 /* Check known 0 bits that don't depend on DLAB. */
240 val = uart_getreg(bas, REG_IIR);
243 val = uart_getreg(bas, REG_MCR);
251 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
257 bas->rclk = DEFAULT_RCLK;
258 ns8250_param(bas, baudrate, databits, stopbits, parity);
260 /* Disable all interrupt sources. */
261 ier = uart_getreg(bas, REG_IER) & 0xf0;
262 uart_setreg(bas, REG_IER, ier);
265 /* Disable the FIFO (if present). */
266 uart_setreg(bas, REG_FCR, 0);
270 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
277 ns8250_term(struct uart_bas *bas)
280 /* Clear RTS & DTR. */
281 uart_setreg(bas, REG_MCR, MCR_IE);
286 ns8250_putc(struct uart_bas *bas, int c)
291 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
293 uart_setreg(bas, REG_DATA, c);
296 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
301 ns8250_rxready(struct uart_bas *bas)
304 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
308 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
314 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
320 c = uart_getreg(bas, REG_DATA);
328 * High-level UART interface.
330 struct ns8250_softc {
331 struct uart_softc base;
337 static int ns8250_bus_attach(struct uart_softc *);
338 static int ns8250_bus_detach(struct uart_softc *);
339 static int ns8250_bus_flush(struct uart_softc *, int);
340 static int ns8250_bus_getsig(struct uart_softc *);
341 static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
342 static int ns8250_bus_ipend(struct uart_softc *);
343 static int ns8250_bus_param(struct uart_softc *, int, int, int, int);
344 static int ns8250_bus_probe(struct uart_softc *);
345 static int ns8250_bus_receive(struct uart_softc *);
346 static int ns8250_bus_setsig(struct uart_softc *, int);
347 static int ns8250_bus_transmit(struct uart_softc *);
349 static kobj_method_t ns8250_methods[] = {
350 KOBJMETHOD(uart_attach, ns8250_bus_attach),
351 KOBJMETHOD(uart_detach, ns8250_bus_detach),
352 KOBJMETHOD(uart_flush, ns8250_bus_flush),
353 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
354 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
355 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
356 KOBJMETHOD(uart_param, ns8250_bus_param),
357 KOBJMETHOD(uart_probe, ns8250_bus_probe),
358 KOBJMETHOD(uart_receive, ns8250_bus_receive),
359 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
360 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
364 struct uart_class uart_ns8250_class = {
367 sizeof(struct ns8250_softc),
368 .uc_ops = &uart_ns8250_ops,
370 .uc_rclk = DEFAULT_RCLK
373 #define SIGCHG(c, i, s, d) \
375 i |= (i & s) ? s : s | d; \
377 i = (i & s) ? (i & ~s) | d : i; \
381 ns8250_bus_attach(struct uart_softc *sc)
383 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
384 struct uart_bas *bas;
389 ns8250->mcr = uart_getreg(bas, REG_MCR);
390 ns8250->fcr = FCR_ENABLE;
391 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
393 if (UART_FLAGS_FCR_RX_LOW(ivar))
394 ns8250->fcr |= FCR_RX_LOW;
395 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
396 ns8250->fcr |= FCR_RX_MEDL;
397 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
398 ns8250->fcr |= FCR_RX_HIGH;
400 ns8250->fcr |= FCR_RX_MEDH;
402 ns8250->fcr |= FCR_RX_MEDH;
403 uart_setreg(bas, REG_FCR, ns8250->fcr);
405 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
407 if (ns8250->mcr & MCR_DTR)
408 sc->sc_hwsig |= SER_DTR;
409 if (ns8250->mcr & MCR_RTS)
410 sc->sc_hwsig |= SER_RTS;
411 ns8250_bus_getsig(sc);
414 ns8250->ier = uart_getreg(bas, REG_IER) & 0xf0;
415 ns8250->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY;
416 uart_setreg(bas, REG_IER, ns8250->ier);
422 ns8250_bus_detach(struct uart_softc *sc)
424 struct uart_bas *bas;
428 ier = uart_getreg(bas, REG_IER) & 0xf0;
429 uart_setreg(bas, REG_IER, ier);
436 ns8250_bus_flush(struct uart_softc *sc, int what)
438 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
439 struct uart_bas *bas;
443 uart_lock(sc->sc_hwmtx);
444 if (sc->sc_rxfifosz > 1) {
445 ns8250_flush(bas, what);
446 uart_setreg(bas, REG_FCR, ns8250->fcr);
450 error = ns8250_drain(bas, what);
451 uart_unlock(sc->sc_hwmtx);
456 ns8250_bus_getsig(struct uart_softc *sc)
458 uint32_t new, old, sig;
464 uart_lock(sc->sc_hwmtx);
465 msr = uart_getreg(&sc->sc_bas, REG_MSR);
466 uart_unlock(sc->sc_hwmtx);
467 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
468 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
469 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
470 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
471 new = sig & ~SER_MASK_DELTA;
472 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
477 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
479 struct uart_bas *bas;
480 int baudrate, divisor, error;
485 uart_lock(sc->sc_hwmtx);
487 case UART_IOCTL_BREAK:
488 lcr = uart_getreg(bas, REG_LCR);
493 uart_setreg(bas, REG_LCR, lcr);
496 case UART_IOCTL_IFLOW:
497 lcr = uart_getreg(bas, REG_LCR);
499 uart_setreg(bas, REG_LCR, 0xbf);
501 efr = uart_getreg(bas, REG_EFR);
506 uart_setreg(bas, REG_EFR, efr);
508 uart_setreg(bas, REG_LCR, lcr);
511 case UART_IOCTL_OFLOW:
512 lcr = uart_getreg(bas, REG_LCR);
514 uart_setreg(bas, REG_LCR, 0xbf);
516 efr = uart_getreg(bas, REG_EFR);
521 uart_setreg(bas, REG_EFR, efr);
523 uart_setreg(bas, REG_LCR, lcr);
526 case UART_IOCTL_BAUD:
527 lcr = uart_getreg(bas, REG_LCR);
528 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
530 divisor = uart_getreg(bas, REG_DLL) |
531 (uart_getreg(bas, REG_DLH) << 8);
533 uart_setreg(bas, REG_LCR, lcr);
535 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
537 *(int*)data = baudrate;
545 uart_unlock(sc->sc_hwmtx);
550 ns8250_bus_ipend(struct uart_softc *sc)
552 struct uart_bas *bas;
557 uart_lock(sc->sc_hwmtx);
558 iir = uart_getreg(bas, REG_IIR);
559 if (iir & IIR_NOPEND) {
560 uart_unlock(sc->sc_hwmtx);
564 if (iir & IIR_RXRDY) {
565 lsr = uart_getreg(bas, REG_LSR);
566 uart_unlock(sc->sc_hwmtx);
568 ipend |= SER_INT_OVERRUN;
570 ipend |= SER_INT_BREAK;
572 ipend |= SER_INT_RXREADY;
574 uart_unlock(sc->sc_hwmtx);
576 ipend |= SER_INT_TXIDLE;
578 ipend |= SER_INT_SIGCHG;
580 return ((sc->sc_leaving) ? 0 : ipend);
584 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
585 int stopbits, int parity)
587 struct uart_bas *bas;
591 uart_lock(sc->sc_hwmtx);
592 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
593 uart_unlock(sc->sc_hwmtx);
598 ns8250_bus_probe(struct uart_softc *sc)
600 struct uart_bas *bas;
601 int count, delay, error, limit;
602 uint8_t lsr, mcr, ier;
606 error = ns8250_probe(bas);
611 if (sc->sc_sysdev == NULL) {
612 /* By using ns8250_init() we also set DTR and RTS. */
613 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
615 mcr |= MCR_DTR | MCR_RTS;
617 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
622 * Set loopback mode. This avoids having garbage on the wire and
623 * also allows us send and receive data. We set DTR and RTS to
624 * avoid the possibility that automatic flow-control prevents
625 * any data from being sent.
627 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
631 * Enable FIFOs. And check that the UART has them. If not, we're
632 * done. Since this is the first time we enable the FIFOs, we reset
635 uart_setreg(bas, REG_FCR, FCR_ENABLE);
637 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
639 * NS16450 or INS8250. We don't bother to differentiate
640 * between them. They're too old to be interesting.
642 uart_setreg(bas, REG_MCR, mcr);
644 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
645 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
649 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
653 delay = ns8250_delay(bas);
655 /* We have FIFOs. Drain the transmitter and receiver. */
656 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
658 uart_setreg(bas, REG_MCR, mcr);
659 uart_setreg(bas, REG_FCR, 0);
665 * We should have a sufficiently clean "pipe" to determine the
666 * size of the FIFOs. We send as much characters as is reasonable
667 * and wait for the the overflow bit in the LSR register to be
668 * asserted, counting the characters as we send them. Based on
669 * that count we know the FIFO size.
672 uart_setreg(bas, REG_DATA, 0);
679 * LSR bits are cleared upon read, so we must accumulate
680 * them to be able to test LSR_OE below.
682 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
686 ier = uart_getreg(bas, REG_IER) & 0xf0;
687 uart_setreg(bas, REG_IER, ier);
688 uart_setreg(bas, REG_MCR, mcr);
689 uart_setreg(bas, REG_FCR, 0);
694 } while ((lsr & LSR_OE) == 0 && count < 130);
697 uart_setreg(bas, REG_MCR, mcr);
700 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
703 if (count >= 14 && count <= 16) {
704 sc->sc_rxfifosz = 16;
705 device_set_desc(sc->sc_dev, "16550 or compatible");
706 } else if (count >= 28 && count <= 32) {
707 sc->sc_rxfifosz = 32;
708 device_set_desc(sc->sc_dev, "16650 or compatible");
709 } else if (count >= 56 && count <= 64) {
710 sc->sc_rxfifosz = 64;
711 device_set_desc(sc->sc_dev, "16750 or compatible");
712 } else if (count >= 112 && count <= 128) {
713 sc->sc_rxfifosz = 128;
714 device_set_desc(sc->sc_dev, "16950 or compatible");
716 sc->sc_rxfifosz = 16;
717 device_set_desc(sc->sc_dev,
718 "Non-standard ns8250 class UART with FIFOs");
722 * Force the Tx FIFO size to 16 bytes for now. We don't program the
723 * Tx trigger. Also, we assume that all data has been sent when the
726 sc->sc_txfifosz = 16;
730 * XXX there are some issues related to hardware flow control and
731 * it's likely that uart(4) is the cause. This basicly needs more
732 * investigation, but we avoid using for hardware flow control
735 /* 16650s or higher have automatic flow control. */
736 if (sc->sc_rxfifosz > 16) {
746 ns8250_bus_receive(struct uart_softc *sc)
748 struct uart_bas *bas;
753 uart_lock(sc->sc_hwmtx);
754 lsr = uart_getreg(bas, REG_LSR);
755 while (lsr & LSR_RXRDY) {
756 if (uart_rx_full(sc)) {
757 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
760 xc = uart_getreg(bas, REG_DATA);
762 xc |= UART_STAT_FRAMERR;
764 xc |= UART_STAT_PARERR;
766 lsr = uart_getreg(bas, REG_LSR);
768 /* Discard everything left in the Rx FIFO. */
769 while (lsr & LSR_RXRDY) {
770 (void)uart_getreg(bas, REG_DATA);
772 lsr = uart_getreg(bas, REG_LSR);
774 uart_unlock(sc->sc_hwmtx);
779 ns8250_bus_setsig(struct uart_softc *sc, int sig)
781 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
782 struct uart_bas *bas;
789 if (sig & SER_DDTR) {
790 SIGCHG(sig & SER_DTR, new, SER_DTR,
793 if (sig & SER_DRTS) {
794 SIGCHG(sig & SER_RTS, new, SER_RTS,
797 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
798 uart_lock(sc->sc_hwmtx);
799 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
801 ns8250->mcr |= MCR_DTR;
803 ns8250->mcr |= MCR_RTS;
804 uart_setreg(bas, REG_MCR, ns8250->mcr);
806 uart_unlock(sc->sc_hwmtx);
811 ns8250_bus_transmit(struct uart_softc *sc)
813 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
814 struct uart_bas *bas;
818 uart_lock(sc->sc_hwmtx);
819 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
821 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
823 for (i = 0; i < sc->sc_txdatasz; i++) {
824 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
828 uart_unlock(sc->sc_hwmtx);