2 * Copyright (c) 2001 Cubical Solutions Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
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13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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26 /* capi/iavc/iavc.h The AVM ISDN controllers' common declarations.
34 /* max 4 units supported per machine */
36 #define IAVC_MAXUNIT 4
40 // The software context of one AVM T1 controller.
43 #define IAVC_IO_BASES 1
45 typedef struct i4b_info {
46 struct resource * io_base[IAVC_IO_BASES];
47 int io_rid [IAVC_IO_BASES];
48 struct resource * irq;
50 struct resource * mem;
54 typedef struct iavc_softc {
60 bus_space_handle_t sc_mem_bh;
61 bus_space_tag_t sc_mem_bt;
63 bus_space_handle_t sc_io_bh;
64 bus_space_tag_t sc_io_bt;
78 char sc_sendbuf[128+2048];
79 char sc_recvbuf[128+2048];
82 struct ifqueue sc_txq;
84 i4b_info_t sc_resources;
87 extern iavc_softc_t iavc_sc[];
89 #define iavc_find_sc(unit) (&iavc_sc[(unit)])
92 // {b1,b1dma,t1}_{detect,reset}
93 // Routines to detect and manage the specific type of card.
96 extern int b1_detect(iavc_softc_t *sc);
97 extern void b1_disable_irq(iavc_softc_t *sc);
98 extern void b1_reset(iavc_softc_t *sc);
100 extern int b1dma_detect(iavc_softc_t *sc);
101 extern void b1dma_reset(iavc_softc_t *sc);
103 extern int t1_detect(iavc_softc_t *sc);
104 extern void t1_disable_irq(iavc_softc_t *sc);
105 extern void t1_reset(iavc_softc_t *sc);
109 // Routines to access the memory mapped registers of the
110 // S5933 DMA controller.
113 static __inline u_int32_t AMCC_READ(iavc_softc_t *sc, int off)
115 return bus_space_read_4(sc->sc_mem_bt, sc->sc_mem_bh, off);
118 static __inline void AMCC_WRITE(iavc_softc_t *sc, int off, u_int32_t value)
120 bus_space_write_4(sc->sc_mem_bt, sc->sc_mem_bh, off, value);
124 // amcc_{put,get}_{byte,word}
125 // Routines to access the DMA buffers byte- or wordwise.
128 static __inline u_int8_t* amcc_put_byte(u_int8_t *buf, u_int8_t value)
134 static __inline u_int8_t* amcc_get_byte(u_int8_t *buf, u_int8_t *value)
140 static __inline u_int8_t* amcc_put_word(u_int8_t *buf, u_int32_t value)
142 *buf++ = (value & 0xff);
143 *buf++ = (value >> 8) & 0xff;
144 *buf++ = (value >> 16) & 0xff;
145 *buf++ = (value >> 24) & 0xff;
149 static __inline u_int8_t* amcc_get_word(u_int8_t *buf, u_int32_t *value)
152 *value |= (*buf++ << 8);
153 *value |= (*buf++ << 16);
154 *value |= (*buf++ << 24);
159 // Controller LLI message numbers.
162 #define SEND_POLL 0x72
163 #define SEND_INIT 0x11
164 #define SEND_REGISTER 0x12
165 #define SEND_DATA_B3_REQ 0x13
166 #define SEND_RELEASE 0x14
167 #define SEND_MESSAGE 0x15
168 #define SEND_CONFIG 0x71
169 #define SEND_POLLACK 0x73
171 #define RECEIVE_POLL 0x32
172 #define RECEIVE_INIT 0x27
173 #define RECEIVE_MESSAGE 0x21
174 #define RECEIVE_DATA_B3_IND 0x22
175 #define RECEIVE_START 0x23
176 #define RECEIVE_STOP 0x24
177 #define RECEIVE_NEW_NCCI 0x25
178 #define RECEIVE_FREE_NCCI 0x26
179 #define RECEIVE_RELEASE 0x26
180 #define RECEIVE_TASK_READY 0x31
181 #define RECEIVE_DEBUGMSG 0x71
182 #define RECEIVE_POLLDWORD 0x75
184 /* Operation constants */
186 #define WRITE_REGISTER 0x00
187 #define READ_REGISTER 0x01
189 /* Port offsets in I/O space */
192 #define B1_WRITE 0x01
193 #define B1_INSTAT 0x02
194 #define B1_OUTSTAT 0x03
195 #define B1_ANALYSE 0x04
196 #define B1_REVISION 0x05
197 #define B1_RESET 0x10
199 #define T1_FASTLINK 0x00
200 #define T1_SLOWLINK 0x08
202 #define T1_READ B1_READ
203 #define T1_WRITE B1_WRITE
204 #define T1_INSTAT B1_INSTAT
205 #define T1_OUTSTAT B1_OUTSTAT
206 #define T1_IRQENABLE 0x05
207 #define T1_FIFOSTAT 0x06
208 #define T1_RESETLINK 0x10
209 #define T1_ANALYSE 0x11
210 #define T1_IRQMASTER 0x12
211 #define T1_IDENT 0x17
212 #define T1_RESETBOARD 0x1f
214 #define T1F_IREADY 0x01
215 #define T1F_IHALF 0x02
216 #define T1F_IFULL 0x04
217 #define T1F_IEMPTY 0x08
218 #define T1F_IFLAGS 0xf0
220 #define T1F_OREADY 0x10
221 #define T1F_OHALF 0x20
222 #define T1F_OEMPTY 0x40
223 #define T1F_OFULL 0x80
224 #define T1F_OFLAGS 0xf0
226 #define FIFO_OUTBSIZE 256
227 #define FIFO_INPBSIZE 512
229 #define HEMA_VERSION_ID 0
230 #define HEMA_PAL_ID 0
233 // S5933 DMA controller register offsets in memory, and bitmasks.
236 #define AMCC_RXPTR 0x24
237 #define AMCC_RXLEN 0x28
238 #define AMCC_TXPTR 0x2c
239 #define AMCC_TXLEN 0x30
241 #define AMCC_INTCSR 0x38
242 #define EN_READ_TC_INT 0x00008000
243 #define EN_WRITE_TC_INT 0x00004000
244 #define EN_TX_TC_INT EN_READ_TC_INT
245 #define EN_RX_TC_INT EN_WRITE_TC_INT
246 #define AVM_FLAG 0x30000000
248 #define ANY_S5933_INT 0x00800000
249 #define READ_TC_INT 0x00080000
250 #define WRITE_TC_INT 0x00040000
251 #define TX_TC_INT READ_TC_INT
252 #define RX_TC_INT WRITE_TC_INT
253 #define MASTER_ABORT_INT 0x00100000
254 #define TARGET_ABORT_INT 0x00200000
255 #define BUS_MASTER_INT 0x00200000
256 #define ALL_INT 0x000c0000
258 #define AMCC_MCSR 0x3c
259 #define A2P_HI_PRIORITY 0x00000100
260 #define EN_A2P_TRANSFERS 0x00000400
261 #define P2A_HI_PRIORITY 0x00001000
262 #define EN_P2A_TRANSFERS 0x00004000
263 #define RESET_A2P_FLAGS 0x04000000
264 #define RESET_P2A_FLAGS 0x02000000
267 // (B1IO_WAIT_MAX * B1IO_WAIT_DLY) is the max wait in us for the card
268 // to become ready after an I/O operation. The default is 1 ms.
271 #define B1IO_WAIT_MAX 1000
272 #define B1IO_WAIT_DLY 1
276 // Diagnostic output routine, returns the written value via
277 // the device's analysis register.
280 // Returns nonzero if data is readable from the card via the
284 // Returns nonzero if data can be written to the card via the
288 static __inline u_int8_t b1io_outp(iavc_softc_t *sc, int off, u_int8_t val)
290 bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, off, val);
292 return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_ANALYSE);
295 static __inline int b1io_rx_full(iavc_softc_t *sc)
297 u_int8_t val = bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_INSTAT);
301 static __inline int b1io_tx_empty(iavc_softc_t *sc)
303 u_int8_t val = bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_OUTSTAT);
308 // b1io_{get,put}_{byte,word}
309 // Routines to read and write the device I/O registers byte- or
312 // b1io_{get,put}_slice
313 // Routines to read and write sequential bytes to the device
317 u_int8_t b1io_get_byte(iavc_softc_t *sc);
318 int b1io_put_byte(iavc_softc_t *sc, u_int8_t val);
320 int b1io_save_put_byte(iavc_softc_t *sc, u_int8_t val);
322 u_int32_t b1io_get_word(iavc_softc_t *sc);
323 void b1io_put_word(iavc_softc_t *sc, u_int32_t val);
325 int b1io_get_slice(iavc_softc_t *sc, u_int8_t *dp);
326 void b1io_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len);
329 // b1io_{read,write}_reg
330 // Routines to read and write the device registers via the I/O
334 u_int32_t b1io_read_reg(iavc_softc_t *sc, int reg);
335 u_int32_t b1io_write_reg(iavc_softc_t *sc, int reg, u_int32_t val);
339 // I/O port write operation for the T1, which does not seem
340 // to have the analysis port.
343 static __inline void t1io_outp(iavc_softc_t *sc, int off, u_int8_t val)
345 bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, off, val);
348 static __inline u_int8_t t1io_inp(iavc_softc_t *sc, int off)
350 return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, off);
353 static __inline int t1io_isfastlink(iavc_softc_t *sc)
355 return ((bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, T1_IDENT) & ~0x82) == 1);
358 static __inline u_int8_t t1io_fifostatus(iavc_softc_t *sc)
360 return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, T1_FIFOSTAT);
363 int t1io_get_slice(iavc_softc_t *sc, u_int8_t *dp);
364 void t1io_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len);
367 // An attempt to bring it all together:
368 // ------------------------------------
370 // iavc_{read,write}_reg
371 // Routines to access the device registers via the I/O port.
373 // iavc_{read,write}_port
374 // Routines to access the device I/O ports.
376 // iavc_tx_empty, iavc_rx_full
377 // Routines to check when the device has drained the last written
378 // byte, or produced a full byte to read.
380 // iavc_{get,put}_byte
381 // Routines to read/write byte values to the device via the I/O port.
383 // iavc_{get,put}_word
384 // Routines to read/write 32-bit words to the device via the I/O port.
386 // iavc_{get,put}_slice
387 // Routines to read/write {length, data} pairs to the device via the
388 // ubiquituous I/O port. Uses the HEMA FIFO on a T1.
391 #define iavc_read_reg(sc, reg) b1io_read_reg(sc, reg)
392 #define iavc_write_reg(sc, reg, val) b1io_write_reg(sc, reg, val)
394 #define iavc_read_port(sc, port) \
395 bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, (port))
396 #define iavc_write_port(sc, port, val) \
397 bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, (port), (val))
399 #define iavc_tx_empty(sc) b1io_tx_empty(sc)
400 #define iavc_rx_full(sc) b1io_rx_full(sc)
402 #define iavc_get_byte(sc) b1io_get_byte(sc)
403 #define iavc_put_byte(sc, val) b1io_put_byte(sc, val)
404 #define iavc_get_word(sc) b1io_get_word(sc)
405 #define iavc_put_word(sc, val) b1io_put_word(sc, val)
407 static __inline u_int32_t iavc_get_slice(iavc_softc_t *sc, u_int8_t *dp)
409 if (sc->sc_t1) return t1io_get_slice(sc, dp);
410 else return b1io_get_slice(sc, dp);
413 static __inline void iavc_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
415 if (sc->sc_t1) t1io_put_slice(sc, dp, len);
416 else b1io_put_slice(sc, dp, len);
421 // Interrupt handler, called by the bus specific interrupt routine
422 // in iavc_<bustype>.c module.
425 // CAPI callback. Resets device and loads firmware.
428 // CAPI callback. Registers an application id.
431 // CAPI callback. Releases an application id.
434 // CAPI callback. Sends a CAPI message. A B3_DATA_REQ message has
435 // m_next point to a data mbuf.
438 extern void iavc_handle_intr(iavc_softc_t *);
439 extern int iavc_load(capi_softc_t *, int, u_int8_t *);
440 extern int iavc_register(capi_softc_t *, int, int);
441 extern int iavc_release(capi_softc_t *, int);
442 extern int iavc_send(capi_softc_t *, struct mbuf *);
444 extern void b1isa_setup_irq(struct iavc_softc *sc);
446 #endif /* _CAPI_IAVC_H_ */