2 * Copyright (c) 2001 Cubical Solutions Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 /* capi/iavc/iavc_card.c
27 * The AVM ISDN controllers' card specific support routines.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
37 #include <sys/socket.h>
41 #include <machine/bus.h>
42 #include <machine/resource.h>
46 #include <i4b/include/i4b_debug.h>
47 #include <i4b/include/i4b_ioctl.h>
48 #include <i4b/include/i4b_trace.h>
50 #include <i4b/include/i4b_global.h>
51 #include <i4b/include/i4b_l3l4.h>
52 #include <i4b/include/i4b_mbuf.h>
54 #include <i4b/capi/capi.h>
56 #include <i4b/capi/iavc/iavc.h>
59 // AVM B1 (active BRI, PIO mode)
62 int b1_detect(iavc_softc_t *sc)
64 if ((iavc_read_port(sc, B1_INSTAT) & 0xfc) ||
65 (iavc_read_port(sc, B1_OUTSTAT) & 0xfc))
68 b1io_outp(sc, B1_INSTAT, 0x02);
69 b1io_outp(sc, B1_OUTSTAT, 0x02);
70 if ((iavc_read_port(sc, B1_INSTAT) & 0xfe) != 2 ||
71 (iavc_read_port(sc, B1_OUTSTAT) & 0xfe) != 2)
74 b1io_outp(sc, B1_INSTAT, 0x00);
75 b1io_outp(sc, B1_OUTSTAT, 0x00);
76 if ((iavc_read_port(sc, B1_INSTAT) & 0xfe) ||
77 (iavc_read_port(sc, B1_OUTSTAT) & 0xfe))
80 return (0); /* found */
83 void b1_disable_irq(iavc_softc_t *sc)
85 b1io_outp(sc, B1_INSTAT, 0x00);
88 void b1_reset(iavc_softc_t *sc)
90 b1io_outp(sc, B1_RESET, 0);
93 b1io_outp(sc, B1_RESET, 1);
96 b1io_outp(sc, B1_RESET, 0);
101 // Newer PCI-based B1's, and T1's, supports DMA
104 int b1dma_detect(iavc_softc_t *sc)
106 AMCC_WRITE(sc, AMCC_MCSR, 0);
108 AMCC_WRITE(sc, AMCC_MCSR, 0x0f000000);
110 AMCC_WRITE(sc, AMCC_MCSR, 0);
113 AMCC_WRITE(sc, AMCC_RXLEN, 0);
114 AMCC_WRITE(sc, AMCC_TXLEN, 0);
116 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
118 if (AMCC_READ(sc, AMCC_INTCSR) != 0)
121 AMCC_WRITE(sc, AMCC_RXPTR, 0xffffffff);
122 AMCC_WRITE(sc, AMCC_TXPTR, 0xffffffff);
123 if ((AMCC_READ(sc, AMCC_RXPTR) != 0xfffffffc) ||
124 (AMCC_READ(sc, AMCC_TXPTR) != 0xfffffffc))
127 AMCC_WRITE(sc, AMCC_RXPTR, 0);
128 AMCC_WRITE(sc, AMCC_TXPTR, 0);
129 if ((AMCC_READ(sc, AMCC_RXPTR) != 0) ||
130 (AMCC_READ(sc, AMCC_TXPTR) != 0))
133 iavc_write_port(sc, 0x10, 0x00);
134 iavc_write_port(sc, 0x07, 0x00);
136 iavc_write_port(sc, 0x02, 0x02);
137 iavc_write_port(sc, 0x03, 0x02);
139 if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x02) ||
140 (iavc_read_port(sc, 0x03) != 0x03))
143 iavc_write_port(sc, 0x02, 0x00);
144 iavc_write_port(sc, 0x03, 0x00);
146 if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x00) ||
147 (iavc_read_port(sc, 0x03) != 0x01))
150 return (0); /* found */
153 void b1dma_reset(iavc_softc_t *sc)
158 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
159 AMCC_WRITE(sc, AMCC_MCSR, 0);
160 AMCC_WRITE(sc, AMCC_RXLEN, 0);
161 AMCC_WRITE(sc, AMCC_TXLEN, 0);
163 iavc_write_port(sc, 0x10, 0x00); /* XXX magic numbers from */
164 iavc_write_port(sc, 0x07, 0x00); /* XXX the linux driver */
168 AMCC_WRITE(sc, AMCC_MCSR, 0);
170 AMCC_WRITE(sc, AMCC_MCSR, 0x0f000000);
172 AMCC_WRITE(sc, AMCC_MCSR, 0);
177 // AVM T1 (active PRI)
180 /* XXX how do these differ from b1io_{read,write}_reg()? XXX */
182 static int b1dma_tx_empty(int iobase)
183 { return inb(iobase + 3) & 1; }
185 static int b1dma_rx_full(int iobase)
186 { return inb(iobase + 2) & 1; }
188 static int b1dma_tolink(iavc_softc_t *sc, void *buf, int len)
191 char *s = (char*) buf;
194 while (!b1dma_tx_empty(sc->sc_iobase) && spin < 100000)
196 if (!b1dma_tx_empty(sc->sc_iobase))
198 t1io_outp(sc, 1, *s++);
203 static int b1dma_fromlink(iavc_softc_t *sc, void *buf, int len)
206 char *s = (char*) buf;
209 while (!b1dma_rx_full(sc->sc_iobase) && spin < 100000)
211 if (!b1dma_rx_full(sc->sc_iobase))
213 *s++ = t1io_inp(sc, 0);
218 static int WriteReg(iavc_softc_t *sc, u_int32_t reg, u_int8_t val)
221 if (b1dma_tolink(sc, &cmd, 1) == 0 &&
222 b1dma_tolink(sc, ®, 4) == 0) {
224 return b1dma_tolink(sc, &tmp, 4);
229 static u_int8_t ReadReg(iavc_softc_t *sc, u_int32_t reg)
232 if (b1dma_tolink(sc, &cmd, 1) == 0 &&
233 b1dma_tolink(sc, ®, 4) == 0) {
235 if (b1dma_fromlink(sc, &tmp, 4) == 0)
236 return (u_int8_t) tmp;
241 int t1_detect(iavc_softc_t *sc)
243 int ret = b1dma_detect(sc);
246 if ((WriteReg(sc, 0x80001000, 0x11) != 0) ||
247 (WriteReg(sc, 0x80101000, 0x22) != 0) ||
248 (WriteReg(sc, 0x80201000, 0x33) != 0) ||
249 (WriteReg(sc, 0x80301000, 0x44) != 0))
252 if ((ReadReg(sc, 0x80001000) != 0x11) ||
253 (ReadReg(sc, 0x80101000) != 0x22) ||
254 (ReadReg(sc, 0x80201000) != 0x33) ||
255 (ReadReg(sc, 0x80301000) != 0x44))
258 if ((WriteReg(sc, 0x80001000, 0x55) != 0) ||
259 (WriteReg(sc, 0x80101000, 0x66) != 0) ||
260 (WriteReg(sc, 0x80201000, 0x77) != 0) ||
261 (WriteReg(sc, 0x80301000, 0x88) != 0))
264 if ((ReadReg(sc, 0x80001000) != 0x55) ||
265 (ReadReg(sc, 0x80101000) != 0x66) ||
266 (ReadReg(sc, 0x80201000) != 0x77) ||
267 (ReadReg(sc, 0x80301000) != 0x88))
270 return 0; /* found */
273 void t1_disable_irq(iavc_softc_t *sc)
275 iavc_write_port(sc, T1_IRQMASTER, 0x00);
278 void t1_reset(iavc_softc_t *sc)
281 iavc_write_port(sc, B1_INSTAT, 0x00);
282 iavc_write_port(sc, B1_OUTSTAT, 0x00);
283 iavc_write_port(sc, T1_IRQMASTER, 0x00);
284 iavc_write_port(sc, T1_RESETBOARD, 0x0f);